Band-Pass Continuous-Time ΣΔ Modulators with Widely Tunable Notch Frequency for Efficient

RF-to-Digital Conversion Gerardo Molina-Salgado, Gordana Jovanovic-Dolecek

Department of Electronics Institute INAOE Puebla, Mexico

E-mail: gsalgado@inaoep.mx

José M. de la Rosa Institute of Microelectronics of Seville

IMSE-CNM (CSIC/Universidad de Sevilla) C/Américo Vespucio, 41092 Sevilla, SPAIN

E-mail: jrosa@imse-cnm.csic.es

Abstract—This paper presents a design methodology to synthesize band-pass continuous-time ΣΔ modulators with a widely programmable notch frequency for the efficient digitization of radio-frequency signals in the next generation of software-defined-radio mobile systems. The presented modulator architectures are based on a fourth-order loop filter – implemented with two LC-based resonators – and a finite-impulsive-response feedback loop to increase their flexibility and degrees of freedom, considering three different cases for the digital-to-analog converter waveform, namely: a return-to-zero, a non-return-to-zero and a raised-cosine waveform. In all cases, the notch frequency can be reconfigured from 0.1fs to 0.4fs, while keeping the noise shaping performance, stability and low sensitivity to circuit-element tolerances. This feature can be combined with undersampling techniques to achieve an efficient and robust digitization of 0.5-to-5GHz signals with scalable resolution and programmable signal bandwidth1.

I. INTRODUCTION Recent advances in Continuous-Time (CT) Sigma-Delta

Modulation (ΣΔM) techniques are pushing Radio-Frequency (RF) digitization forward, taking significant steps towards making Software-Defined-Radio (SDR) based smartphones a reality. The majority of reported RF digitizers are Band-Pass (BP) CT-ΣΔMs which include diverse strategies to reduce the required sampling frequency and mitigate the impact of interference signals, including frequency translation, out-of band embedded filtering and undersampling technique [1]–[6].

Most of BP CT-ΣΔMs intended for RF-to-digital conversion use a fixed center or notch frequency, fn, and vary the sampling frequency, fs, in order to tune the desired RF signal. However, one of the main inconveniences of this approach is that the RF receiver would require a widely programmable Voltage-Controlled Oscillator (VCO) in order to place the in-coming signal within the passband of the modulator. This issue has motivated the interest for reconfigurable BP CT-ΣΔMs with tunable notch frequency in these applications [3].

This paper contributes to this topic and presents the high-level synthesis of several fourth-order LC-based BP CT-ΣΔMs with a widely reconfigurable notch frequency, ranging from 0.1fs to 0.4fs. Three different cases of the feedback Digital-to-Analog-Converter (DAC) are considered as case studies, namely: a Return-to-Zero (RZ) waveform, a Non-Return-to-Zero (NRZ) waveform, and a raised-cosine waveform. In all cases, a Finite-Impulsive-Response (FIR) is used to increase the degree of programmability and to reduce the impact of clock-jitter error [3], [7]. These features are combined with a systematic design methodology which takes into account the variability of fn from the very beginning of the synthesis procedure, thus allowing us to increase the programmability of LC-based CT BP-ΣΔMs with respect to previously reported designs.

II. PROPOSED SYNTHESIS METHOD OF TUNABLE BP CT-ΣΔMS

Fig. 1 shows the block diagram of the BP CT-ΣΔM under study. It consists of a fourth-order single-loop topology made up of two LC-based resonators. The feedback loop is implemented by a RZ DAC and a two-tap half-delayed FIR structure realized with four coefficients m0, m1, i0, i1 in order to increase the degrees of freedom in the synthesis process when applying a CT-to-Discrete-Time (DT) transformation [7]. An additional feedback path, with gain c0, is included to compensate for an Excess Loop Delay (ELD) of z-1, thus giving a full sampling-period delay margin for the quantizer+DAC operation.

The modulator is synthesized by applying it a CT-to-DT transformation and using the well-known equivalency: ( ) ( ) · ( ) , (1)

where HDT(z) is the loop filter of a fourth-order BP DT-ΣΔM whose Noise Transfer Function (NTF) satisfies the required specifications in terms of Dynamic Range (DR) and Band-Width (BW). The well-known Schreier’s toolbox [8] can be used to obtain the desired NTF(z) for a given notch frequency,

This work was partially supported by the Spanish Ministry of Economyand Competitiveness (with support from the European RegionalDevelopment Fund) under contract TEC2010-14285/MIC and by CONACYT Mexico grant 179587.

566978-1-4799-0066-4/13/$31.00 ©2013 IEEE

Fig. 1 Block diagram of the BP CT-ΣΔM with RZ DAC under

study.

fn, and the loop filter transfer function can be easily derived as HDT(z) = 1 – 1/NTF(z).

H(s) and HFIR-DAC(s) are the transfer functions of the LC filter and the FIR-based DAC, respectively. In this case, as the FIR-based RZ DAC transfer function uses half-delay, modified Z-transform is a more suitable technique to compute (1) with delays, which are not integral multiples of the sampling time [7].

In order to calculate the modified Z-transform of (1), the residues theorem is usually considered, for the different resonator feedback paths, considering a constant value of fn, which is fn =fs/4 in the majority of cases. However, this method is not valid in those applications requiring a widely tunable fn, since the synthesized modulator is only stable within a very narrow band around fn. Alternatively, the presented methodology, referred to as a notch-frequency-aware synthesis, computes the modified Z-transform of each modulator loop-filter path considering that fn is variable, i.e. a design parameter. This way, a generic matrix expression is derived to get the loop-filter coefficients (m0, m1, i0, i1 and c0 in Fig. 1) as a function of fn.

Following this procedure, it can be shown that the numerators of the modified Z-transform of the different resonator feedback paths in Fig.1 can be expressed as: ( ) ( ( ) + ( ) + ( ) + ( ) ) , (2) ( ) ( ( ) + ( ) + ( ) + ( ) ) , (3) ( ) ( ( ) + ( ) + ( ) + ( ) ) , (4) ( ) ( ( ) + ( ) + ( ) + ( ) ) , (5) where ( ) 1 2 + 2 /8 , (6) ( ) 1 1 + 3 + /8 , (7) ( ) 1 1 + 2 3 + 2 /8 (8) ( ) 1 /8 , (9) ( ) 1 + , (10) ( ) 1 1 + + + + , (11) ( ) 1 + , (12) ( ) 1 , (13)

and v =fs/(2fn) stands for the normalized notch frequency.

Following the above procedure, a set of the modulator loop-filter coefficients can be derived as a function of fn. As an

illustration, Fig. 2(a) shows the variation of m0, m1, i0, i1 and c0 with the normalized notch frequency (fn/fs). Note that the values of these coefficients, specifically those of the main feedback path, tend to decrease as fn increases. This reduction in the values of the loop-filter coefficients causes a reduction of the DR, which becomes particularly critical for fn > fs/4. The opposite situation is given for fn < 0.15fs, for which the values of the loop-filter coefficients becomes relatively high compared to those obtained for fn = fs/4. As an illustration of this effect, Fig. 2(b) represents several Signal-to-Noise Ratio (SNR) versus input signal of Fig. 1, showing how the DR of the modulator is degraded as fn increases.

In order to keep DR constant with fn, the weight of the LC-based filters should be maintained over the entire fn range. However, using the modulator architecture shown in Fig. 1, the LC-based filter weight, w, varies with fn. To avoid this, additional loop-filter gains are needed to include the required degrees of freedom and hence, to find out the optimum set of loop-filter coefficients for each fn.

Thus, following the same synthesis procedure described above but considering that the gain of the LC-based filters has a fixed value of π/4, a new set of loop-filter coefficients less sensitive to the variation of fn can be found. The value of π/4 is chosen in such a way that the BP CT-ΣΔM of Fig. 1 keeps the DR for frequencies up-to fn=0.4fs.

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Fig. 2 Influence of fn on the performance of Fig. 1: (a) Variation of loop-filter coefficients. (b) DR degradation.

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Fig. 3 shows the proposed BP CT-ΣΔM which is basically the same topology of Fig. 1, except for the additional coefficient k, which accounts for the DR compensation. It can be shown that the value of this additional gain stage is given by: ( ) 4. (14)

Fig. 4 (a) illustrates the SNR vs input amplitude of Fig. 3 for several values of fn , where it can be noticed that the DR is preserved over the given range of fn (0.1fs-to-0.4fs in this case). Additionally, Fig. 4 (b) represents several output spectra of Fig. 3, showing how the noise-shaping performance is not degraded as fn increases.

Fig. 3 Proposed BP CT-Σ∆M with RZ DAC and increased fn tuning range.

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Fig. 4 Influence of fn on the performance of Fig. 3: (a) SNR vs. input amplitude, (b) Output spectra for an input amplitude of -16.5 dBFS..

III. EXTENSION TO BP CT-ΣΔMS WITH NRZ AND RAISED-COSINE DACS

The presented notch-frequency-aware synthesis method can be extended to BP CT-ΣΔMs with other kinds of DAC waveforms. As a case study, Fig. 5 shows the block diagram of a fourth-order BP CT-ΣΔM with FIR-based NRZ DAC. In this case, the CT-to-DT transformation of those branches that has a full clock delay, such as m0 and i0, are straightforward and can be obtained with the c2d function of the control toolbox in MATLAB. On the other hand, those branches with a fractional delay, such as m1 and i1, would require the use of the modified Z-transform as described in previous section. However, the c2d function in MATLAB can only convert delayed analog versions into digital ones, provided that the shape of the feedback is of the NRZ type. Therefore, all the required transformations in this case can be obtained by the use of c2d function in MATLAB. Similarly to the RZ-DAC case, the modulator in Fig. 5 is able to keep the same noise-shaping performance over a wide range of fn provided that k(v)=v/5 is used for the additional gain stage.

One of the main limitations of using squared waves DAC arises when undersampling is used in BP CT-ΣΔMs, since their performance is degraded due to the attenuation of the RF alias signal in the Nyquist band. These problems can be partially mitigated by using a raised-cosine DAC waveform [3], [7]. In this case, the tuning range of fn can be increased by following the same method discussed in previous sections with k(v)=v/8, giving rise to the modulator architecture shown in Fig. 6, which is able to tune its noise-shaping in a wide fn range, while keeping its stability and DR properties.

IV. APLICATION TO SDR AND SIMULATION RESULTS The main specifications of SDR mobile systems, involves

the digitization of a large number of wireless standards, whose RF signals have carrier frequencies ranging from 0.455GHz (CDMA) to 5.093GHz (WiMAX) and channel band-widths (Bw) varying from 0.2MHz (GSM) to 100MHz (LTE). These requirements impose very aggressive specifications for the modulator, particularly in terms of the sampling frequencies, which can be relaxed by using undersampling techniques [1]. The proposed modulators can cover the whole range of RF signals with a reconfigurable fs of 1, 2, 2.5 and 4GHz along with the widely programmable value of fn, ranging from 0.1fs to 0.4fs.

Fig. 5 Proposed BP CT-Σ∆M with NRZ DAC and increased fn tuning

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Taking into account these system requirements and specifications, the proposed modulator of Fig. 5 has been synthesized and simulated considering a 4-bit quantizer.

Fig. 7 shows the simulated SNR versus input signal for CDMA-450, LTE-700, and for WLAN 802.11Y, this later in undersampling mode, considering fs=2GHz in all cases. Note that for LTE-700 standard, the sampling frequency is less than 4fn but without entering in the undersampling mode. Thus, an additional advantage of the presented methodology, and the resulted modulators, is that they allow reducing the sampling frequency in BP CT-ΣΔM provided that 0.25<fn/fs≤0.4.

The modulators under study have been also simulated considering the effect of mismatch. As an illustration, Fig. 8 presents the histogram of SNR corresponding to a 200-run Monte Carlo simulation for CDMA-450, where a standard deviation of 10% in the coefficients has been considered in all loop-filter coefficients. It can be noted that the SNR shows a deviation of less than 3dB in the worst cases.

V. CONCLUSIONS A notch-frequency-aware synthesis methodology has been

presented for the design of LC-based BP CT-ΣΔMs with a widely programmable notch frequency. The proposed method allows us to extend the tuning range of the notch frequency up to 0.1fs to 0.4fs, while keeping the performance of the modulator in terms of dynamic range, stability and robustness with respect to the variability of its loop-filter coefficients.

Fig. 7 SNR vs input amplitude for different standards, considering fs=2GHz.

Fig. 8 Monte Carlo simulation considering a 10% variation of loop-filter

coefficients for CDMA-450, input amplitude of -16.5dBFS.

Different feedback FIR-based DACs, including RZ, NRZ and Raised-Cosine waveforms, have been considered in the presented study, resulting in suitable BP CT-ΣΔM topologies for the efficient implementation of RF digitizers in future generations of SDR mobile systems.

REFERENCES [1] A. Naderi, M. Sawan, and Y. Savaria, “On the Design of

Undersampling Continuous-Time Bandpass Delta-Sigma Modulators for Gigahertz Frequency A/D Conversion,” IEEE Trans. on Circuits and Systems – I Regular Papers, vol. 55, pp. 3488–3499, December 2008.

[2] N. Beilleau, H. Aboushady, F. Montaudon, and A. Cathelin, “A 1.3V 26mW 3.2GS/s Undersampled LC Bandpass ΣΔ ADC for a SDR ISMband Receiver in 130nm CMOS,” Proc. of the IEEE Radio Frequency Integrated Circuits Symp., 2009.

[3] S. Gupta et al., “A 0.8-2GHz Fully-Integrated QPLL-Timed Direct-RFSamplingBandpass ΣΔ ADC in 0.13_m CMOS,” IEEE J. of Solid-State Circuits, vol. 47, pp. 1141–1153, May 2012.

[4] J. Rychaert et al., “A 6.1GS/s 52.8mW 43dB DR 80MHz Bandwdith 2.4GHz RF Bandpass ΣΔ ADC in 40nm CMOS,” Proc. of the IEEE Radio Frequency Integrated Circuits Symp., pp. 443–446, June 2010.

[5] A. Ashry et al., “A 3.6GS/s, 15mW, 50dB SNDR, 28MHz Bandwidth RF ΣΔ ADC with FoM of 1pJ/bit in 130nm CMOS,” Proc. of the IEEE Custom Integrated Circuits Conf., September 2011.

[6] H. Shibata et al., “A DC-to-1GHz Tunable RF ΣΔ ADC Achieving DR=74dB and BW=150MHz at f0 =450MHz Using 550mW,” IEEE ISSCC Digest of Technical Papers, pp. 150–151, February 2012.

[7] N. Beilleau, H. Aboushady, and M. Loureat, “Using Finite Impulse Response Feedback DACs to design ΣΔ Modulators based on LC Filters,” Proc. of the IEEE Intl. Midwest Symp. on Circuits and Systems (MWSCAS), pp. 696–699, August 2005.

[8] R. Schreier, The Delta-Sigma Toolbox. [Online]. Available http://www.mathworks.com/matlabcentral/fileexchange/19.,2011.

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