1
CMOSCMOS INTEGRATED CIRCUIT DESIGN TECHNIQUESINTEGRATED CIRCUIT DESIGN TECHNIQUES
University of University of IoanninaIoannina
Embedded CoreEmbedded CoreEmbedded CoreEmbedded CoreEmbedded CoreEmbedded CoreTestingTesting
Embedded CoreEmbedded CoreTestingTesting
((ΙΕΕΕ ΙΕΕΕ 1500 Std. 1500 Std. –– SECT)SECT)((ΙΕΕΕ ΙΕΕΕ 1500 Std. 1500 Std. –– SECT)SECT)
Dept. of Computer Science and EngineeringDept. of Computer Science and Engineering
Y. Tsiatouhas
OverviewOverview
CMOS Integrated Circuit Design TechniquesCMOS Integrated Circuit Design Techniques
1.1. Basic SECT architectureBasic SECT architecture
2.2. The Wrapper Interface Port (WIP)The Wrapper Interface Port (WIP)
3.3. SECT registersSECT registers
4.4. Instruction setInstruction set
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 2
5.5. Parallel test access mechanismParallel test access mechanism
VLSI Systemsand Computer Architecture Lab
2
RAM AG
SystemSystem‐‐onon‐‐Chip (Chip (SoCSoC))
ChipCores
A main design paradigm in modernRAM
FlashDSP
RISCJTA
Clock
GSM Tm
Interr.C
Radio
Audio
RISCInt.
BUS
BUS
CMOS technologies is the developmentof Systems‐on‐a‐Chip (SoCs) wherereusable cores (digital, analog,memory) are embedded in a chip.
The used core designs are characterizedas:
• Soft (RTL code).Fi ( tli t)
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 3
RAMEBI
URTS
Perif. Int.
Data Int.
Contr. BUS
Cores
• Firm (netlist).• Hard (layout).
Design ParadigmsDesign Paradigms
Design and testdevelopment
Design and testdevelopment
System on Board System on Chip
rovider
Compone
Provid
e(Cores
Manufacturing
Test
Design and test Design and test
Components Pr
(ICs)
ator
ents
er s)
Syst
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 4
development
Manufacturing
Test
development
Manufacturing
Test
System
Integra tem
Integrato
r
3
RAM AG
Automatic Test Equipment SupportAutomatic Test Equipment Support
Chip
AutomaticAutomatic TestTest EquipmentEquipment: Hardware
ATESource Test Access Mechanism (TAM)
RAM
FlashDSP
RISC
JTA
Clock
GSM Tm
Interr.C
Radio
Audio
RISCInt.
BUS
US
equipment for the testing and diagnosisof integrated circuits under the controlof proper software. An ΑΤΕ provides testdata (test source) and monitors the testresponses (response sink)
TestTest AccessAccess MechanismMechanism: Circuitryembedded in the chip to support thet f f t t d t b t th ATE
Core Under Test
Embedded Core Testing (ΙΕΕΕ 1500 ‐ SECT std) 5
RAMEBI
URTS
Perif. Int.
Data Int.
Contr. BU transfer of test data between the ATE
and the chip.
ATESink
Test Access Mechanism (TAM)
RAM AG
Automatic Test Equipment + Automatic Test Equipment + BISTBIST
Chip
Built‐In Self Test (BIST) circuits can be
Test Access Mechanism (TAM)ATE
Source
RAM
FlashDSP
RISC
JTA
Clock
GSM Tm
Interr.C
Radio
Audio
RISCInt.
BUS
US
exploited for embedded test datageneration and test responsemonitoring. Thus, the ΑΤΕ complexity isdrastically reduced and the samestands for the required bandwidth totransfer test data in/out the chip.The ΑΤΕ activates the BIST circuitry andreceives the final test decision.
Core Under Test
BISTSource
Embedded Core Testing (ΙΕΕΕ 1500 ‐ SECT std) 6
RAMEBI
URTS
Perif. Int.
Data Int.
Contr. BU
Test Access Mechanism (TAM)
BISTSink
ATESink
4
Basic IEEE 1500Basic IEEE 1500 Architecture Architecture (Ι)(Ι)
The IEEE 1500 Embedded Core Testingstandard supports the testing processof embedded cores in a chip,according to a common DFT and test
Wrapper
TAM‐In(WPI[0:r])
TAM‐Out(WPO[0:m])
WrapperBoundaryRegister(WBR)
Core
according to a common DFT and testapplication methodology.
It consists of a test wrapper around acore and provides the followingfacilities:
• A Wrapper Interface Port ‐ WIPwith 6 inputs for control signalsplus 1 serial test data input and 1
WrapperSerialInput
WSI
CoreWrapperCells
WrapperBypassRegister(WBY)
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 7
p pserial test data output.
• A set of registers.WrapperSerialOutput
WrapperInterfacePort
WSO
…
WIP[0:5]
WrapperInstructionRegister(WIR)
In the normal mode of operation the IEEE1500 std. circuitry is “transparent”.
Basic IEEE 1500Basic IEEE 1500 Architecture Architecture (ΙΙ)(ΙΙ)
TAM‐In(WPI[0:r])
TAM‐Out(WPO[0:m])
Optional TestingPorts
There are three modes of operation:• Normal Operation: where thewrapper is transparent.
• Core Internal Testing: where theinternal core logic is under test
Core
WSI
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 8
internal core logic is under test.• Core External Testing: where theinterconnects between the cores andthe glue logic are tested.
WSI
WSO
…
WIP[0:5]All protocol signals
(WPI, WPO, WSI, WSO, WIP) are managed either by the BIST or the ATE
5
CorePI PO
WBR
. . .. . .
Wrapper RegistersWrapper Registers
The IEEE 1500 protocol
supports the following
WBR
Decode Logic
WMUX‐1
WMUX‐2
Scan Chain 0
supports the followingregisters:
• Wrapper Bypass Register (WBY).
• Wrapper Instruction Register (WIR).
• Wrapper Boundary register (WBR)0
R
Scan Chain 1
WBY
WPI WPO
. . .
WDRs
CDRs
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 9
WSO
WIR
Decode Logic
WSI
SelectWIRShiftWRUpdateWRCaptureWRWrapper
(WBR).
• Various Data Registers (WDR/CDR).
1
0
SelectWIR
WRCKWRSTN
WIP[0:5]
. . . WIR Circuitry
Wrapper Interface Port Wrapper Interface Port –– WIP (I)WIP (I)
Core
WrapperWrapper
WRSTNUpdate WR
Shift WRCapture WR
Select WIRWRCK
WIPControls& Clocks
• SelectWIR (Select Wrapper Instruction Register) Signal which controls the
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 10
• SelectWIR (Select Wrapper Instruction Register): Signal which controls theoperation of the WIP port. When active (high) the WIR register is connectedbetween the WSI and WSO pins else another register (WBY, WBR, WDR,CDR …) is connected according to the instruction in the WIR register.
6
• ShiftWR (Wrapper Shift): Enable signal for the shift operations on the WIRregister (when SelectWIR=high) or another register (when SelectWIR=low)according to the instruction in the WIR register
Wrapper Interface Port Wrapper Interface Port –– WIP (II)WIP (II)
according to the instruction in the WIR register.• CaptureWR (Wrapper Capture): Enable signal for the parallel load of data in
the WIR register (when SelectWIR=high) or another register (whenSelectWIR=low) according to the instruction in the WIR register.
• UpdateWR (Wrapper Update): Enable signal for the update of the WIRregister (when SelectWIR=high) or another register (when SelectWIR=low)according to the instruction in the WIR register.
• WRCK (Wrapper Clock): Clock signal for the operation of the WIR and WBY
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 11
registers or other registers of the wrapper (e.g. WBR) or even the core.• WRSTN (Wrapper Reset): Asynchronous reset signal (active‐low) of the WIR
register or other registers of the wrapper.
Wrapper Registers’ ArchitectureWrapper Registers’ Architecture
CDR z
Core1500 SIL
WPOWPI
1
0
WBY
WDR s
WBR
WBY_WSO
WMUX‐1
n
1
WMUX‐2
WSO
… …
DR_WSO
WBR_WSO
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 12
WIR CircuitryWIR_WSO
DR_Select[0:log2n]
WBY_Cntrl
WBR_C
ntrl
WDR_C
ntrl
CDR_C
ntrl
Core_C
ntrl
WSI
WIP[0:5]
Select_WIR
7
Wrapper Bypass Register Wrapper Bypass Register –– WBYWBY
• TheWrapper Bypass Register – WBY is an one stage register. When this registeris enabled, the signal at the WSI input port bypasses every other register andis enabled, the signal at the WSI input port bypasses every other register anddirectly feeds the WSO output port.
WSIWBY_WSOSerial Shift
StageFF
WBY_Cntrl
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 13
WRCK
WBY
Wrapper Instruction Register Wrapper Instruction Register –– WIRWIR
• The Wrapper Instruction Register – WIR is a serial/parallel input and outputregister. It consists of two stages: a flip‐flop based serial shift stage and a latchbased update/decode stage. Every flip‐flop drives a latch. The latch retainsthe current instruction when the register is fed with new data (instructions)the current instruction when the register is fed with new data (instructions).
S[0]. . .WSI WIR_WSO
Optional Parallel Capture Inputs (WPI of TAM)
S[1]S[k]
ShiftWR
CaptureWR
Serial ShiftStage
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 14
. . .
k 3
Update and Decode
DR_Select[0:log2n]
WBY_C
ntrl
WBR_C
ntrl
WDR_C
ntrl
CDR_C
ntrl
Core_C
ntrl
WRSTN
WRCKUpdateWR
SelectWIR
8
WRCK
WIR Timing DiagramsWIR Timing Diagrams
WIR Shift and Update Operations
WRCK
SelectWIR
ShiftWR
UpdateWR
WIR Shift Register
Data Shift
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 15
WIR Update Register
Instruction Register UpdateInstruction Decoding
Wrapper Boundary Register Wrapper Boundary Register –– WBRWBR
• TheWrapper Boundary Register ‐WBR lies at the core boundary, between theinput‐output pins and the internal core logic. It consists of the WrapperBoundary Cells ‐ WBC and contributes to the testing of the internal core logic
ll h i f h i h h i h hias well as the interconnects of the core with other cores in the chip.
0from chip
to core
sc
scan‐in
wci
MUX
MUX
WBC
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 16
0
1
1
clk scan‐out
MUX
MUX
MM
To next WBCor WBR_WSO
From previous WBCor WSI
FFFF
wrapper input cell
9
The multiplexers of the WBR cells are controlled by the sc (scan) signal, which isalso used to control the core’s scan chains, and the wci (wco) signal for the inputcell (output cell). The value of the wci (wco) signal is defined by the decoding of
Wrapper Boundary Register Wrapper Boundary Register –– WBRWBR
the instruction inside the WIR. In addition, the clock clk signal of the core is usedto drive the flip‐flop of the cell.
0from core
to chip
sc
scan‐in
wco
MUX
MUX
WBC
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 17
0
1
1
clk scan‐out
MUX
MUX
MM
FFFF
wrapper output cellTo next WBCor WBR_WSO
From previous WBCor WSI
IEEE 1500 std. InstructionsIEEE 1500 std. Instructions
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 18
10
Scan Chain 0
Scan Chain 1si[0:1] so[0:1]
The CoreThe Core
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]q[0]
q[1]q[1]
d[0]d[0]
d[1]d[1]d[2]d[2]
d[3]d[3]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 19
d[4]q[2]q[2]q[2]
d[4]d[4]
scsc clkclk
sc clk
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
IEEE 1500IEEE 1500 Wrapper Compliant CoreWrapper Compliant Core
m5 m9
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]q[0]
q[1]q[1]
d[0]d[0]
d[1]d[1]d[2]d[2]
d[3]d[3]
WPO[0:2]
CoreCore
m2
m3
m4
m6
m7
m10
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 20
WBY
WIR
d[4]q[2]q[2]q[2]
d[4]d[4]
scsc clkclk
WSI WSO
WIP[0:5]Wrapper
scclk
m1m8
m11m12
11
The WThe WBBYPASS InstructionYPASS Instruction
The mandatory WBYPASS instruction provides two non‐conflicting modes ofoperation: the normal mode and the bypass mode.p yp
This instruction configures the WBCs for the normal mode of operation and inparallel connects the WBY register between the WSI and WSO ports so thatduring test operations the core is bypassed to provide fast test data access toother cores in the chip.
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 21
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Normal Mode of Operation Normal Mode of Operation –– WWBBYPASSYPASS
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 22
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
scclk
WSI WSO
WIP[0:5]Wrapper
12
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Serial Bypass Serial Bypass –– WWBBYPASSYPASS
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 23
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
WSI WSO
WIP[0:5]Wrapper
scclk
The WThe WCCOREORETTESTESTS S InstructionInstruction
The WCORETESTS instruction is utilized for the serial internal core testing.
This instruction connects the WBR register and the internal core scan chains to aThis instruction connects the WBR register and the internal core scan chains to aunified scan chain between the WSI and WSO ports.
Test data, from the test control unit (BIST or ΑΤΕ), are scanned‐in to the wrapperinput boundary cells of the WBR and the scan chains and they are applied to thecore’s logic. Next, the core’s responses are captured at the scan chains and thewrapper output boundary cells of the WBR and they are scanned‐out to the testcontrol unit (BIST or ATE) for processing.
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 24
13
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Serial Serial InTestInTest –– WWCCOREORETTESTESTSS (Ι)(Ι)
ScanScan‐‐in phasein phase
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 25
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
WSI WSO
WIP[0:5]Wrapper
scclk
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Test applicationTest application
Serial Serial InTestInTest –– WWCCOREORETTESTESTSS (Ι(ΙII))
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 26
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
WSI WSO
WIP[0:5]Wrapper
scclk
14
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Response CaptureResponse Capture& Scan& Scan‐‐out phaseout phase
Serial Serial InTestInTest –– WWCCOREORETTESTESTSS (Ι(ΙIIII))
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 27
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
WSI WSO
WIP[0:5]Wrapper
scclk
The WThe WCCOREORETTESTESTWS WS InstructionInstruction
The WCORETESTWS instruction is almost identical to the WCORETESTSinstruction. The difference is that the core scan chains are not utilized and onlyythe WBR is exploited for the scan operations.
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 28
15
The WThe WEEXXTTESTESTS S InstructionInstruction
The mandatory WEXTESTS instruction is utilized during the serial external testingof the core interconnects with other cores in the chip.p
This instruction provides controllability and observability over the glue logicsurrounding the core.
The instruction exclusively connects the WBR between the WSI and WSO ports.The wrapper output boundary cells of the WBR are exploited to provide testdata, while the wrapper input boundary cells of the WBR are used to capture thetest responses. The test data are serially transferred between the test controller(BIST or ΑΤΕ) and the WBR.
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 29
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Serial Serial ExTestExTest –– WWEEXXTTESTESTSS (Ι)(Ι)
ScanScan‐‐in phasein phase
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 30
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
WSI WSO
WIP[0:5]Wrapper
scclk
16
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Test applicationTest application
Serial Serial ExTestExTest –– WWEEXXTTESTESTSS (Ι(ΙII))
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 31
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
WSI WSO
WIP[0:5]Wrapper
scclk
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Response CaptureResponse Capture& Scan& Scan‐‐out phaseout phase
Serial Serial ExTestExTest –– WWEEXXTTESTESTSS (Ι(ΙIIII))
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 32
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
WSI WSO
WIP[0:5]Wrapper
scclk
17
The WThe WCCOREORETTEST InstructionEST Instruction
The WCORETEST instruction is utilized for the parallel internal core testing.
This instruction exploits the parallel (user defined) ΤΑΜ to scan‐in/out in paralleld /f h WBR d h h itest data to/from the WBR and the scan chains.
The instruction connects the WBR between a dedicated input of the WPI portand a dedicated output of the WPO port. Similarly, connects the scan chain (if it
is required) between dedicated inputs of the WPI port and dedicated outputs of
the WPO port.
The test data are concurrently scanned‐in from the test controller (BIST or ΑΤΕ)to the wrapper input boundary cells of the WBR and the scan chains and they
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 33
are applied to the core logic. Next, the test responses are captured at the scanchains and the wrapper output boundary cells of the WBR and then concurrentlyscanned‐out to the test controller (BIST or ATE) for processing.
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Parallel Parallel InTestInTest –– WWCCOREORETTESTEST (Ι)(Ι)
ScanScan‐‐in phasein phase
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 34
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
WSI WSO
WIP[0:5]Wrapper
scclk
18
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Test applicationTest application
Parallel Parallel InTestInTest –– WWCCOREORETTESTEST (Ι(ΙII))
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 35
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
WSI WSO
WIP[0:5]Wrapper
scclk
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Response CaptureResponse Capture& Scan& Scan‐‐out phaseout phase
Parallel Parallel InTestInTest –– WWCCOREORETTESTEST (Ι(ΙIIII))
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 36
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
WSI WSO
WIP[0:5]Wrapper
scclk
19
The WThe WEEXXTTESTESTP P InstructionInstruction
The WEXTESTP instruction is utilized for the parallel external testing of the coreinterconnects with other cores in the chip.p
The instruction provides controllability and observability of the glue logicsurrounding the core.
The test data are scanned‐in in parallel from the test controller (BIST or ΑΤΕ) tothe wrapper output boundary cells of the WBR. The wrapper input boundarycells of the WBR are used to capture the test responses which are scanned‐outin parallel to the test controller (BIST or ΑΤΕ) for processing.
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 37
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Parallel Parallel ExTestExTest –– WWEEXXTTESTESTPP (Ι)(Ι)
Test applicationTest application
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 38
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
WSI WSO
WIP[0:5]Wrapper
scclk
20
Scan Chain 0
Scan Chain 1WPI[0:2]WPO[0:2]
Response CaptureResponse Capture
Parallel Parallel ExTestExTest –– WWEEXXTTESTESTPP (Ι(ΙII))
d[0]
d[1]d[2]
d[3]
q[0]
q[1]
q[0]
q[1]
d[0]
d[1]d[2]
d[3]
WPO[0:2]
CoreCore
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 39
WBY
WIR
d[4]q[2]q[2]
d[4]
sc clk
WSI WSO
WIP[0:5]Wrapper
scclk
Instructions and MUX SettingsInstructions and MUX Settings
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 40
Pattern loaded in the WIR
WIR decoder signals to control the multiplexers
X = don’t care value
21
Parallel TAM Configurations Parallel TAM Configurations
Core 1
SoC
Core 1
SoC
NCore 1
SoC
N1N1
PI 1 O1
WPI1 WPI1 WPO1
Core 2N N Core 2 Core 2
N2N2
WP
WP
WPI 2
WPO
2
WPO1
WPI2
WPO2
WPI2WPO2
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 41
Core 3 Core 3
N
Core 3N3
N3
MultiplexedMultiplexed DaisychainDaisychain DistributedDistributed
WPI 3
WPO
3
WPI3
WPO3
WPI3 WPO3
WPI WPIWPO WPO
User Defined Parallel TAMfrom Source to Sink
IEEE 1500 Chip ArchitectureIEEE 1500 Chip Architecture
Core 1
IEEE 1500 Wrapper
WIR
Core N
IEEE 1500 Wrapper
WIR
FunctionalInputs 1
FunctionalInputs N
FunctionalOutputs 1
FunctionalOutputs N
WSI1 WSINWSO1 WSON
WPI1 WPINWPO1 WPON
. . .. . .
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 42
JTAG & Test Controller
WIP[0:5]
Serial TAM Serial TAM
TDI TDO
TMS
TCK TRSTN
SoC
22
ReferencesReferences
• IEEE 1500 Standard for Embedded Core Test (http://grouper.ieee.org/groups/1500/).
• “Testing Embedded Core‐Based System Chips,” Y. Zorian, E.J. Marinissen and S. Dey, IEEEComputer, June 1999.
• “Towards a Standard for Embedded Core Test,” E.J. Marinissen, Y. Zorian, R. Kapur, T.Taylor and L. Whetsel, IEEE Int. Test Conference (ITC), Sept. 1999.
• “On Using IEEE P1500 SECT for Test Plug‐n‐Play,” E.J. Marinissen, R. Kapur and Y. Zorian,IEEE Int. Test Conference (ITC), Oct. 2000.
• “System Chip Test: How will it Impact your Design?,” Y. Zorian and E.J. Marinissen, ACMDesign Automation Conference (DAC), 2000.
• “ETM10 Incorporates Hardware Segment of IEEE P1500,” T. McLaurin and S. Ghosh, IEEEd f
Embedded Core Testing (ΙΕΕΕ 1500 - SECT std) 43
Design and Test of Computers, pp. 8‐13, May‐June 2002.
• “On IEEE P1500’s Standard for Embedded Core Test,” E.J. Marinissen, R. Kapur, M.Lousberg, T. McLaurin, M. Ricchetti and Y. Zorian, Journal of Electronic Testing: Theoryand Applications (JETTA), vol. 18, pp. 365‐383, 2002.
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