COMPLEX ORIENTED COHOMOLOGY THEORIES AND THE LANGUAGE OF STACKS
Schottky Barrier Heigh oriented process integration 2012
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Transcript of Schottky Barrier Heigh oriented process integration 2012
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Schottky barrier height oriented fabrication process integration
James M.M. Chu, PhDDepartment of Engineering Science
NCKU
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Three transportation mechanisms for electrical carriers in MS interface
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Types of electrical carrier transportation behaviors vs. dopant
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Contact resistivity vs. Schottky barrier height along dopant density
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Metal Silicide
N-Type Semiconductor
Metal Silicide
P-Type Semiconductor
N-type semiconductor ΦM > ΦS P-type semiconductor ΦM < ΦS
ΦBnelectron
Bn: SBH for n-MOS
Bp: SBH for p-MOS
EC
EF
EVhole
EC : Si conduction band
EF : Effective Si SBH
Ev : Si valence band
ΦBp
(a) (b)
Figure 2.4 Schottky barrier heights vs. carrier transport (a) nMOS, (b) pMOS [67]
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Silicide
Source / Drain
electron
Silicide Si S/DInterface
hole
RCSD
WF Bn
RspreadRs
Bp
WF
(a) (b)
Figure 2.5 (a) Metal silicide as MS contact (b) resistive path of MS contact
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Table 2.1 Characteristic of C54-TsSi2, CoSi2 and NiSi for CMOS application [50]
C54-TiSi2 CoSi2 NiSi
Formation Temperature (℃) 600-700 600-700 400-600
Thin film resistivity (μΩ-cm) 13-20 14-20 14-20
Schottky barrier height (n-Si, eV) 0.6 0.64 0.67
Dominant moving species Si Co Ni
Si consumption ratio 2.27 3.64 1.83
Silicide thickness ratio 2.51 3.52 2.34
Melting point (℃) 1500 1326 992
Eutectic point (℃) 1330 1204 964
Thermal stability temperature (℃) < 950 900 700
Epitaxy on Silicon No Yes No
Reduction of SiO2 Yes No No
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Phase Thin film resistivity(μΩ-cm)
Melting ortransformation/melting (℃)
Ni 7~10 1455
Ni3Si 80~90 1035/1170
Ni31Si12 90~150 1242
Ni2Si 24~30 1255/1306
Ni3Si2 60~70 830/845
NiSi 10.5~18 992
NiSi2 34~50 981/993
Si Dopant Dependent 1414
Electrical and thermal characters of nickel silicide on different phases
(NixSiy)
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Phase Thin film resistivity(μΩ-cm)
Melting ortransformation/melting (℃)
IrSi 500 1707
Ir3Si5 4000 1402
Pt2Si 14-16 1100PtSi 28-35 1229IrSi3 350-580 1260
DySi2-x 250-380 1550
ErSi2-x 30 1620
YbSi2-x 34 1425
Electrical and thermal characters of metal silicide alternatives
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Parasitic resistance reductions engineering on NiSi contact silicide
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Summary of impurity additive enhanced NiSi thermal stability
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PAI for silicide zone definition
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Experimental workfunction of metal silicide
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Metal additives for silicide work function adjustments
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Ideal situation of dopant allocations at silicide/silicon interface
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Band edge engineering through dipole layer on (a) nMOS, (b) pMOS
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Element ionization energy for Si
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Summary of DS effects on silicide-silicon SBH adjustment
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Silicide-Si contacts for parasitic resistance reduction
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The overlap of options / optimization
Consideration of the impurity material selection
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Schematic illustrations of the metal/semiconductor contact
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Parasitic resistivity reductions through SBH modulation techniques
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Ideal situations of impurity distribution in NiSi-interface-Si
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Process technologies for CMOS contact silicide resistivity scaling
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Summary
• SBH lowering dominate future scaling of transistor contact resistivity.
• Impurity additive as key for new Ohmic contact engineering.
• Impurity spatial allocation in M-S interface dominate the process design approach.
• Three technology lines for process integration: Wafer substrate, silicide material and interface engineering