Pipeline: Ένα παράδειγμα από ….τη καθημερινή ζωή

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    30-Dec-2015
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Pipeline: Ένα παράδειγμα από ….τη καθημερινή ζωή. Σειριακή προσέγγιση για 4 φορτία = 8 h. Πλυντήριο Στεγνωτήριο Δίπλωμα αποθήκευση. 30 min κάθε «φάση». Pipelined προσέγγιση για 4 φορτία = 3.5h. Το κάθε «φορτίο» συνεχίζει να θέλει 2 h, όμως περισσότερα «φορτία» ολοκληρώνονται ανά ώρα. - PowerPoint PPT Presentation

Transcript of Pipeline: Ένα παράδειγμα από ….τη καθημερινή ζωή

  • Pipeline: . 30 min 4 = 8hPipelined 4 = 3.5h 2h,

  • MIPS : (IF-Instruction Fetch) , (ID+RegisterFile Read) ( : ID) ( ALU) (EX-execute) (MEM) RegisterFile (WB-write back)

  • Single-cycle vs pipelined performance:Single cycle: , : 2 ns ALU, MEM 1 ns register file

    Instruction classInstruct. fetchRegister readALU operationData accessRegister WriteTotal TimeLoad word (lw)2ns1ns2ns2ns1ns8nsStore word (sw)2ns1ns2ns2ns7nsR-Type (add,sub,and, or, slt)2ns1ns2ns2ns1ns6nsBranch(beq)2ns1ns2ns5ns

  • lw:lw $2, 200($0)lw $3, 300($0)lw $1, 100($0)3x8=24ns 2ns ! . : time_between_instructionspipelined= time_between_instructionsnon_pipelined/ number of pipe stages

  • single cycle , (: 8 ns) pipeline , (-pipeline stage) (2 ns), 1ns 14 ns pipeline, 24ns single cycle, 1,71 . 1000 : pipeline 1000x2ns + 14 ns = 2014 nsSingle cycle 1000x8ns + 24 ns = 8024 ns : 8024/2014=3,98 ~4 (8ns/2ns ratio )

  • (single cycle datapath): -: ? Write-back PC ( data hazard) ( control hazard)EX (ALU result)MEM (DM result)

  • (pipelined execution) (Functional Unit), .. IM, RegFile, ALU, DM ?

  • RegFile : ( hazards) ( ) ( ) functional unit pipeline register ( ) ( ): -M RegFile: Functional Units:

  • multicycle datapath, , .. ALU pipelined datapath, () () ; ;;; (pipeline stages)

  • Pipelined single cycle datapath ( -pipeline registers )

  • -Type:lw $rt, address_offset($rs)R-Type:(register type)Op: opcoders,rt: register source operandsRd: register destination operandShamt: shift amountFunct: op specific (function code)add $rd, $rs, $rtRead_Register_1Read_Register_2Write_Register

    oprsrtaddress_offset6 bits5 bits5 bits16 bits

    oprsrtrdshamtfunct6 bits5bits5bits5bits5bits6bits

  • To pipeline lw:O write register pipeline

  • datapath lw:

  • (Pipeline Hazards) (structural hazards) . (.. L1 $ I & D) (control hazards) , (.. Branches) (data hazards)

  • (Data Hazards) / (forwarding)sub $2, $1, $3# $2 suband $12, $2, $5# 1 ($2) subor $13, $6, $2# 2 ($2) subadd$14, $2, $2# 1&2 $2) -//- subsw $15, 100($2) # offset ($2) -//- sub

  • RAW (Read-After-Write) (true-dependence) WAR: (Write-After-Read) (anti-dependence) WAW: (Write-After-Write) (output-dependence) XY+KYX+SYZ+KWAWWARRAW

  • RAW - add $t0, $s0, $s1sub $t2, $t0, $s3or $s3, $t7, $s2mult $t2, $t7, $s0True dependence

  • WAR - Name dependence -antidependence add $t0, $s0, $s1sub $t2, $t0, $s3or $s3, $t7, $s2mult $t2, $t7, $s0

  • WAW -name dependence -output dependence add $t0, $s0, $s1sub $t2, $t0, $s3or $s3, $t7, $s2mult $t2, $t7, $s0

  • Identify all of the dependencies IF ID IF IDMEM1 2 3 4 5 6 7 8MEMWBWB IF ID IF IDWBMEMMEMWBadd $t0, $s0, $s1sub $t2, $t0, $s3or $s3, $t7, $s2mul $t2, $t7, $s0RAWWARWAW

  • Which dependencies cause hazards? (stalls) IF ID IF IDMEM1 2 3 4 5 6 7 8MEMWBWB IF ID IF IDWBMEMMEMWBadd $t0, $s0, $s1sub $t2, $t0, $s3or $s3, $t7, $s2mul $t2, $t7, $s0RAWWARWAW

  • Lets reorder the or IF ID IF IDMEM1 2 3 4 5 6 7 8MEMWBWB IF ID IF IDWBMEMMEMWBadd $t0, $s0, $s1sub $t2, $t0, $s3or $s3, $t7, $s2mul $t2, $t7, $s0RAWWARWAW

  • Lets reorder the or IF ID IF IDMEM1 2 3 4 5 6 7 8MEMWBWB IF ID IF IDWBMEMMEMWBadd $t0, $s0, $s1sub $t2, $t0, $s3or $s3, $t7, $s2mul $t2, $t7, $s0RAWWARWAWRAW

  • Lets reorder the mul IF ID IF IDMEM1 2 3 4 5 6 7 8MEMWBWB IF ID IF IDWBMEMMEMWBadd $t0, $s0, $s1sub $t2, $t0, $s3or $s3, $t7, $s2mul $t2, $t7, $s0RAWWARWAW

  • Lets reorder the mul IF ID IF IDMEM1 2 3 4 5 6 7 8MEMWBWB IF ID IF IDWBMEMMEMWBadd $t0, $s0, $s1sub $t2, $t0, $s3or $s3, $t7, $s2mul $t2, $t7, $s0RAWWARWAW

  • How to alleviate name dependencies? IF ID IF IDMEM1 2 3 4 5 6 7 8MEMWBWB IF ID IF IDWBMEMMEMWBadd $t0, $s0, $s1sub $t2, $t0, $s3or $s3, $t7, $s2mul $t2, $t7, $s0

  • Data Hazards: - () Register File .

    123456789sub $2,$1,$3IFIDEXMEMWBand $12,$2,$5IFIDEXMEMWBor $13,$6, $2IFIDEX MEMWBadd $14, $2,$2IFIDEXMEMWBsw $15, 100($2)IFIDEXMEMWB

  • (stall) (pipeline): NOP:sub $2, $1, $3nop nopand $12, $2, $5or $13, $6, $2add $14, $2, $2sw $15, 100($2)STALL ( )

    1234567891011sub $2,$1,$3IFIDEXMEMWBnopIFIDnopIFIDand $12,$2,$5IFIDEXMEMWBor $13,$6, $2IFIDEX MEMWBadd $14, $2,$2IFIDEXMEMWBsw $15, 100($2)IFIDEXMEMWB

  • (forwarding): RAW. register file. R-TYPE: RegFile, ALU, EX/MEM1. EX/MEM ALU 2. , MEM/WB , ALU EX : ALU ID/EX !!

  • 1a. EX/MEM.RegisterRd = ID/EX.RegisterRs1b. EX/MEM.RegisterRd = ID/EX.RegisterRt2a. MEM/WB.RegisterRd = ID/EX.RegisterRs2b. MEM/WB.RegisterRd = ID/EX.RegisterRtsub-and hazard: EX/MEM.RegisterRd = ID/EX.RegisterRs = $2sub-or hazard: MEM/WB.RegisterRd = ID/EX.RegisterRt = $2 () hazard:

  • Forwarding: Forwarding EX hazardForwarding MEM hazard NO hazard!!

  • EX hazard:if (EX/MEM.RegWrite and (EX/MEM.RegisterRd0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10

    if (EX/MEM.RegWrite and (EX/MEM.RegisterRd0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB=10 :

  • 2. MEM hazard:if (MEM/WB.RegWrite and (/W.RegisterRd0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01

    if (MEM/WB RegWrite and (MEM/WB.RegisterRd0)and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01

  • Pipelining forwardingForwarding paths:: a) / register :b) MEM/WB register ALU

  • Datapath to resolve hazards via forwarding:

  • K (data hazards) (stalls) write R-TYPE, EX ( ALU) , , EX/MEM . forwarding . ( write WB) forwarding !!

  • ( write) load store, MEM WB ( ) (stalls):

  • : (stalls) pipeline : ID and IF or.

  • :Hazard detection unit ID load .If (ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt)))Stall the pipeline stall: PC IF/ID -

  • Pipelined Control: