Jacky Huang-AE, Tek Taiwan

PCI Express 3 Receiver Testing Using the Tektronix BERTScope

Copyright © 2010, PCI-SIG, All Rights Reserved

2 2

PCIe 3.0 Timeline as of June 20122012

Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec

2010Jan Feb Mar

0.9 1.0

PCIe3 Base

0.7 0.9 1.0PCIe3 CEM

0.3 0.5 0.9 1.0

PCIe3 Test

0.7

6 mo FYI

�βTesting at workshops

�Test procedures posted

�IL Ready

27 mo

�CBB / CLB requirements understood

�CBB / CLB schematics and gerbers ready

�First CBB / CLB ready for testing

�Sigtest ready for testing�CBB / CLB available

for membership (early testing)

�Final CBB / CLB available for member purchase

�Final Sigtest posted

�PCIECV 2.1 release, PCIECV beta release for 3.0

�8G platform for PCIECV testing available

�Final PCIECV release and source posted

�PTC vendors submit proposals

�PTC HW and SW ready for beta testing

�Final PTC available for member purchase

�SW binary and source posted

�PTC vendor selection complete

Apr May Jun

2011

Slip

Completed

Milestone

Original

Milestone

Estimated

Milestone

Jul Aug

0.71

Scheduled

CWs

Planned

CWs

Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr

2013

Which PCIe3 Specification Applies? Plus Embedded PCIe 3.0

Copyright © 2012, Tektronix, Inc. - All Rights Reserved3

Base Specification vs. CEM Test Philosophies

� CEM Testing is primarily focused on Compliance

– Ensure Interoperability of Systems (Hosts) and Add-In Cards (Endpoints)

– Pass/Fail

– Margin Testing mainly to verify manufacturability

� Base Specification Testing is generally focused on Characterization

– Verify chip performance across a wide range of operating conditions– Voltage, Temperature, Eye Height, Eye Width, Equalization, etc.

– Margining is Key– Increase OEM’s latitude in choice of backplane material and PCB layout

PCI Express 3.0 Receiver Testing – Fall 2012 Copyright © 2012, Tektronix, Inc. - All Rights Reserved4

PCIe 3.0 Rx Solutions

Basic Receiver Testing

PCI Express 3.0 Receiver Testing – Fall 2012 Copyright © 2012, Tektronix, Inc. - All Rights Reserved6

At the simplest level, receiver testing is composed of:

1. Send impaired signal to the receiver under test

2. The receiver decides whether the incoming bits are a one or a zero

3. The chip loops back the bit stream to the transmitter

4. The transmitter sends out exactly the bits it received

5. An error counter compares the bits to the expected signal and looks for mistakes (errors)

Pattern Generator with Stress

1.2.

3.

4.

5.Error Counter

PCIe 3 CEM Test Fixtures

PCI Express 3.0 Receiver Testing – Fall 2012 Copyright © 2012, Tektronix, Inc. - All Rights Reserved7

Compliance Load Board

(CLB)

Compliance Base Board (CBB) Compliance Base Board Riser Card (CBB Riser)

Tx Lane 0 Out

CBB Riser Connector

PCIe Connector

100 MHz Refclk In

ATX Power In

Rx Lane 0 In

CBB Main Connector

x1/x16 Switch (Down for x1)

Tx Lane 0 Out (x1 Configuration)

(NOTE: Rx Connectors are on Rear Side of Board)

PCIe 3 CEM/Add-In Card Receiver Test

8 Gb/s Pattern Generator

RJ Source

SJ Source

DM Interference

CBB Riser CBB

Error Detector

DUT

RxTx

Combiner

Loopback

100 MHz Refclk

PCI Express 3.0 Receiver Testing – Fall 2012 Copyright © 2012, Tektronix, Inc. - All Rights Reserved8

PCIe 3 CEM/System Receiver Test

8 Gb/s Pattern Generator

RJ Source

SJ Source

DM Interference

CLB

Error Detector

DUT

RxTx

Combiner

Loopback

RefclkMultiplier

Refclk Out

Repeater(Optional)

PCI Express 3.0 Receiver Testing – Fall 2012 Copyright © 2012, Tektronix, Inc. - All Rights Reserved9

Tektronix Receiver Test Solution

� BERTScope– Stressed Pattern Generator

and Error Detector– Various models cover 2.5, 5,

8, and 16 GT/s

� DPP125– 3 or 4 tap pre-shoot and de-

emphasis in accordance with PCIe Gen 3 requirements

� BERTScope CR125A– Flexible and compliant clock

recovery

� DSA/DSO70000 Series Real-Time Oscilloscope

– Bandwidths to 33 GHz– TX testing– RX Stressed Eye Calibration

10 PCI Express 3.0 Receiver Testing – Fall 2012 Copyright © 2012, Tektronix, Inc. - All Rights Reserved

Equipment Setup for Amplitude, Emphasis, SJ and RJ Calibration

PCI Express 3.0 Receiver Testing – Fall 2012 Copyright © 2012, Tektronix, Inc. - All Rights Reserved11

12”

72”

SI Combiner

Data

Out

+

-

Data

In

+

-

CM In CM

Correction

DM In

Equipment Setup for CEM/Add-In Card Receiver Testing

PCI Express 3.0 Receiver Testing – Fall 2012 Copyright © 2012, Tektronix, Inc. - All Rights Reserved12

12”

72”

CBB Riser

Device Under Test (DUT)

RX LANE 0

TX LANE 0

REFCLK

IN CBB

SI Combiner

Data

Out

+

-

Data

In

+

-

CM In CM

Correction

DM In

Equipment Setup for CEM/System Receiver Testing

PCI Express 3.0 Receiver Testing – Fall 2012 Copyright © 2012, Tektronix, Inc. - All Rights Reserved13

12”

72”

CLB

Device Under Test (DUT)

RX LANE 0TX LANE 0

(Rear)

REFCLK OUT

IN

OUT

PCIe Repeater

SI Combiner

2.5 / 5.0 /

8.0 GHz

Out

100

MHz In

PCIe RefclkMultiplier

Data

Out

+

-

Data

In

+

-

CM In CM

Correction

DM In

NEW! -Components of the Receiver Test Solution

� BERTScope C Model

– PG, stressed eye sources, ED

� New! DPP125C Option ECM

– Eye opener, Clock doubler/Multiplier

� New! BSAITS125

– CM/DM interference

– ISI for Gen2 & Gen3

– Option EXP for variable ISI

� New! CR125A Opt PCIE8G

– PLL analysis for Gen1/2/3

� New! BSAPCI3 SW

– Auto calibration, Link training, and test

� Cables, adapters, compliance boards

� DSA/DPO/MSO70K Series Real-Time Oscilloscope

– Stressed Eye Calibration14

New! DPP125C with Option ECM

� Integrated reference clock multiplication to PCIe compliant 2.5 GHz, 5 GHz, and 8 GHz.

� Integrated eye opener functionality for testing DUTs with long channels.

� New microcontroller to provide more processing power.

� RS-232 interface enhancement to speed-up PCIe receiver equalization link training.

� SW to accommodate channel de-embedding and ISI fine adjustments.

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New! BSAITS125 Interference Test Set

� Programmable, variable ISI for automated testing and precision setting

� Built-in compliant PCIe2 and PCIe3 Medium and Long ISI channels

� Integrated PCIe3 CM and DM interference combiner

� Integrated PCIe3 Base Spec CM interference calibration

� Continuously Variable, Expanded ISI for automated testing of multiple standards with Option EXP

16

New! CR125A Opt PCIE8G

� PLL Loop BW Analysis for Gen1/2/3

� Uses CR125A and Test SW– Similar to Gen1/2 PLL Loop BW solution

17

New! BSAPCI3 PCIe 3.0 Automation SW

• Automated calibration, link training, loopback initiation, and testing.

• BER Map feature for TxEQ optimization.

• Reduces the time and minimizes the skill-set required to perform the calibration and testing.

• Increases the reliability and accuracy by removing inconsistencies with manual calibration.

18

Typical Test Configuration

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Beyond Compliance: BERTScope Analysis Tools

PCI Express 3.0 Receiver Testing – Fall 2012 Copyright © 2012, Tektronix, Inc. - All Rights

Reserved

20

� Besides being a BERT, the BERTScope’s “Scope” functionality brings benefits that complement those of the Tektronix scopes

� Analysis tools are full featured and easy to use

� Frees up the scope for other

tasks

� Eye diagram for quick diagnosis of synchronization and BER failure issues

� Debug challenging signal integrity problems

� Error Location Analysis

� Pattern Capture

� Jitter Map

� BER Contour

Comprehensive PCI Express Solution

Transmitter Receiver Protocol

Component Level Testing System Level Debug

HW/SW Integration

Characterization Compliance

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Thank You!