Nano-electronics of high κdielectrics on high mobility channel semiconductors for...

Nano-electronics of high κ dielectrics on high mobility channel semiconductors for key

technologies beyond Si CMOS

T. D. Lin, P. Chang, M. L. Huang, H. C. Chiu, C. A. Lin, W. H. Chang, Y. J. Lee, Y. C. Chang, and Y. H. Chang

J. Kwo and M. Hong

National Tsing Hua University, Hsinchu, Taiwan1

AOARD

Electron mobilities in GaAs, Si, and Ge

Solid curve: theory with combined polar and ionized-impurity scattering (Ehrenreich: JAP 32, 2155, 1961) Experimental points o: Reid and Willardson: J. Electronics and Control, 5, 54 (1958) ▲: Weisberg, Rosi, and Herkart: Metallurgical Soc. Conf., v.5 “Properties of elemental and compound semiconductors, Interscience Publishers, New York, p.275

GaAs Si and GeMeasured drift

mobility in Si and Ge(F. J. Morin and J. P. Maita, Phys. Rev.,

94, 1526, (1954) and 96, 28 (1954))

DRIFT MOBILITIES (cm2/ V-s) in Ge, Si, and GaAs at 300KGe Si GaAs

μn μp μn μp μn μpvalue at 300K 3900 1900 1400 470 8500 340

Temperature dependence

T -1.66 T -2.33 T -2.5 T -2.7 ― T -2.3

Background leading to unpin surface Fermi level in III-V compound semiconductors

Late 1980s to early 1990s, problems in then AT&T’s pump lasers (980 nm) for undersea optical fiber cable (trans-Atlantic)

Semiconductor facet (HR, AR) coating Reducing defects between InGaAs (GaAs) and coating

dielectrics Passivation of the facets Electronic passivation much more stringent than

optical passivation (110) vs (100) of InGaAs (GaAs)

Pioneering work of GaAs and InGaAs MOSFET’s using Ga2O3(Gd2O3) at Bell Labs w/o 2 overlayers 1994

novel oxide Ga2O3(Gd2O3) to effectively passivate GaAs surfaces 1995

establishment of accumulation and inversion in p- and n-channels in Ga2O3(Gd2O3)-GaAs MOS diodes with a low Dit of 2-3 x 1010 cm-2 eV-1(IEDM)

1996 first e-mode GaAs MOSFETs in p- and n-channels with inversion (IEDM) Thermodynamically stable

1997 e-mode inversion-channel n-InGaAs/InP MOSFET with gm= 190 mS/mm, Id = 350 mA/mm, and

mobility of 470 cm2/Vs (DRC, EDL) 1998

d-mode GaAs MOSFETs with negligible drain current drift and hysteresis (IEDM) e-mode GaAs MOSFETs with improved drain current (over 100 times) Dense, uniform microstructures; smooth, atomically sharp interface; low leakage currents

1999 GaAs power MOSFET Single-crystal, single-domain Gd2O3 epitaxially grown on GaAs

2000 demonstration of GaAs CMOS inverter

1897 J. J. Thomson discovery of electron

1947 The Transistor

2007 High k + metal gate on Si for 45 nm node CMOS

What next – III-V InGaAs, GaN, Ge MOS ?

Mervin Kelly, the then Director of Res. at Bell Labs, had predicted the problem and had already taken action to find a solution.

Although relays and vacuum tubes were apparently making all things possible in telephony, he had predicted for some years that the low speed of relays and the short life and high power consumption of tubes would eventually limit further progress in telephony and other electronic endeavors. In the summer of 1945, Kelly had established a research group at Bell Labs to focus on the understanding of semiconductors. The group also had a long-term goal of creating a solid-state device that might eventually replace the tube and the relay.

6

For Chip Makers, Hybrids May Be a Way Forward – NYTimes (Dec. 2009)By John MarkoffSearching for new ways to make computers that run faster and use less power, the chip industry is once again eyeing some exotic materials that can offer great speed, but have been more costly and difficult to manufacture than silicon.The materials, so-called III-V semiconductors, include compounds like gallium arsenide and indium phosphide. The have found their way into military and communications uses, but have largely been relegated to niches by more standard silicon-based manufacturing processes. The legendary supercomputer designer Seymour Cray used gallium arsenide in his Cray 3 and Cray 4 designs. In general, though, the materials have not had the low-power characteristics that have made conventional silicon chips so cost-effective.Sometime in the future, however, a new kind of hybrid chip might be made possible by manufacturing techniques that essentially glue together materials with incompatible molecular structures. This could result in chips that integrate radio or optical communications functions. It could also make it possible to run the III-V-based transistors at lower power without losing all of their speed advantages.Intel executives said the new class of transistors had no immediate product applications, but could help in the future in scaling transistors down to even more Lilliputian dimensions. The company is currently manufacturing chips at the 45-nanometer scale — a measure of minimum transistor feature size — and at this week’s meeting it will describe working chips at the next step down, 32 nanometers. Intel can now place about one billion transistors in its most advanced microprocessors, and the next step toward smaller scale, which will double the number of transistors available to circuit designers, will probably take place toward the end of 2009.It might be four chip generations, however, before Intel adds the new hybrid approach to its commercial chips, said Mike Mayberry, the company’s director of components research.The new technology could have widespread applications in consumer electronics products.During a news conference on Monday, industry executives expressed optimism about the new technique, which they said was still years away from commercialization.

exotic materials compounds like gallium arsenide and indium phosphidea new kind of hybrid chip, integrating radio or optical communications III-V-based transistors at lower power without losing all of their speed advantagesMOSFET, Not MESFET, HEMT four chip generations

http://bits.blogs.nytimes.com/author/john-markoff/�http://bits.blogs.nytimes.com/author/john-markoff/�

Motivation- Why InGaAs, Ge? Why MOSFET?Interfacial layer free?? Interfacial perfection → SiO2/Si

Outline

Experimental- Deposition of Ga2O3(Gd2O3) [GGO]- Characterization of GGO/Ge interface usingstructual (RHEED, HR-TEM),

- Electrical analyses for MOS devices, including Quasi-static C-V and Charge pumping measurement

Inversion-channel InGaAs, Ge MOSFET’s and comparison

Oxide scalability and thermodynamical stabilityConclusion

7

K. Saraswat, et al., Mat. Sci. and Eng. B 135, 242 (2006). (Stanford U.)

Ge

Si SiO2

HfO2

B. De Jaeger, et al., Microelectron. Eng. 80, 26 (2005). (IMEC)

SiGeON

GeO2

Ge

GeO2

K. Kita, et al., App. Surf. Sci. 254 (2008). (U. of Tokyo)

GGO

Si

GGO

GaAs

Direct deposition of high κ GGO on Si & GaAs

M. Hong, et al., Appl. Phys. Lett. 76, 312 (2000).

T. D. Lin, et al., J. Cryst. Growth, 301, 386 (2007).

Experimental- Novel deposition of MBE-Ga2O3(Gd2O3) [GGO] and ALD oxides- Characterization of oxide/InGaAs,Ge interface usingstructural (RHEED, HR-TEM), and chemical (in-situ AR-XPS) analyses

Amorphous GGO

Cleaned Ge surface

High-κ

Do we need a new methodology for GaAs passivation?A. M. Green and W. E. SpicerStanford UniversityJVST A11(4), 1061, 1993

“A new methodology for passivating compound semiconductors is presented in which two overlayers are used. In this approach, the first layer defines the surface electronically and the second provides long term protection.”

Sulfur passivation –Sandroff et al, Bell Labs APL51, 33, 1987Sb passivation – Cao et al, Stanford Surf. Sci. 206, 413, 1988

Is it possible to have a III-V (GaAs) MOS, similar to SiO2/Si, in which a low Dit, a low J, thermodynamic stability at high temp. (>800°C), single layer of gate dielectric, no S and Sb, etc are achievable?

YES!!!Is it necessary to have GeON as an interfacial layer in Ge MOS? No!!!

oxideMBE

in-situXPS

oxide & metal

MBE

III-VMBE

Si-GeMBE

annealing& metalchamberWafer in

Multi-chamber MBE/in-situ analysis system

In-situSPM SMOKE

metalchamber

ALD

ALD

Pioneer Work : Single Crystal Gd2O3 Films on GaAs

GaAsa=5.65Å

[001]

(110)

[110]a= 10.81Å

1: 2 match

(100)

[110]

[110]

3: 4 match

O

Gd

Ga

View along GaAs [110]

Gd2O3

Mn2O3 Structure

Gd2O3 (110) 25Å

M. Hong, J. Kwo et al, Science 283, p.1897, 1999

-10 -8 -6 -4 -2 0 2 4 6 8 1010-12

1x10-10

1x10-8

1x10-6

1x10-4

1x10-2

1x100

1x102-10 -8 -6 -4 -2 0 2 4 6 8 10

t=260A t=185A t=140A t=104A t=45A t=25A Gd2O3 on Si, 40A

J L (A

/cm

2 )

E [MV/cm)

EOT0.8 nm

SiO21.5 nm

Low Dit’sand low JL

Single domain, epitaxial film in (110) Mn2O3 structure

ULTRAHIGH VACUUM DEPOSITION OF OXIDES

Gd/(Ga+Gd) > 20%Gd+3 stabilize Ga+3

GaAs

a-(Ga,Gd)2O3x-tal Gd2O3

Mixed Oxide (Ga,Gd)2O3

Epitaxy

Pure Gd2O3 Film

x-tal Gd2O3

GaAs

Initial thinking: to attain Ga2O3 film for passivationHigh-purity single crystal Ga5Gd3O12 (GGG) source

Evaporation (sublime) by e-beam

Gd2O3 ionic oxideTm > 4000K

Ga2O3 more covalent oxideTm ~ 2000K

Ga2O3 evaporated mostly, and formed amorphous Ga2O3 film

High Resolution TEM of (Ga,Gd)2O3 on GaAs

Epitaxy

Initial growth of Ga2O3(Gd2O3) 1.1 nm thick

X-ray diffraction of normal scan and rocking curve

In-situ RHEED pattern showing a single crystal growth

MBE – compound semiconductor growth – A. Y. Cho (National Medal of Science 1993 and National Medal of Technology 2007)

MBE – metal and oxide growth – J. Kwo (first in discovering anti-ferromagnetic coupling through non-magnetic layer in magnetic superlattices PRL’s 1985 – 1986)

Frank Shu, UC University Professor and former President of Tsing Hua Univ.

Growth of Ga2O3(Gd2O3) films using e-beam evaporation from Ga5Gd3O12 target – RBS studies

Identified the essential role of Gd2O3The Gd/(Ga+Gd) ratio needs to be greater than 20%The electropositive Gd+3 may stabilize Ga+3 in the film

1960 Kahng and Atalla, Bell Labs First MOSFET

Device Scaling – Beyond 22-16 nm node:high κ, metal gates, and high mobility channel

Moore’s Law:The number of transistors per square inch doubles every 18 months

Shorter gate length LThinner gate dielectrics tox

Driving force :High speedLower power consumptionHigh package density

Oxide/semiconductor interface

Metal gate

High mobilitychannel

High κ gatedielectric

Integration of IIIV, Ge, GaN with Si

Si GaAs In0.53Ga0.47As

GaN InAs InSb units

Energy gap 1.12 1.43 0.75 3.40 0.354 0.17 eV

Lattice constant 5.431 5.65 5.87 3.19 6.06 6.50 Å

Electron effective

mass0.19 0.063 0.041 0.20 0.023 0.014 -

Electron mobility 1500 8500 14000 1300 25000 78000

cm2 V-1 s-1

Electron saturation velocity

1 × 107 2 × 107 8 × 106 3 × 107 3 × 107 5 × 107 cm s-1

Electron mean free

path0.07 0.15 0.19 0.2 0.27 0.58 μm

III-V (Ge)MOSCritical Issuesand proposed

solutions

Charge trapping and phononsElectrical characterizations:IETS and charge pumping

Scalability of high κon III-V

In-situ cap of GGG with other oxides

or metal gates

Device fabrication-Material issues

In-situ metal gateEtching of metals

and oxides

Growth of oxide/ III-V MOS – MBE , ALD

In-situ ALD + MBE

Theoretical modeling and simulation

Devices with fT over 500GHz at 0.1 um

gate length

Device fabrication-Process integrationE-beam writing

New mask levels

Proposed Solutions to Challenges of III-V (Ge) MOSFET

Thermodynamic Stability High Temp. Oxide

+Tailored heat treatment

Interfacial density of states- Chemical bonding

--structuresIn-situ XPS, AFM, STM

-Interfacial phonon

18

Enhancement-mode devices

HEMT-like structures

Same as conventional Si MOSFET

Buried Channel Transistor - HEMT

D. –H. Kim et al., IEEE EDL, p. 830, (2008)D. –H. Kim et al., IEDM, p. 719, (2008)

Lg = 30 nm Gm = 1.8-1.9 mS/µm

Surface channel InGaAs MOSFET with non-self-aligned Process

Y. Xuan et al., IEDM, p. 371, (2008)

Self-aligned inversion-channel InGaAs MOSFET

1. TiN sputtering2. PMMA coating, E-beam writing, and hard mask deposition3. Dry-etching4. S/D patterning, implantation & activation5. S/D contact region patterning, wet-etching of oxide, contact

metal deposition, lift-off & ohmic alloying

In0.53Ga0.47As Buffer

MBE-Al2O3/GGOor ALD-Al2O3

Si implanted region Si implanted region

Source Drain

p- In0.53Ga0.47As

InP substrate

TiN-GatePMMA (~300nm)Pt

Output & Sub-threshold Characteristics

1. tTiN= 160nm, tAl2O3=2nm, tGGO=5nm, W/L=10/1μm

2. Id,max=1.05 mA/µm @Vg=2V, Vd=2V

3. gm,max=714 µS/µm @Vg=0.7V, Vd=2V

4. Vth~0.2V, µFE=1300 cm2/V∙s (from transconductance analysis)

Si NMOSFET90nm nodeLg~45nmId,sat~1 mA/µm

Self-aligned inversion-channel TiN/Al2O3/GGO/In0.53Ga0.47As/InP MOSFET

Performance Trend

Lg 20µm 10µm 8µm 4µm 2µm 1µm

Id,sat(µA/µm) 60 104 140 263 506 1050

gm,max(µS/µm) 34 56 81 152 320 714

Estimated PerformanceFor Lg=0.5µm

0.5µm

~2mA/µm

~1.4mS/µm

Performance for Si 32 nm nodeId,sat = 1.5-1.6 mA/µm

0.35 µm

~3mA/µm

~2.1mS/µm

ALD-Al2O3 on In0.53Ga0.47As MOSFETs

0.0 0.5 1.0 1.5 2.00.00

0.05

0.10

0.15

0.20

0.25

0.30 Vg = 0~4Vstep = +0.5V

I d (m

A/µm

)

Vd (V)

4V

0V-2 -1 0 1 2 3 40.00

0.05

0.10

0.15

0.20

0.25

0.30

0

30

60

90

120

I d (m

A/µm

)

Vg (V)

g m (µ

S/µm

)

Vd = 2V

Short air-exposure between ALD-Al2O3 and InGaAs Self-aligned process Id,max= 288 mA/µm @Vg= 4V, Vd= 2V gm= 93 µS/µm @Vg=1.6V, Vd=2V

Gate length= 1µm

H. C. Chiu et al, submitted to EDL

ALD-Al2O3 on In0.53Ga0.47As MOSFETs

Low leakage current density for TiN/ALD-Al2O3/InGaAswithstanding dopant activation temp up to 750oC for 15 sec

Gate-to-source leakage current

Sub-micron Gate Length ALD- Al2O3/In0.53Ga0.47As/InP MOSFET

1 2 3 40

200

400

600

800

0.0V

0.5V

1.0V

1.5V

2.0VVg=2.5V

I d (µ

A/µm

)

Vd (V)-1 0 1 2 3

10-2

100

102

I d (µ

A/µm

)

Vg (V)

Vd=4.0V

Vd=0.1V

0

100

200

300

400

Gm

(µS/

µm)

W/L= 100/0.6μm, tox= 6nm, CET ~3nm

Id,max= 678 μA/μm @Vg= 2.5V, Vd= 4V

gm,max= 354 μS/μm @Vg= 0.8V, Vd= 4V

Vth= 0.35V, Ion/Ioff= 1.7×103

Sub-micron Gate Length ALD- Al2O3/In0.53Ga0.47As/InP MOSFET

2009 VLSI-TSA Symposium

1 10-0.4-0.2

0.0

0.2

0.4

0.6

0.8

Vth

V th

(V)

Lg (µm)100

200

300

400

S.S.

(mV/

dec)

S.S.

0.1 1 10101

102

103

I d (µ

A/µm

)

Lg (µm)

101

102

103

Gm

(µS/

µm)

channel doping(cm-3)

Tox (CET)[nm]

SIC*(cm-3)

Ta **(oC)

Rs*** (Ω/□)

ρc**** (Ω．cm2)

Id, max (µA/µm)@Lg=1µm

Gm (µS/µm)@Lg=1µm

Ion/Ioff@Vds=2V

S.S.(mV/dec)

DIBL(mV/V)

5×1016 10(5) 5×1018 650 717 1.28×10-5 164 60

E-mode III-V MOSFETsBenchmark

MBE-Al2O3/GGO/In0.53Ga0.47AsLg=1µmId= 1.05 mA/μmgm= 714 μS/μmT. D. Lin et al., APL 93, 033516 (2008)

ALD-Al2O3/In0.53Ga0.47AsLg=0.6µmId= 678 μA/μmgm= 354 μS/μm

0.0 0.5 1.0 1.5 2.00

400

800

1200 InxGa1-xAs

ALD-Al2O3

x=0x=0

MBE-Al2O3/GGO

x=0.3x=0.53

x=0.53

x=0.7

x=0.7

x=0.65

x=0.53

x=0.75x=0.53

x=0

I d,m

ax(µ

A/µm

)

0.0 0.5 1.0 1.5 2.00

200

400

600

800

x=0 x=0x=0x=0.7

x=0.7x=0.3

x=0.53

x=0.53x=0.53

x=0.53

InxGa1-xAs

ALD-Al2O3x=0.75

x=0.65

MBE-Al2O3/GGO

Lg (µm)

g m(µ

S/µm

)

Self-aligned

Non-self-aligned

HEMT-like

MBE Lg 0.35 µm → gm 2mS/µm

ALD Lg 0.1 µm → gm 2mS/µm

29

Key – high κ’s/InGaAs interface

Toward Fermi-level Unpinning and have achieved it

GGO scalability and high-temperature thermodynamic stability of GGO/InGaAs

Energy parameters

MOSCAPs with different work function metals

30




Energy parameters


31

1.0

0.8

0.6

0.4

0.2Cap

acita

nce

(µF/

cm2 )

-3 -2 -1 0 1 2 3Gate voltage (V)

1.0

0.8

0.6

0.4

0.2

Cap

acita

nce

(µF/

cm2 )

-3 -2 -1 0 1 2 3Gate voltage (V)

1.0

0.8

0.6

0.4

Cap

acita

nce

(µF/

cm2 )

-3 -2 -1 0 1 2 3Gate voltage (V)

-4 -2 0 2 40.0

0.2

0.4

0.6

0.8

1.0

1.2

Frequency 1k 10k 50k 100k 500k

Bias (V)

Capa

cita

nce

(µF/

cm2 )

P-type N-type25oC 150oC 150oC 25oC

In-situ MBE-Al2O3/GGO/ n- and p-In0.2Ga0.8As

Fermi-level movement efficiency (FLE), an "aid" to show effectiveness of passivation; FLE ~100% for perfected SiO2/SiFLE ~ 30% near mid-gap at 150oC, and much higher away from mid-gap at 25oC in the p- and n-samples

32

1.4

1.2

1.0

0.8

0.6

0.4Cap

acita

nce

(µF/

cm2 )

-3 -2 -1 0 1 2 3Gate voltage (V)

0.70.60.50.40.30.2C

apac

itanc

e (µ

F/cm

2 )

3210-1-2Gate voltage (V)

Comparison between Al2O3/GGO and ALD-Al2O3n-In0.2Ga0.8As at room temperature

Fermi-level trace

GGO/InGaAs showed much better CV/GV (compared with that of ALD)

NTHU sample-Al2O3(3nm)/GGO(8.5nm) on In0.2Ga0.8As

IMEC sample –ALD Al2O3(10nm) on In0.15Ga0.85As

Fermi-level trace

Fermi-Level Movement Efficiency (FLME) with Quasi-Static CV

( ) ( ) 1G

FB

V

s G s FBoxV

CV VC

− = −

∫ψ ψ

C. N. Berglund et al., IEEE Trans. Electron Dev. Vol. 13, 701 (1966)

Berglund’sintegral

theoretical CV (Dit=0) measured CV

Capa

citan

ce

Gate Bias (V)

EC

EV

E i

theroretical (Dit=0) measured

ψ s (e

V)Gate Bias (V)

Berglund’s integral

-4 -2 0 2 40.2

0.4

0.6

0.8

1.0

1.2

QSCV 1 kHz 10 kHz 50 kHz 100 kHz 500 kHz

C (µ

F/cm

2 )

Gate Bias (V)

-4 -2 0 2 4

0.2

0.4

0.6

0.8

1.0

1.2

QSCV 1 kHz 10 kHz 50 kHz 100 kHz 500 kHz

C (µ

F/cm

2 )

Gate Bias (V)

-3 -2 -1 0 1 2 30.4

0.6

0.8

1.0

1.2

Sweap Rate 50mV/1s 50mV/5s 50mV/25s 50mV/50s

C (µ

F/cm

2 )

Gate Bias (V)

-3 -2 -1 0 1 2 3

0.4

0.6

0.8

1.0

1.2

Sweep Rate 50mV/1s 50mV/5s 50mV/25s 50mV/50s

C (µ

F/cm

2 )

Gate Bias (V)

-3 -2 -1 0 1 2 3-0.20.00.20.40.60.81.01.2

E i

ψs (

eV)

EC

Gate Bias (V)

EV Measured Dit=0

-3 -2 -1 0 1 2 3-0.20.00.20.40.60.81.01.2

EC

EV

E i

Measured Dit=0

ψs (

eV)

Gate Bias (V)

Al/Al2O3(3nm)/GGO(5nm)/p-In0.2Ga0.8As/GaAs

Fermi-Level Movement Efficiency (FLME)

Al/Al2O3(3nm)/GGO(7nm)/n-In0.2Ga0.8As/GaAs

FLME~77%

FLME~80%

CV curve at 100 Hz should not rise up.

36

GGO Unpins the In0.2Ga0.8As Fermi level

-5 -4 -3 -2 -1 0 1 2 3 4 50.20.40.60.81.01.21.4

0.20.40.60.81.01.21.4

dark

Bias (V)

1kHz 10kHz 50kHz 100kHz 500kHzC

apac

itanc

e(µF

/cm

2 )

Al2O3/GGO/p-In0.2Ga0.8As/p-GaAs High k :

GGO: 14-15Al2O3: 8

Low leakage unpinned Fermi-level The role played by In ?

illuminated

-5 -4 -3 -2 -1 0 1 2 3 40.20.40.60.81.01.21.4

0.20.40.60.81.01.21.4

Bias (V)

light on

100Hz 500Hz 1kHz 10kHz 50kHz 100kHz 500kHzC

apac

itanc

e(pF

/cm

2 )

-6 -4 -2 0 2 4 610-10

10-8

10-6

10-4

10-10

10-8

10-6

10-4

J (A

/cm

2 )

E (MV/cm)

37

-2 -1 0 1

1

2

3

4

Bias (V)

C/A

(µ F

/cm

2 )

50k 100k 500k

4.5nmk ~17@100 kHz, CET=1nm

ALD-HfO2 on In0.53Ga0.47Aswith short air exposure ~10 min

-2 -1 0 101234

∆VFB~0 V

C/A

(µF/

cm2 )

Bias (V)

Theoretical curve 1 MHz

TiAu

InPn-In0.53Ga0.47As

n-In0.53Ga0.47As (buffer)ALD HfO2 (4.5 nm)

ƒinv ∝1/ τR ∝ ni

Unpinning Fermi-level

Achieving a low Dit in ALD-Al2O3 on In0.53Ga0.47As with short air exposure

38

10 nm

H. C. Chiu et al., Appl. Phys. Lett., 93, p202903 (2008)

very sharp Al2O3/InGaAs interface Fermi-level moves across the nearly

entire bandgap high FLME of 63% near midgap

-3 -2 -1 0 1 2 30.0

0.2

0.4

0.6

0.8

1 kHz

10 kHz

100 kHz

Quasi-static

C (µ

F/cm

2 )

Gate Bias (V)

1000 kHz

-3 -2 -1 0 1 2 3-0.4-0.20.00.20.40.60.8

EC

EV

E i

Measured Dit=0

ψ s (e

V)

Gate Bias (V)

0 10k 20k

3x10-7

4x10-7

5x10-7

6x10-7

+0.1 V 0.0 V -0.1 V

G p/ω

(S·s/

cm2 )

Frequency (Hz)

Dit Overestimation in Small Band-gap Semiconductors Using Conductance Method

K. Martens et al., IEEE Trans. Electron Devices, Vol. 55, 547 (2008)

Dit=3×1012 cm-2eV-1 extracted at 300kOverestimating Dit due to weak

inversion at depletion region

GeOxNy on Ge

Dit=8.5×1012 cm-2eV-1 extracted at 300k Dit=7.0×1011 cm-2eV-1 extracted at 80k

ALD-Al2O3 on In0.53Ga0.47As

Charge Pumping

-1.0 -0.5 0.0 0.5 1.00.0

0.4

0.8

1.2

1.6 =2.5 × 1011 cm-2eV-1itD

itD

Vfb

I cp (µ

A)

Bias (V)

1M 900k 800k 700k 600k 500k 400k 300k 200k 100k

Area =7.85x10-5cm-250% duty cycleTr,Tf = 100nsAmp. =1V

VthAmp.

4 5 6 7 8 91017

1018101910201021

N bt (

#/cm

3 )

Tunneling distance (A)

ALD-Al2O3

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.31011

1012

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3

1011

1012

itD

itD

Upper Half

Lower Half

D it (

eV-1cm

-2)

E-Ei (eV)

ALD-Al2O3 on In0.53Ga0.47As

A low mean Dit ~ 2.5×1011 cm-2eV-1 near midgap (±0.2eV) A Dit of ~ (2-4)×1011 cm-2eV-1 in the

lower half of the bandgap and 1012 cm-2 eV-1 in the upper half of the bandgap A low bulk trap density ~ 7×1018 cm-3

41




Energy parameters


42

Summary of samplesN-type TH622

MBE Al2O3/GGO(10nm)/In0.2Ga0.8As TH647

MBE Al2O3/GGO(8.5nm)/In0.2Ga0.8As TH663

MBE Al2O3/GGO(4.5nm)/In0.2Ga0.8AsP-type TH834



MBE Al2O3/GGO(3.0nm)/In0.2Ga0.8As

(n)p-GaAs (buffer)

GGO

(n)p-In0.2Ga0.8As

~3nm

2” n-GaAs

Al2O3

~225nm

~7.5nm

-4 -2 0 2 41020304050607080

1k 10k 50k 100k 500k

Au/Al2O3(3nm)/GGO(10nm)/In0.2Ga0.8As/GaAs/B.E.

k~15-16

Bias (V)

Capa

cita

nce(

pF)

-4 -2 0 2 415

30

45

60

75

90

1k 10k 50k 100k 500k

Au/Al2O3(3nm)/GGO(8.5nm)/In0.2Ga0.8As/GaAs/B.E.

Bias (V)

Capa

cita

nce(

pF)

K~14-15

-3 -2 -1 0 1 2 30

20

40

60

80

100

120

1k 10k 50k 100k 500k

k~14-16

Bias (V)

Au/Al2O3(3nm)/GGO(4.5nm)/In0.2Ga0.8As/GaAs/B.E.

Capa

cita

nce(

pF)

-5 -4 -3 -2 -1 0 1 2 3 4 50102030405060708090

100Pt/Al2O3(3nm)/GGO(8.5nm)/In0.2Ga0.8As/GaAs/B.E.

1k 10k 50k 100k 500k

Capa

cita

nce

(pF)

Voltage (V)

k~14-16

-5 -4 -3 -2 -1 0 1 2 30102030405060708090

100Ni/Al2O3(3nm)/GGO(5nm)/In0.2Ga0.8As/GaAs/B.E.

1k 10k 50k 100k 500kCa

paci

tanc

e (p

F)

Voltage (V)

K~15-17

-3 -2 -1 0 1 2 30102030405060708090

100110120130140

Ni/Al2O3(2.5nm)/GGO(3nm)/In0.2Ga0.8As/GaAs/B.E.

500 1k 10k 50k 100k 500k

Capa

cita

nce

(pF)

Voltage (V)

k~15-17

C-V Characteristics

-6 -4 -2 0 2 4 6

10-910-710-510-310-1101

GGO-45A GGO-85A GGO-100A

E (MV/cm) J

(A/c

m2 )

Low leakage current density @Vg=Vfb+1V10-8-10-9 A/cm2 [GGO≧8.5nm]3.1×10-5 A/cm2 [GGO 4.5nm]

-6 -4 -2 0 2 4 610-910-810-710-610-510-410-3

GGO-85A GGO-50A GGO-30A

J (A

/cm

2 )

V (V)

Low leakage current density @Vg=Vfb-1V~10-8-10-9 A/cm2 for various GGO thicknesses

J-E Characteristics

45

Au gate metal (N2 8000C 10 s + FG 3750C 30 min with B.E(AuGe-Ni-Au))GGO

thicknessGGO κvalue Vfb

Dispersion(10k-500k)

J@Vfb+1V(A/cm2) Dit(cm

-2eV-1) GGO CET

10 nm 14-15 1.1V 2.2% 1.46×10-9 1.4×1011 2.7 nm8.5 nm 14-16 1.1V 4.7% 1.78×10-9 2.6×1011 2.2nm4.5 nm 14-16 1.1V 5.4% 3.1×10-5 1.3×1011 1.2 nm

Electrical properties of Au(Ni)/Al2O3/GGO/In0.2Ga0.8As/GaAs

Ni gate metal (He 8500C 10 s + 3000C 30min in with B.E(TiN))GGO

thicknessGGO κvalue Vfb

Dispersion(10k-500k)

J@Vfb+1V(A/cm2) Dit(cm

-2eV-1) GGO CET

8.5 nm 14-16 -0.9V 5.71% 8.55×10-9 1.1×1011 2.21 nm5nm 15-17 -0.9V 4.22% 2.9×10-9 1.5×1011 1.2nm3 nm 15-17 -0.9V 6.62% 4.72×10-9 1.2×1011 0.73 nm

46

GGO scalability

tGGO(nm) 10 8.5 4.5

CETGGO(nm) 2.7 2.2 1.2

3 4 5 6 7 8 9 100.60.91.21.51.82.12.42.7

CET G

GO (n

m)

tGGO (nm)

n-type p-type

tGGO(nm) 8.5 5 3

CETGGO(nm) 2.21 1.2 0.73

n-type p-type

47




Energy parameters


153 150 147 144 141 138 135

hν = 680 eV

(III)

(V)

(VI)

153 150 147 144 141 138 135

250 eV

460 eV

680 eV

(VI)

153 150 147 144 141 138 135

hν = 680 eV

GaAs

GaAs

As2O3

(II)

(I)

114 111 108 105 102 99

GaAsGa2O3

(VI)

(V)(III)

hν = 680 eV

114 111 108 105 102 99

Ga2O3

GaAs

(II)

(I)

hν = 680 eV

448 446 444 442

InGaAs

In(OH)3

In2O3

(VI)

(V)

(III)

hν = 680 eV

448 446 444 442

hν = 680 eV

InGaAs

InGaAs

In2O3

(II)

(I)

Depth profile of ALD-HfO2/In0.15Ga0.85As: SR-XPS

(III)

(V)

(VI)

Native oxide/In0.15Ga0.85As

8nm-HfO2/In0.15Ga0.85As

In 3d5/2 Ga 3p As 3p

In 3d5/2 Ga 3p As 3p As 3p

(IV)

arsenic oxide was removed

Interfacial layer:Ga2O3; In2O3; In(OH)3

Ga2O3, As2O3, In2O3

In0.15Ga0.85As

Ga2O3, In2O3

ALD-Al2O3

In0.15Ga0.85As

Fraction of a mono-layer As2O5

ALD-HfO2

In0.15Ga0.85As

Fermi level unpinning at ALD-oxide/InGaAs

Fermi Level unpinning

Native oxide

Different chemical reaction for TEMAH/H2O and TMA/H2O on air-exposed InGaAs surface

M.L.Huang, et al, APL Dec 2005; citations:53

50

Valence band offsets: determined by XPS

InGaAsVBM

InGaAsCL EE −

oxideVBM

oxideCL EE −InGaAs

CLoxideCL EE −

VE∆

InxGa1-xAs

oxide

)()()( oxideVBMoxideCL

InGaAsCL

oxideCL

InGaAsVBM

InGaAsCLv EEEEEEE −−−+−=∆

:InGaAsCLE core level of InGaAs

valence level max of InGaAs

:oxideVBME

:InGaAsVBME

:vE∆

:oxideCLEvalence level maximum of oxide

core level of oxide

Valence band offset

E. A. Kraut et al., PRL 44, 1620 (1980); A. Franciosi et al., Surf. Sci. Rep. 25, 1 (1996)M. L. Huang et al., APL 89, 012903 (2006)

VBM

CBM

VBM

CBM

CL

CL

30 25 20 15 10 5 0 -5

17.1 eV

16.1 eV

23.1 eV

~5.65 eVALD amorphous HfO2

ALD amorphous Al2O3MBE single crystalγ-Al2O3 on Si(111)

~7.5 eV

~6.8 eV

Norm

alize

d In

tens

ity (e

V)

Energy Loss (eV)

O 1s EELS

~5.45 eV

MBE amorphous (Ga2O3)(Gd2O3)

hωp~25.0 eV

Band-to-band transitionPlasmon Loss

The minimum energy of band-to-band transition => Bandgap (Eg)

Bandgap of oxide : determined by photoemission-EELS

(Electron Energy Loss Spectroscopy)

F. G. Bell & L. Ley, PRB 37, 8383 (1988); S. Miiyazaki, Appl. Surf. Sci. 190, 66 (2002)

deviation: ±0.1 eV

52

HfO2/GaAs 40.36 eV -23.58 eV 14.19 eV 2.62 eV

HfO2/In0.15Ga0.85As 40.42 eV -23.56 eV 14.19 eV 2.67 eV

HfO2/In0.53Ga0.47As 40.57 eV -23.52 eV 14.19 eV 2.86 eV

Energy-Band Parameters at HfO2/InGaAs

InGaAsVBM

InGaAsdAs EE −2/53

oxideVBM

oxidefHf EE −2/74

InGaAsdAs

oxidefHf EE 2/52/7 34 − VE∆

0.72

1.8

2.86

1.48

2.67

1.19

x=0.53

Eg(HfO2)~5.34 eV

x=0.15HfO2/InxGa1-xAs

ΔEc

ΔEv

Eg(HfO2)~5.38 eV

ΔEc

ΔEv

InxGa1-xAs

HfO2

ΔEc

ΔEv

Eg

[1] M. L. Huang et al., APL 89, (2006)

)()()( oxideVBMoxideCL

InGaAsCL

oxideCL

InGaAsVBM

InGaAsCLv EEEEEEE −−−+−=∆

53

-4 -2 0 2 410-10

10-810-610-410-2

J (A

/cm

2 )

EG (MV/cm)-6 -4 -2 0 2 4 610

-10

10-810-610-410-2

J (A

/cm

2 )

EG (MV/cm)

J at Vfb+1V =2x10-8 A/cm2

J at Vfb+1V =1x10-8 A/cm2

Conduction band offsets: F-N tunneling

8.3nm-HfO2 / In0.15Ga0.85As 7.8nm-HfO2 / In0.53Ga0.47As

0 2 4 6 8

-48

-44

-40

ln(J

/Eox

2 )

1/Eox (nm/V)

ΔEc=1.48 eV

(-) (+)

(φ-_ φ+) = (Фm-χs) --- (1) S+ = -8π(2m*)1/2(φ+)3/2/3qh --- (2)S- = -8π(2m*)1/2(φ-)3/2/3qh --- (3)

ln(JFN/Eox2) = S/Eox+ ln(C)S = -8π(2m*)1/2(φ)3/2/3qhC = q3/8πhφm*

Фm: metal work functionχs : electron affinity of InGaAs

2 4 6 8-48

-44

-40

ln(J/E

ox2 )

1/Eox (nm/V)

ΔEc=1.8 eV

(-) (+)

deviation : ±0.08 eV[1] T.S. Lay et al, Solid State Electron. 45, (2001)[2] Y. C. Chang, et. al. Appl. Phys. Lett, 92, 072901 (2008).

Discussion: Energy band parameters

Eg(Al2O3)~6.8 eV

ALD-Al2O3/In0.15Ga0.85As

1.19 eV

3.78 eV

cE∆

vE∆

1.83±0.1eV

XPS method FN tunneling

1.6 ± 0.1 eV

deviation : ±0.1 eV

0.75

1.84

2.86

1.591.41

2.672.62

1.191.42

x=0 x=0.25 x=0.5

Eg(HfO2)~5.45 eV

ALD-HfO2/InxGa1-xAs

1.66

2.74

1.05

x=0.15

cE∆

vE∆

0.75

1.89

3.86

2.09

3.96

1.71

3.67

1.051.42Eg(Al2O3)~6.8 eV

x=0 x=0.25 x=0.5ALD-Al2O3/InxGa1-xAs

1.19

3.78

x=0.15

cE∆

vE∆

1.83

0.75 eV

1.84 ±0.1 eV

2.86 eV

x=0.5

Eg(HfO2)~5.45 eV

ALD-HfO2/In0.5Ga0.5As

cE∆

vE∆

1.8 ± 0.1 eV

XPS method FN tunneling

Conclusion

Perfecting the best atomic-scale hetero-structures and their interfaces in high κ and high mobility semiconductors

Probing them with the most powerful analytical tools (XPS and x-ray diffraction using synchrotron radiation, in-situ XPS, and HR-TEM)

Producing novel, high-performance electronic devices ready for beyond Si CMOS

55

�� Nano-electronics of high k dielectrics on high mobility channel semiconductors for key technologies beyond Si CMOS � � T. D. Lin, P. Chang, M. L. Huang, H. C. Chiu, C. A. Lin, W. H. Chang, Y. J. Lee, Y. C. Chang, and Y. H. Chang �J. Kwo and M. Hong��National Tsing Hua University, Hsinchu, Taiwan��Electron mobilities in GaAs, Si, and GeBackground leading to unpin surface Fermi level in III-V compound semiconductorsPioneering work of GaAs and InGaAs MOSFET’s using Ga2O3(Gd2O3) �at Bell Labs w/o 2 overlayers投影片編號 5投影片編號 6投影片編號 7投影片編號 8投影片編號 9Pioneer Work : Single Crystal Gd2O3 Films on GaAs投影片編號 11投影片編號 12投影片編號 13投影片編號 14投影片編號 15投影片編號 16投影片編號 17投影片編號 18Buried Channel Transistor - HEMTSurface channel InGaAs MOSFET with non-self-aligned ProcessSelf-aligned inversion-channel InGaAs MOSFET Output & Sub-threshold CharacteristicsPerformance Trend投影片編號 24投影片編號 25Sub-micron Gate Length �ALD- Al2O3/In0.53Ga0.47As/InP MOSFETSub-micron Gate Length �ALD- Al2O3/In0.53Ga0.47As/InP MOSFET投影片編號 28Key – high k’s/InGaAs interface Key – high k’s/InGaAs interface 投影片編號 31投影片編號 32Fermi-Level Movement Efficiency (FLME) �with Quasi-Static CVFermi-Level Movement Efficiency (FLME)投影片編號 35 GGO Unpins the In0.2Ga0.8As Fermi level投影片編號 37Achieving a low Dit in ALD-Al2O3 on �In0.53Ga0.47As with short air exposure投影片編號 39投影片編號 40Key – high k’s/InGaAs interface Summary of samples投影片編號 43投影片編號 44投影片編號 45GGO scalabilityKey – high k’s/InGaAs interface 投影片編號 48投影片編號 49投影片編號 50投影片編號 51投影片編號 52投影片編號 53投影片編號 54Conclusion

Nano-electronics of high κdielectrics on high mobility channel semiconductors for...

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