MTJ Design Space
23
MTJ Design Space Design Space v3
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MTJ Design Space. Design Space v3. MTJ Data (Zhongming). Data supports modeling MTJ variation as a nominal R P and TMR with some σ Rp and σ TMR. MTJ Scaling. Critical Switching Current: If we scale MTJ dimensions to keep Δ constant, then: - PowerPoint PPT Presentation
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MTJ Design Space
Design Space v3
MTJ Data (Zhongming)
Data supports modeling MTJ variation as a nominal RP and TMR with some σRp and σTMR.
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0 500 1000 1500 2000 25000
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RP []
RA
P [
]
Wafer: 6.4.1, Chip: 1aR
Column 4: 150x45nm2
Column 7: 130x50nm2
Column 9: 170x50nm2
0 500 1000 1500 2000 25000
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RP []
RA
P [
]
Wafer: 6.4.1, Chip: 1cR
Column 4: 150x45nm2
Column 9: 170x50nm2
Critical Switching Current:
If we scale MTJ dimensions to keep Δ constant, then:
(Note: scaling MTJ dimensions theoretically has no effect on TMR)
MTJ Scaling
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0
0
ln1
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VTk
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Tk
MH
Tk
E
B
S
B
SK
B
211
2
VMe
I SC2
0 h
4
Gilbert Damp. Constant Magnetization Saturation
Spin-polarization Factor Demagnetization Anisotropy
Free Layer Volume Boltzmann Constant
Dirac Constant Natural Time Constant (~ 1ns)
Elemental Charge Pulse Width0BkKHSM
V
eh
230 slwdIC 21 s
lwR
212 and , sdswlwld
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RP vs. WN for Fixed IC Traces (Fengbo)
Upper bounds: Maximum resistance to support minimum desired write current– Empirically derived for RP & RAP for a given cell size
Bounds: RP & RAP (TMR)
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IBM90nm: RP vs. WN [RP]
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RP [
k]
WN [m]
IBM90nm: Boosting
0 0.5 1 1.5 20
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700700
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10001000
RP [
k]
WN [m]
IBM90nm: No Boosting
0 0.5 1 1.5 20
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IBM90nm: RP vs. WN [RAP]
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200200
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400400
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RA
P [
k]
WN [m]
IBM90nm: Boosting
0 0.5 1 1.5 20
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RA
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k]
WN [m]
IBM90nm: No Boosting
0 0.5 1 1.5 20
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IBM65nm: RP vs. WN [RP]
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600600
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10001000
1000R
P [
k]
WN [m]
IBM65nm: Boosting
0 0.5 1 1.5 20
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100
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RP [
k]
WN [m]
IBM65nm: No Boosting
0 0.5 1 1.5 20
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IBM65nm: RP vs. WN [RAP]
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RA
P [
k]
WN [m]
IBM65nm: Boosting
0 0.5 1 1.5 20
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P [
k]
WN [m]
IBM65nm: No Boosting
0 0.5 1 1.5 20
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IBM45nm: RP vs. WN [RP]
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1000R
P [
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WN [m]
IBM45nm: Boosting
0 0.5 1 1.5 20
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100
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600600
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700700
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RP [
k]
WN [m]
IBM45nm: No Boosting
0 0.5 1 1.5 20
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IBM45nm: RP vs. WN [RAP]
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IBM45nm: Boosting
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IBM45nm: No Boosting
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65nm Design Space Examples
65nm Design Space Example [FLASH]
Target Performance:– Write Time: 100µs-10ms– Read Time: < 10µs
Cell Size: 6F2 ~ WN = 0.10µm
MTJ Device Characteristics (Sample Distribution):– RA = 5Ωµm2
– TMR = 110%– Δ = 50– For 1ns switching with L = 170nm &W = 50nm
● IP→AP ≥ 375μA● IAP→P ≥ 550μA
CELL SIZE TOO SMALL → BETTER MTJs NEEDED13
65nm Design Space Example [eDRAM]
Target Performance:– Write Time: 5-10ns– Read Time: <10ns
Cell Size: 30F2 ~ WN = 0.50µm
MTJ Device Characteristics (Sample Distribution):– RA = 5Ωµm2
– TMR = 110%– Δ = 50– For 1ns switching with L = 170nm &W = 50nm
● IP→AP ≥ 375μA● IAP→P ≥ 550μA
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65nm: Nominal [eDRAM]
No Boosting
Wn = 0.50μm (30F2)
Write Time: 10ns
MTJ (Nominal):– IP→AP ≥ 358μA– IAP→P ≥ 525μA– RP = 749Ω
● RA = 5 [Ωμm2]● L = 170 [nm]● W = 50 [nm]
– TMR = 110%
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RP []
RA
P [
]
RP,MIN
RP,MAX
RAP,MIN
RAP,MAX
3 (MTJ)4 (MTJ)5 (MTJ)
65nm: MTJ Scaling [eDRAM]
No Boosting
Wn = 0.50μm (30F2)
Write Time: 10ns
MTJ (S = 0.75):– IP→AP ≥ 232μA– IAP→P ≥ 341μA– RP = 1332Ω
● RA = 5 [Ωμm2]● L = 128 [nm]● W = 38 [nm]
– TMR = 110%
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RP []
RA
P [
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RP,MIN
RP,MAX
RAP,MIN
RAP,MAX
3 (MTJ)4 (MTJ)5 (MTJ)
65nm: MTJ & RA Scaling [eDRAM]
No Boosting
Wn = 0.50μm (30F2)
Write Time: 10ns
MTJ (S = 0.75):– IP→AP ≥ 232μA– IAP→P ≥ 341μA– RP = 799Ω
● RA = 3 [Ωμm2]● L = 128 [nm]● W = 38 [nm]
– TMR = 110%
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0 500 1000 1500 2000 25000
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RP []
RA
P [
]
RP,MIN
RP,MAX
RAP,MIN
RAP,MAX
3 (MTJ)4 (MTJ)5 (MTJ)
65nm: Boosting [eDRAM]
Boosting
Wn = 0.50μm (30F2)
Write Time: 10ns
MTJ (Nominal):– IP→AP ≥ 358μA– IAP→P ≥ 525μA– RP = 749Ω
● RA = 5 [Ωμm2]● L = 170 [nm]● W = 50 [nm]
– TMR = 110%
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0 500 1000 1500 2000 2500 30000
500
1000
1500
RP []
RA
P [
]
RP,MIN
RP,MAX
RAP,MIN
RAP,MAX
3 (MTJ)4 (MTJ)5 (MTJ)
65nm: Boosting & MTJ Scaling [eDRAM]
Boosting
Wn = 0.50μm (30F2)
Write Time: 10ns
MTJ (S = 0.90):– IP→AP ≥ 306μA– IAP→P ≥ 448μA– RP = 925Ω
● RA = 5 [Ωμm2]● L = 153 [nm]● W = 45 [nm]
– TMR = 110%
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0 500 1000 1500 2000 2500 3000 35000
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RP []
RA
P [
]
RP,MIN
RP,MAX
RAP,MIN
RAP,MAX
3 (MTJ)4 (MTJ)5 (MTJ)
65nm Design Space Example [SRAM]
Target Performance:– Write Time: ~1ns– Read Time: <5ns
Cell Size: 120F2 ~ WN = 2.00µm
MTJ Device Characteristics (Sample Distribution):– RA = 5Ωµm2
– TMR = 110%– Δ = 50– For 1ns switching with L = 170nm &W = 50nm
● IP→AP ≥ 375μA● IAP→P ≥ 550μA
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65nm: Nominal [SRAM]
No Boosting
Wn = 2.00μm (120F2)
Write Time: 1ns
MTJ (Nominal):– IP→AP ≥ 375μA– IAP→P ≥ 550μA– RP = 749Ω
● RA = 5 [Ωμm2]● L = 170 [nm]● W = 50 [nm]
– TMR = 110%
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0 500 1000 1500 20000
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RP []
RA
P [
]
RP,MIN
RP,MAX
RAP,MIN
RAP,MAX
3 (MTJ)4 (MTJ)5 (MTJ)
65nm: MTJ Scaling [SRAM]
No Boosting
Wn = 2.00μm (120F2)
Write Time: 1ns
MTJ (S = 1.30):– IP→AP ≥ 556μA– IAP→P ≥ 815μA– RP = 443Ω
● RA = 5 [Ωμm2]● L = 221 [nm]● W = 65 [nm]
– TMR = 110%
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0 500 1000 15000
500
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RP []
RA
P [
]
RP,MIN
RP,MAX
RAP,MIN
RAP,MAX
3 (MTJ)4 (MTJ)5 (MTJ)
65nm: Boosting [SRAM]
Boosting
Wn = 2.00μm (120F2)
Write Time: 1ns
MTJ (Nominal):– IP→AP ≥ 375μA– IAP→P ≥ 550μA– RP = 749Ω
● RA = 5 [Ωμm2]● L = 170 [nm]● W = 50 [nm]
– TMR = 110%
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0 500 1000 1500 2000 2500 3000 35000
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RP []
RA
P [
]
RP,MIN
RP,MAX
RAP,MIN
RAP,MAX
3 (MTJ)4 (MTJ)5 (MTJ)
