Lecture 20 Power Optimization (Part 1)

Xuan ‘Silvia’ Zhang Washington University in St. Louis

http://classes.engineering.wustl.edu/ese461/

Power Dissipation

•  Dynamic power consumption –  switching current

•  Static power consumption –  short-circuit current –  leakage current

2

staticlkgshortdynavg PPPPP +++=

Dynamic Power

•  Switching current –  energy dissipated in half a cycle

–  dynamic power expression –  α is the average number of rising transitions in one

cycle

3

2

0

)2/(1

0 21

DD

Vf

CVCVdVdtdtdVCV

DD

∫∫ ==⎟⎠

⎞⎜⎝

⎛

fVCP DDoutdyn2α=

Static Power

•  Short-circuit currents –  β is the gain factor of s MOSFET –  Vth is the threshold voltage –  τ is the rise/fall time

4

τβ

α fVVP thDDshort3)2(

12−=

Static Power

•  Leakage currents

•  Other static power –  current flow from VDD to GND during idle time –  historically, NMOS circuits has high static power –  CMOS static power should be 0 –  might result from bus conflict where multiple drivers

attempt to drive a signal to different logic values

5

DDldsubthreshodiodelkg VIIP ⋅+= )(

Low Power Design Methodologies

•  Adapt process technology –  reduce capacitance –  Cfo is the input capacitance of fan-out gates –  Cw is the wire capacitance –  Cp is the parasitic capacitance

–  reduce leakage current –  reduce supply voltage

6

pwfoout CCCC ++=

( )2thDD

DDoutDDoutd

VVLW

VCIVCT

−⎟⎠

⎞⎜⎝

⎛==η

Low Power Design Methodologies

•  Reduce switch activity –  minimize glitches

–  nodes logically deeper more prone to signal glitches

7

Low Power Design Methodologies

•  Reduce switch activity –  minimize glitches –  minimize number of operations –  example: vector quantization (VQ) algorithm –  Xi are the elements of the input vector –  Cij are the elements of the codebook vector

8

Low Power Design Methodologies

•  Reduce switch activity –  minimize glitches –  minimize number of operations –  low power bus

•  Examples –  one-hot coding –  gray coding –  bus-inversion coding

9

Minimize Data Transition on Bus

10

Bus Coding

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Bus Invert Coding

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Low Power Design Methodologies

•  Reduce switch activity –  minimize glitches –  minimize number of operations –  low power bus (state machine encoding) –  scheduling and binding optimization

13

control-data-flow graph (CDFG)

Low Power Design Methodologies

•  Power down modes –  clock gating

–  enabled flip-flops –  memory partitioning –  power gating

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How Effective is Clock-Gating?

•  90% FF clock-gated •  70% power reduction

15

Low Power Design Methodologies

•  Voltage optimization and scaling –  multi-Vth optimization

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Low Power Design Methodologies

•  Voltage optimization and scaling –  multi-voltage domain –  dynamic voltage frequency scaling

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Resource Sharing

•  Save area and power

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Questions?

Comments?

Discussion?

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