High Performance 0.1 pm PD SO1 Tunneling-Biased MOSFETs (TBMOS) Kuo-Nan Yang, Yi-Lin Chan, Yu-Lin Chu, Hou-Yu Chen, Fu-Liang Yang, Chenming Hu

TSMC, Hsin-Chu, Taiwan, ROC Tel: +886-3-5781688extl201 e-mail: knyang@tsmc.com.tw

Abstract This paper for the first time proposes a new structure of

partially-depleted SO1 MOSFETs- Tunneling-Biased MOSFETs (TBMOS). In this structure, the floating body potential is pulled up by the carriers which tunnel from specially doped polysilicon gate to the floating body. Compared with bulk MOSFET (represented by body grounded device), TBMOS produces excellent swing (-66 mV/dec), and > 15 % increase in ID,SAT. TBMOS also has better hot carrier immunity than body grounded device.

Introduction Mobile and portable electronics have advanced rapidly and

there is an increasing demand for high performance and low power digital circuits. The main technology approach for reducing power has been power supply scaling. Scaling of power supply should be accompanied by threshold voltage reduction in order to preserve low V, device performance. Low V, unfortunately raises subthreshold leakage. One novel solution is to tie the gate to the substrate to operate the device as a dynamic threshold voltage MOSFET (DTMOS)[ 11. ’In that configuration, the gate input voltage forward biases the substratelsource junction and causes V, to decrease. But the gate voltage of a DTMOS has to be limited to approximately one diode voltage (-0.7 V at room temperature) to avoid significant junction leakage. To overcome this limitation, we propose a SO1 Tunneling-Biased MOS. It can operate under power supply voltages larger than 0.7 V. Not only does TBMOS have the advantage of conventional DTMOS but the body contact can also be eliminated.

Experiment and Characterization The transistors are fabricated with a partially-depleted 0.1

pm CMOS/SOI technology. The substrates are 8” SIMOX wafers with a buried oxide thickness of 1500 . Partially depleted transistors are processed on a 1900 thick silicon film. STI dielectrically isolates transistors. A polysilicon gate is deposited after thermal growth of a 16

Fig. l(a)-(b) shows the layout and electrical schematic of normal SO1 nMOS and conventional SO1 n-DTMOS with gate tied to body, respectively. Fig. l(c) introduces the layout of SO1 n-TBMOS. The purpose of extended thin-oxide and p+ polysilicon regions is to provide hole tunneling in order to increase the body potential in the on state. The floating body potential is limited below 0.7V even when V, is equal to 1 V as shown in Fig. 2. Fig. 3 displays the I-V characteristics of n-TBMOS and p-TBMOS, respectively. The difference between TBMOS and body grounded device is 15 % for n- TBMOS and 30 % for p-TBMOS because of reduced threshold voltage and increased mobility.

The comparison of gate to source current (with drain open)

gate oxide.

of DTMOS and TBMOS is exhibited in Fig. 4. It is obvious that the leakage of DTMOS is significantly larger than that of TBMOS, about three orders of magnitude. This implies TBMOS can operate under the power supply voltage V,, larger than 0.7 V.

TBMOS requires special gate design. Fig. 5 displays the cross-section of TBMOS along the line AA‘ seen in Fig. 1 (c). I,, and I,, represent the oxide tunneling currents in n+ and p+ polysilicon regions, respectively. In n-TBMOS under the bias condition of V,,=V,=O V, Fig. 6(b) shows IB=Ip+ when V, is below 1 V. The conduction mechanism of I,, is accumulation hole tunneling in the p+ poly region as shown in Fig. 6(a). When n-TBMOS operates under small V,, I,, is the current that pulls up V,. When V, is larger than 1 V, IN+,VET (Valence Band- Electron Tunneling current under n+ poly gate) starts to dominate IB[2]. On the other hand in Fig. 7(b), I,, is the accumulation electron tunneling current in the n+ poly region and its mechanism is shown in Fig. 7(a). Under small IV,[, I,, is the main current to pull down V,. When IV,I is larger than 1 V, I,+,,(Valence Band-Electron Tunneling current under the p+ poly gate) starts to dominate I,.

The subthreshold characteristics and GWMm under TBMOS with body floating is better than with body tied to ground as shown in Fig. 8-9. Another important advantage of TBMOS or DTMOS is the smaller threshold voltage variation compared with the devices with body tied to ground [4].

Fig. 10 exhibits the DC hot carrier reliability of TBMOS and the body grounded devices. Both n- and p-TBMOS have better hot carrier immunity. The reason for the reliability improvement is the reduced lateral electrical voltage across drain-to-body junction. Table I lists the comparisons among conventional bulk device, DTMOS, and the proposed TBMOS. TBMOS has better ID,SAT and subthreshold swing than conventional bulk devices, and is without the V,, limitation on DTMOS.

Conclusion Ideally, MOSFETs should have low subthreshold leakage in

the off-state and high drive current in the on-state. SO1 TBMOS can improve the performancelleakage tradeoff. TBMOS has reduced layout area and much lower input leakage at vd, >0.7 V than DTMOS.

References [l] F. Assaderaghi, et al., IEDM Tech. Digest, pp. 809-812, 1994. [2] E Assaderaghi, International Conference on Microelectronics, pp.

[3] Y. Shi, et al., IEEE TED, vol. 45, pp. 2355-2360, 1998. [4] Atsushi, et al., IEDM Tech. Digest, pp. 663-666,2000.

9-10,2000.

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I

I I I I I I

I I I

I I I I

I I I I

1

P I

> -0.3 I l

'0 0.2 0.4 0.6 0.8 1 0 -0.2 -0.4 -0.6 -0.8 - 1 VQS (VI VQS (VI

Fig. 2 The floating-body potential, V,, increases with increasing gate bias. W/L of n-TBMOS (left) and p-TBMOSMOS(right) is 10 pd0.1 pm.

h

4 E W

v1

c(

,-1.5 < E W

v) -1 c1

-0.5

n U

0 0.2 0.4 0.6 0.8 1 "0 -0.2 -0.4 -0.6 -0.8 -1

Fig. 3 The I-V characteristics of n-TBMOS(1eft) and p-TBMOS(right) compared with body VQS (VI 'QS (v)

grounded devices. W/L=IO pm/O. 1 pm.

A-

----- VG (VI VG (VI

Fig. 4 Comparison of the junction forward-bias current (I,) between DTMOS and TBMOS configurations. lib

N+ Implt.

Tunnel oxide Fig. 1 (a)-(c) Layouts and electrical schematics of conventional SOI, DTMOS, and TBMOS devices.

Fig. 5 The SO1 n-TBMOS(1eft) and p-TBMOS(right) cross-section along AA' line in Fig. 1 (c ). I,, is the tunneling current of N+ poly region and I,, is that of P+-poly region.

10.7.2 IEDM 01-935

-TBMOS

lo-"O 0.2 0.4 0.6 0.8 1 VGS (VI VG (VI

Fig. 8 Subthreshold characteristics of n-TBMOS(1eft) and p-TBMOS(right) compared with body grounded devices. W/L=IO pmj0.1 pm.

4 , . . . , . . . , . . . , . . , I . . . - I .5 L

2 3 0 . :--Bodygrp .-TBMOS

? : & ; E 2 . W

2 : . I 11 I /

Fig. 6 (a)The band diagrams of n-TBMOS's / VD= 0.1 . tunneling paths under n+ and p+ poly regions at . , , . 1 1 , , 1 1 , , , 1 , , L 0 positive V,. (b) I, of n-TBMOS. The bias " 0 0.2 0.4 0.6 0.8 1 condition is Vs,D=VB =O V. The area of p+ poly v- (VI

TBMOS - - - Body grounded

-0.2 -0.4 -0.6 -0.8 -1

VG (VI ci' .

Fig. 9 Transconductance G, of n-TBMOS(1eft) and p-TBMOS(right) compared with body grounded devices. W/L=IO pm/0.1 pm.

region is 10'pm2.

n

*TBMOS *TBMOS .

+Body grounded * -+ Body grounded

IND (Volt-') lND (Volt-' ) Fig. 10 Life time evaluation of n-TBMOS(lefi) and p-TBMOS(right) with respect to body grounded devices. W/L=lO pm/O.l pm.

Subthreshold swin

V,limit Fig. 7 (a)The band diagrams of p-TBMOS's tunneling paths under n+ and p+ poly regions at negative V,. (b) I, of p-TBMOS. The bias condition is VSlD=VB =O V. The area of n+ poly region is IO pm2.

Table 1. Comparison among three types of device structures.

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