[IEEE IEEE International Solid-State Circuits Conference - San Francisco, CA, USA (9-13 Feb. 2003)]...
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ISSCC 2003 / SESSION 18 / NYQUIST A/D CONVERTERS / PAPER 18.5 18.5 A 10b 150MS/s 123mW 0.18µm CMOS Pipelined ADC Sang-Min Yoo, Jong-Bum Park 1 , Hee-Suk Yang 1 , Hyuen-Hee Bae 1 , Kyoung-Ho Moon, Ho-Jin Park, Seung-Hoon Lee 1 , Jae-Hwui Kim Samsung Electronics, Yongin, Republic of Korea 1 Sogang University, Seoul, Republic of Korea Applications such as high-definition video systems, personal mobile communication equipment, and high-speed digital wire- less networks that make use of advanced CMOS VLSI, increas- ingly require high-resolution high-speed low power ADCs. Particularly, the ADCs for wired/wireless network applications and high-end imaging systems require 10b resolution at 150MS/s and need wideband sample-and-hold amplifiers (SHAs) to handle high frequency inputs. Conventional CMOS ADCs for high-speed applications have employed flash, folding, subrang- ing, and pipelined architectures. The pipelined ADC architecture has commonly been employed to optimize speed, power dissipa- tion, and chip area for applications with 10bits or more, at speeds exceeding 100MS/s [1-3]. This work proposes a 1.8V CMOS pipelined ADC to achieve a single-channel 10b 150MS/s performance based on (i) bootstrap- ping techniques to sample higher frequency inputs than the sam- pling rate, (ii) the MCS technique [3] to reduce the number of capacitors required in the multiplying D/A converter (MDAC) by 50%, and (iii) lastly, temperature- and supply-insensitive on-chip CMOS current/voltage (I/V) references. The proposed ADC in Fig. 18.5.1 consists of a SHA, two MDACs, three flash ADCs, dig- ital correction logic (DCL), on-chip I/V reference circuits, and on- chip decimators. Nonlinear interstage offsets and clock feedthrough errors are digitally corrected in the DCL by over- lapping two bits from 12bits to obtain 10bits. On-chip I/V refer- ences are required for stable high-speed operation that is diffi- cult to achieve with off-chip references at 150MS/s level. The on- chip decimators can reduce high-speed measurement cost. The wideband SHA requires input sampling switches with very low and constant on-resistance. Conventional CMOS switches hardly meet the requirements due to decreased gate-driving volt- ages with decreased supply voltages. Conventional bootstrap- ping circuits [4-5] reduce signal distortion due to switch on-resis- tance variations by keeping the gate-source voltage of the switches constant independent of input signal levels. However, conventional circuits based on deep sub-micron CMOS may have long-term reliability problems such as gate oxide overstress and breakdown between source, drain, gate, and body nodes of the switch transistors due to bias voltages exceeding the power sup- plies. The improved gate-bootstrapping circuits in Fig. 18.5.2 decrease the oxide failure and breakdown effects by employing 3.3V devices (instead of nominal 1.8V devices) with long channels and thick gate oxide in the transistors exposed to the high-voltage stress. The 3.3V devices surrounded by the dotted rectangles are utilized in I/O interface circuits in this specific 0.18µm CMOS. The parasitic elements and increased threshold voltage of the 3.3V devices prevent the NMOS sampling switch, M9, from maintaining constant gate-source voltage at high speed. While the on-resistance of M9 can be decreased with a large W/L ratio, the increased parasitic capacitance limits the VOUT capability as much as the W/L ratio. The proposed PMOS transistor, M10, con- nected in parallel with M9 minimizes the on-resistance and the parasitic capacitance between VIN and the bottom plate of C3. Note that M10 is driven by the on-chip clock Q2B with 1.8V rather than 3.3V. The extra 1.8V PMOS device, MP1, in parallel with the 3.3V NMOS sampling switch MN1 of the SHA, enables the switch on-resistance to be less sensitive to input signal lev- els and body effects. The input sampling capacitance is 1.2pF. The prototype ADC employs the MCS technique in the 4b MDACs for low power, high speed, and low noise coupling [3]. The technique reduces the required MDAC unit capacitors from 16 to 8 by merging two unit capacitors into a single capacitor based on the equal charge redistribution concept. The unit capacitor sizes in the first and second MDACs are 0.2pF and 0.1pF, respectively, considering the kT/C noise and the required 10b matching. The MDACs are based on a folded-cascode two- stage amplifier with a gain of 100dB. Properly laid out on-chip MOS bypass capacitors of 400pF suppress undesirable coupling noise from the power supplies and the substrate at high speed. The temperature- and supply-insensitive CMOS current refer- ences digitally calibrate device variations within +/-30% and generate on-chip voltage references for the prototype [6]. The on- chip voltage references can be optionally disabled so that off-chip voltage references can be used. The integrated I/V references with buffers occupy a die area of 180μm x 300μm and consume 6.5mW at 150MHz. The proposed ADC was implemented in 0.18µm single-poly CMOS as shown in Fig. 18.5.3. The capacitors have a Metal- Insulator-Metal architecture. The ADC occupies an active die area of 2.2mm 2 and dissipates 123mW at 1.8V and 150MS/s. The measured DNL and INL are within -0.56/+0.69 LSB and - 1.50/+0.68 LSB as illustrated in Fig. 18.5.4. Figure 18.5.5 demonstrates a typical FFT spectrum measured with a 10MHz input at 150MS/s. The output data are captured at half the 150MHz clock with the on-chip decimators. The measured dynamic performance of the ADC is shown in Fig. 18.5.6. The SFDR and SNDR in Fig. 18.5.6a are measured with different sampling frequencies up to 150MS/s at a 10MHz input. The SFDR and SNDR in Fig. 18.5.6b are measured with increasing input frequencies and a 140MHz clock. Both the SFDR and SNDR are not significantly degraded with input frequencies up to 80MHz, which is the maximum that can be measured with the currently available signal generator. Off-chip and on-chip CMOS voltage references were evaluated and compared. In all mea- surement conditions, both references demonstrated almost the same SFDR, although the on-chip references showed a slightly better SNDR than the off-chip circuits. The measured perfor- mance of the prototype ADC is summarized in Fig. 18.5.7. References [1] S. M. Jamal, D. Fu, P. Hurst, and S. Lewis, "A 10b 120MSample/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration," ISSCC Dig. Tech. Papers, pp. 172-173, Feb. 2002. [2] L. Sumanen et al., "A 10-bit 200-MS/s CMOS parallel pipeline A/D con- verter," IEEE JSSC, vol. 36, no. 7, pp. 1048-1055, July 2001. [3] S. M. Yoo, T. H. Oh, J. W. Moon, S. H. Lee, and U. K. Moon, "A 2.5V 10b 120 MSample/s CMOS Pipelined ADC with high SFDR," Proc. CICC, pp. 441-444, May 2002. [4] A. Abo and P. Gray, "A1.5-V, 10-bit, 14.3-MS/s CMOS Pipelined Analog- to-Digital Converter," IEEE JSSC, vol. 34, no. 5, pp. 599-606, May 1999. [5] L. Singer, S. Ho, M. Timko, and D. Kelly, "A 12b 65MSample/s CMOS ADC with 82dB SFDR at 120MHz," ISSCC Dig. Tech. Papers, pp. 38-39, Feb. 2000. [6] M. J. Kim, H. S. Yoon, Y. J. Lee, and S. H. Lee, "An 11b 70MHz 1.2mm 2 49mW 0.18μm CMOS ADC with On-chip Current/Voltage References," Proc. ESSCIRC, pp. 463-466, Sep. 2002. • 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE
Transcript of [IEEE IEEE International Solid-State Circuits Conference - San Francisco, CA, USA (9-13 Feb. 2003)]...
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ISSCC 2003 / SESSION 18 / NYQUIST A/D CONVERTERS / PAPER 18.5
18.5 A 10b 150MS/s 123mW 0.18µm CMOS Pipelined ADC
Sang-Min Yoo, Jong-Bum Park1, Hee-Suk Yang1, Hyuen-Hee Bae1,Kyoung-Ho Moon, Ho-Jin Park, Seung-Hoon Lee1, Jae-Hwui Kim
Samsung Electronics, Yongin, Republic of Korea 1Sogang University, Seoul, Republic of Korea
Applications such as high-definition video systems, personalmobile communication equipment, and high-speed digital wire-less networks that make use of advanced CMOS VLSI, increas-ingly require high-resolution high-speed low power ADCs.Particularly, the ADCs for wired/wireless network applicationsand high-end imaging systems require 10b resolution at150MS/s and need wideband sample-and-hold amplifiers (SHAs)to handle high frequency inputs. Conventional CMOS ADCs forhigh-speed applications have employed flash, folding, subrang-ing, and pipelined architectures. The pipelined ADC architecturehas commonly been employed to optimize speed, power dissipa-tion, and chip area for applications with 10bits or more, atspeeds exceeding 100MS/s [1-3].
This work proposes a 1.8V CMOS pipelined ADC to achieve asingle-channel 10b 150MS/s performance based on (i) bootstrap-ping techniques to sample higher frequency inputs than the sam-pling rate, (ii) the MCS technique [3] to reduce the number ofcapacitors required in the multiplying D/A converter (MDAC) by50%, and (iii) lastly, temperature- and supply-insensitive on-chipCMOS current/voltage (I/V) references. The proposed ADC inFig. 18.5.1 consists of a SHA, two MDACs, three flash ADCs, dig-ital correction logic (DCL), on-chip I/V reference circuits, and on-chip decimators. Nonlinear interstage offsets and clockfeedthrough errors are digitally corrected in the DCL by over-lapping two bits from 12bits to obtain 10bits. On-chip I/V refer-ences are required for stable high-speed operation that is diffi-cult to achieve with off-chip references at 150MS/s level. The on-chip decimators can reduce high-speed measurement cost.
The wideband SHA requires input sampling switches with verylow and constant on-resistance. Conventional CMOS switcheshardly meet the requirements due to decreased gate-driving volt-ages with decreased supply voltages. Conventional bootstrap-ping circuits [4-5] reduce signal distortion due to switch on-resis-tance variations by keeping the gate-source voltage of theswitches constant independent of input signal levels. However,conventional circuits based on deep sub-micron CMOS may havelong-term reliability problems such as gate oxide overstress andbreakdown between source, drain, gate, and body nodes of theswitch transistors due to bias voltages exceeding the power sup-plies.
The improved gate-bootstrapping circuits in Fig. 18.5.2 decreasethe oxide failure and breakdown effects by employing 3.3Vdevices (instead of nominal 1.8V devices) with long channels andthick gate oxide in the transistors exposed to the high-voltagestress. The 3.3V devices surrounded by the dotted rectangles areutilized in I/O interface circuits in this specific 0.18µm CMOS.The parasitic elements and increased threshold voltage of the3.3V devices prevent the NMOS sampling switch, M9, frommaintaining constant gate-source voltage at high speed. Whilethe on-resistance of M9 can be decreased with a large W/L ratio,the increased parasitic capacitance limits the VOUT capability asmuch as the W/L ratio. The proposed PMOS transistor, M10, con-nected in parallel with M9 minimizes the on-resistance and theparasitic capacitance between VIN and the bottom plate of C3.
Note that M10 is driven by the on-chip clock Q2B with 1.8Vrather than 3.3V. The extra 1.8V PMOS device, MP1, in parallelwith the 3.3V NMOS sampling switch MN1 of the SHA, enablesthe switch on-resistance to be less sensitive to input signal lev-els and body effects. The input sampling capacitance is 1.2pF.
The prototype ADC employs the MCS technique in the 4bMDACs for low power, high speed, and low noise coupling [3].The technique reduces the required MDAC unit capacitors from16 to 8 by merging two unit capacitors into a single capacitorbased on the equal charge redistribution concept. The unitcapacitor sizes in the first and second MDACs are 0.2pF and0.1pF, respectively, considering the kT/C noise and the required10b matching. The MDACs are based on a folded-cascode two-stage amplifier with a gain of 100dB. Properly laid out on-chipMOS bypass capacitors of 400pF suppress undesirable couplingnoise from the power supplies and the substrate at high speed.The temperature- and supply-insensitive CMOS current refer-ences digitally calibrate device variations within +/-30% andgenerate on-chip voltage references for the prototype [6]. The on-chip voltage references can be optionally disabled so that off-chipvoltage references can be used. The integrated I/V referenceswith buffers occupy a die area of 180µm x 300µm and consume6.5mW at 150MHz.
The proposed ADC was implemented in 0.18µm single-polyCMOS as shown in Fig. 18.5.3. The capacitors have a Metal-Insulator-Metal architecture. The ADC occupies an active diearea of 2.2mm2 and dissipates 123mW at 1.8V and 150MS/s. Themeasured DNL and INL are within -0.56/+0.69 LSB and -1.50/+0.68 LSB as illustrated in Fig. 18.5.4. Figure 18.5.5demonstrates a typical FFT spectrum measured with a 10MHzinput at 150MS/s. The output data are captured at half the150MHz clock with the on-chip decimators. The measureddynamic performance of the ADC is shown in Fig. 18.5.6. TheSFDR and SNDR in Fig. 18.5.6a are measured with differentsampling frequencies up to 150MS/s at a 10MHz input. TheSFDR and SNDR in Fig. 18.5.6b are measured with increasinginput frequencies and a 140MHz clock. Both the SFDR andSNDR are not significantly degraded with input frequencies upto 80MHz, which is the maximum that can be measured with thecurrently available signal generator. Off-chip and on-chip CMOSvoltage references were evaluated and compared. In all mea-surement conditions, both references demonstrated almost thesame SFDR, although the on-chip references showed a slightlybetter SNDR than the off-chip circuits. The measured perfor-mance of the prototype ADC is summarized in Fig. 18.5.7.
References[1] S. M. Jamal, D. Fu, P. Hurst, and S. Lewis, "A 10b 120MSample/sTime-Interleaved Analog-to-Digital Converter with Digital BackgroundCalibration," ISSCC Dig. Tech. Papers, pp. 172-173, Feb. 2002.[2] L. Sumanen et al., "A 10-bit 200-MS/s CMOS parallel pipeline A/D con-verter," IEEE JSSC, vol. 36, no. 7, pp. 1048-1055, July 2001.[3] S. M. Yoo, T. H. Oh, J. W. Moon, S. H. Lee, and U. K. Moon, "A 2.5V 10b120 MSample/s CMOS Pipelined ADC with high SFDR," Proc. CICC, pp.441-444, May 2002.[4] A. Abo and P. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipelined Analog-to-Digital Converter," IEEE JSSC, vol. 34, no. 5, pp. 599-606, May 1999.[5] L. Singer, S. Ho, M. Timko, and D. Kelly, "A 12b 65MSample/s CMOSADC with 82dB SFDR at 120MHz," ISSCC Dig. Tech. Papers, pp. 38-39,Feb. 2000.[6] M. J. Kim, H. S. Yoon, Y. J. Lee, and S. H. Lee, "An 11b 70MHz 1.2mm2
49mW 0.18µm CMOS ADC with On-chip Current/Voltage References,"Proc. ESSCIRC, pp. 463-466, Sep. 2002.
• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE
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ISSCC 2003 / February 12, 2003 / Salon 7 / 10:45 AM
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Figure 18.5.1: Proposed 10b 150MS/s ADC. Figure 18.5.2: Proposed gate bootstrapping circuits.
Figure 18.5.3: Die photograph of the prototype ADC.
Figure 18.5.5: Measured FFT spectrum (1/2 fs down sampled).
Figure 18.5.4: Measured DNL and INL.
DIGITAL CORRECTION LOGIC
4bMDAC1SHA
4b FLASHADC1
AIN
4b
10b DOUT
4b FLASHADC2
4b FLASHADC3
4bMDAC2
CURRENT/VOLTAGE REFERENCES
TIMINGCIRCUIT
Q1
Q2Q2!
Q1!
DECIMATOR ( 1/1, 1/2, 1/4 of fs )
10b
4b 4b
Q2B
VDD
M1 M2
C1 C2 C3
M3M8
VDD
M5
M6M7
M4
M11 M12
M13
M9
M10VSS
VOUT
VIN
Q2B Q2
Q2
Q2
Q2B
Q2B
Q2B
VSS
! 3.3 V DEVICEFor Reliability
Sampling SW & SHA
S (VIN)
G (VDD+VIN)
VDD
G (VDD)! Proposed Extra PMOS
For High Linearity
MP1
MN1
AMP
Cs
F1 F3F2
DC
L &
D
EC
IMA
TO
R
I/V REFERENCE
SHA MDAC1 MDAC2
CL
OC
K
-2
-1
0
1
2
CODE
DN
L [
LS
B/1
0b]
0 1023
-2
-1
0
1
2
CODE
INL
[L
SB
/10b
]
0 1023
fin = 10MHz, fs = 150MHz (2048 FFT)
-120
-90
-60
-30
0
Frequency [MHz]
[dB
]
0 37.5
0
20
40
60
80
40 80 120 160fs [MHz]
[dB
]
SFDRSNDRfin = 10MHz
0
20
40
60
80
0 20 40 80 100fin [MHz]
[dB
]
SFDRSNDRfs = 140MHz
(a)
(b)Figure 18.5.6: Measured SFDR and SNDR versus (a) sampling and (b)input frequencies.
• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE
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• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE
Figure 18.5.7: Performance summary of the prototype ADC.
2.2mm2 (=1.4mm ×××× 1.6mm)Active Die Area
123mW at 150MS/sADC Power
—1.50LSB / +0.68LSBINL
—0.56LSB / +0.69LSBDNL
64.4dB at 10MHz, 64.8dB at 70MHz65.6dB at 10MHz
SFDR (at 140MS/s)SFDR (at 150MS/s)
54.0dB at 10MHz, 52.2dB at 70MHz52.2dB at 10MHz
SNDR (at 140MS/s)SNDR (at 150MS/s)
1 Vp-pInput Range
0.18µm 1 poly 6 metal CMOSProcess
150MS/sConversion Rate
10 bitsResolution
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• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE
DIGITAL CORRECTION LOGIC
4bMDAC1SHA
4b FLASHADC1
AIN
4b
10b DOUT
4b FLASHADC2
4b FLASHADC3
4bMDAC2
CURRENT/VOLTAGE REFERENCES
TIMINGCIRCUIT
Q1
Q2Q2!
Q1!
DECIMATOR ( 1/1, 1/2, 1/4 of fs )
10b
4b 4b
Figure 18.5.1: Proposed 10b 150MS/s ADC.
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• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE
Q2B
VDD
M1 M2
C1 C2 C3
M3M8
VDD
M5
M6M7
M4
M11 M12
M13
M9
M10VSS
VOUT
VIN
Q2B Q2
Q2
Q2
Q2B
Q2B
Q2B
VSS
! 3.3 V DEVICEFor Reliability
Sampling SW & SHA
S (VIN)
G (VDD+VIN)
VDD
G (VDD)! Proposed Extra PMOS
For High Linearity
MP1
MN1
AMP
Cs
Figure 18.5.2: Proposed gate bootstrapping circuits.
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• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE
Figure 18.5.3: Die photograph of the prototype ADC.
F1 F3F2
DC
L &
D
EC
IMA
TO
R
I/V REFERENCE
SHA MDAC1 MDAC2
CL
OC
K
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• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE
-2
-1
0
1
2
CODE
DN
L [
LS
B/1
0b]
0 1023
-2
-1
0
1
2
CODE
INL
[L
SB
/10b
]
0 1023Figure 18.5.4: Measured DNL and INL.
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fin = 10MHz, fs = 150MHz (2048 FFT)
-120
-90
-60
-30
0
Frequency [MHz]
[dB
]
0 37.5
Figure 18.5.5: Measured FFT spectrum (1/2 fs down sampled).
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0
20
40
60
80
40 80 120 160fs [MHz]
[dB
]
SFDRSNDRfin = 10MHz
0
20
40
60
80
0 20 40 80 100fin [MHz]
[dB
]
SFDRSNDRfs = 140MHz
(a)
(b)
Figure 18.5.6: Measured SFDR and SNDR versus (a) sampling and (b) input frequencies.
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2.2mm2 (=1.4mm ×××× 1.6mm)Active Die Area
123mW at 150MS/sADC Power
—1.50LSB / +0.68LSBINL
—0.56LSB / +0.69LSBDNL
64.4dB at 10MHz, 64.8dB at 70MHz65.6dB at 10MHz
SFDR (at 140MS/s)SFDR (at 150MS/s)
54.0dB at 10MHz, 52.2dB at 70MHz52.2dB at 10MHz
SNDR (at 140MS/s)SNDR (at 150MS/s)
1 Vp-pInput Range
0.18µm 1 poly 6 metal CMOSProcess
150MS/sConversion Rate
10 bitsResolution
Figure 18.5.7: Performance summary of the prototype ADC.
