Electrostatic10 GHz

Wils

CarletoEmail: w

Abstract – Two 10-GHz LNAs, one with ESDanother without ESD protection were designed in 0.13 μm RFCMOS technology. The ESD prcompasses PI topology ESD protection, compriESD protection diodes, LNA gate inductor andprotection diodes, and RC-triggered MOSFETThe desired level of ESD protection for the LNthe Human Body Model (HBM). Measured resshowed that both have similar performance, aresults showed that an ESD protection higher tachieved. The LNA with ESD protection passstress without showing leakage and degradparameters and noise figure, demonstrating thRF parameters can be minimized by choosingESD protection and by taking it into account eprocess.

I. INTRODUCTION

IC design enhancements have dramaticadimensions of IC features such as gate oxidwidth, and diffusion depth. With each new tnew ESD protection solutions need to be desivalidated. Among the different types of ICs,ones that pose a greater challenge from an design perspective, due to the continued increfrequency and degradation of RF parameterintroduction of ESD protection circuits. Thertection is a subject that must be considered ithe RF circuit design in order to minimize ththe RF performance.

The three main ESD testing models at theel that IC manufacturers and end users use tothe human body model (HBM), machine mcharged device model (CDM). These modelsthe main ESD type of stress that a device mayduring its manufacturing, handling during assing of printed circuit boards (PCB). These tdestructive tests, if an IC is overstressed abovetion voltage threshold. The only informationwhether an IC has passed or failed a certain Eel. In this paper, only the HBM will be discuss

The most widely used ESD HBM test ANSI/ESDA/JEDC JS-001 [1], which was provide the ESD test results of this paper. Twas developed to emulate the discharge of charged with an electrostatic voltage touchingan electronic component with a finger. The

c Discharge Protection fz Low Noise Amplifier

son J. Bortoletto Machado, Calvin Plett

Department of Electronics on University, Ottawa, ON, Canada K1S 5B6

wmachado@doe.carleton.ca, cp@doe.carleton.ca

D protection and and implemented

rotection used en-ising the primary d secondary ESD T power clamps. NA was 2 KV for sults of the LNAs and the ESD test than 2 KV can be sed a 2 KV ESD dation of the S-at degradation of

g the appropriate arly in the design

ally reduced the e thickness, gate technology node, igned, tested, and , RF ICs are the

ESD protection ease of operation rs caused by the refore, ESD pro-in early stages of he degradation of

e component lev-o qualify ICs are:

model (MM), and s try to replicate y be subjected to sembly, and test-three models are e its ESD protec-

n they provide is ESD voltage lev-sed.

standard is the the one used to

The HBM testing f a human being g the terminals of e HBM network

consists of a 100 pF capacitor in seras showed in Figure 1. A high voltathe capacitor with the ESD voltagethrough the 1.5 KΩ between two pi(DUT). Typically, all pin combinati

Figure 1. Basic HBM

A full chip ESD protection is sD1 and D2 provide the primary proCDM ESD events; the series resistD4 provide the secondary protectioand the ESD power clamp providesbetween VDD and VSS.

Figure 2. Full Chip ESD P

The series resistor RS and diodvoltage divider in order to lower thof the main circuit and also limitingevent (~10A for 500V). In the case series resistor is not possible as it degradation of the RF parameters.

II. ESD PROTECTI

The parasitic input capacitanceLNA as shown in Figure 3 encompainput of the LNA such as bondingwork, gate-drain capacitance of M[2]. The use of an L-type network a

for a

ries with a 1.5 KΩ resistor, age supply is used to charge e and then it is discharged ins of the device under test ions are tested.

M Test Circuit

shown in Figure 2. Diodes tection for HBM, MM, and tor RS, and diodes D3 and on for a CDM ESD event; s a path for the ESD current

Protection Scheme

des D3 and D4 are used as he voltage at the input gate g the current during a CDM of a RF circuit the use of a would cause unacceptable

ION TOPOLOGY

e (Cp) at the input of the asses all capacitances at the g pad, ESD protection net-

M1, and wiring capacitance as shown is very restrictive

978-1-4799-4885-7/14/$31.00 ©2014 IEEE

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and almost impossible to match the input if thcitance is too large. As the frequency increrange, the L-type network doesn’t work becaamount of parasitic capacitance decreases wi[2], as showed in (1):

,

Figure 3. Common Source LNA Schematic with L-Ty

A PI-type network as depicted in Figure 4degree of freedom in comparison with the L-it has an additional component. The LNA comprises the primary ESD protection devicetor (Lg) and the secondary ESD protection [2]very similar to the traditional ESD protectionin Figure 2 with the series resistance beinginductor. The PI-type network was used duequency of operation (10 GHz) and the extra dthat facilitates the matching of the LNA input

Figure 4. Common-Source LNA Schematic with PI ESD

III. LNA ARCHITECTURE

A common source cascode LNA configsource follower output buffer, was used for cascode configuration is used to minimize thethe common source transistor and to facilitapedance matching. A simultaneous noise and technique was used for the design. The schemcircuit is shown in Figure 5.

The LNA without ESD protection has thture, only the ESD protection network is remtion of the ESD network changed the inputherefore the values of Lg and Ls needed to be

he parasitic capa-ases to the GHz

ause the tolerated ith the frequency

(1)

ype ESD Protection

4, offers an extra -type network, as

ESD protection e, the gate induc-. This network is

n network shown g replaced by an e to the high fre-egree of freedom impedance.

D Protection Network

E

guration, with a this project. The e Miller effect of ate the input im-

power matching matic of the LNA

he same architec-moved. The addi-ut matching and adjusted.

Figure 5. Common-Source LNA Schematic

IV. ESD PROTECTI

For the primary and secondarytrench isolation (STI) bounded diolow parasitic capacitance. The diodtransmission line pulse (TLP) datprovided by the foundry.

A. Primary ESD Protection DeviceMultiple-finger diodes were use

ter and minimize the area, and henance and the resistance, as they dirmance [2].

The primary ESD protection c(SX) diode between the RF input a(NW) 2-string diode between the inwere sized to withstand an HBM ESthan 2 KV.

The P+/NW 2-string diode was long emitter fingers with a total pthe size that would be required (220one diode. This was done to reducehalf, in order to keep the resistancekeep the voltage at the gate of the L

The N+/SX diode was designedthode fingers with a total perimeterto a maximum current carrying capan ESD transient. A smaller diode, capacity of about 2 A, would satisftage, but a bigger size was used incapacity closer to the 2-string diodelar level of protection.

B. Secondary ESD Protection DeviThe secondary ESD protection

N+/SX diode to ground and a P+/Ner, these diodes are smaller as mthrough the primary diodes during atantly, they are used to lower the cascode LNA, mainly during an ES

The fact that the gate inductor (about 4 Ohms) significantly smalleommended (50 Ohms - 100 Ohms)flowing through the secondary diotransient. Consequently, the size of

c with Pi ESD Protection Network

ION DESiGN

y ESD protections, shallow des were used due to their

des were sized based on the a and process information

es ed to maximize the perime-nce minimizing the capacit-rectly affect the RF perfor-

comprises an N+/substrate and VSS and a P+/N-Well nput and VDD. The diodes SD transient voltage greater

designed with four 55 µm erimeter of 440 µm; twice 0 µm, 2.5A) if we had only e the diode on-resistance in e of the path low, and help

LNA transistor low.

d with three 55 µm long ca-r of 330 µm. This translates pacity of about 3 A during e.g. 220 µm with a current

fy a > 2 KV threshold vol-nstead, obtaining a current es, in order to provide simi-

ices also was designed with an

NW diode to VDD. Howev-most of the current flows an ESD event; most impor-voltage at the gate of the

D CDM transient.

(Lg) has a series resistance er than what would be rec-), leads to a higher current ode during an ESD CDM

f the secondary P+/NW and

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N+/SX protection diodes was designed with a perimeter of 100 µm to be able to handle a current greater than 1 A.

C. Output ESD Protection Devices An output ESD protection similar to the primary ESD pro-

tection was used in the output pin of the LNA.

D. Power Rails ESD Protection The power rails ESD protection is necessary to provide a

current path between VDD and VSS during ESD events. An RC-triggered power clamp was chosen over the other options because it doesn’t use parasitic devices, it is immune to lat-chup, and has very low on-resistance [3].

An RC-clamp with a low on-resistance is important to pro-tect the LNA input transistor by keeping the gate voltage be-low the oxide breakdown voltage during an ESD event.

The RC-power clamp size was chosen based on the foun-dry TLP data. A 4000 µm RC-clamp with current capacity greater than 5.5A and an on-resistance of 0.4 Ohms were used. As the RC-power clamp is placed between VDD and VSS it doesn’t affect the RF parameters.

V. SIMULATION AND MEASUREMENT RESULTS

A. Similations Results The photograph of the chip is shown in Figure 6. The im-

age shows both LNAs, with and without ESD protection, and test structures. The location of the RC Clamp and the elements of the PI network are indicated. The device was manufactured using an eight metal (7 Cu, 1 Al), single poly, tungsten con-tact, STI, Co silicide 0.13 µm RF CMOS process.

Figure 6. Chip Photograph Showing LNA With and Without ESD Protection

and Test Structures.

Simulations of the extracted circuit of both LNAs were carried out and compared. During the comparison of measured and simulated results, it was noticed that the wrong extracted data set was used to tune both LNAs before tape-out; i.e. RC instead of RLC extracted circuit was used to optimize the pa-rameters at the center frequency. This caused a downward frequency shift on the measured LNA parameters. The results of RC simulation are summarized in Table I, and the following can be concluded:

TABLE I. SIMULATION RESULTS SUMMARY

Parameter LNA without ESD

Protection LNA with ESD

Protection Noise figure 2.4 dB 3.4 dB

S11 -16.2 dB -48.2 dBS21 17.4 dB 17.6 dB

• Noise figure: the ESD protection contributes with an increase of 1 dB, this is mainly due to the extra parasitic ca-pacitance and resistance introduced by the ESD protection, as shown in Figure 7. Moreover, the fact that wrong extracted data was used to tune the LNAs has also contributed to this difference

Figure 7. Simulated Noise Figure LNA with ESD Protection vs. LNA

without ESD Protection.

• S11: the LNA with ESD protection has a lower S11 than the LNA without ESD protection; since both are ade-quate, this is of little importance; however, as expected, S11 of the LNA with ESD protection has a smaller bandwidth due to the capacitance introduced by the ESD protection

• S21: the gain for both LNAs is practically the same; this is because the CLC PI-network formed by the capacitan-ces of the primary and secondary ESD protections and Lg, is a nearly lossless CLC matching network

Figure 8. Simulated S21 LNA with ESD Protection vs. LNA without ESD

Protection.

B. RF Measurement Results There was a significant discrepancy between the measured

and simulated results, particularly for noise figure and S21.

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There are a couple of reasons that can explain that: first the use of wrong extracted data set to tune the LNAs, as explained above; second the absence of on-chip power supply decoupl-ing capacitors causing the RF return current to be done through the external power supply. As the layout for both LNAs is similar, even though they may have been affected differently by lack of decoupling capacitance, it is still worth-while to compare both LNA measured results. Table II shows a summary of the results, measured at 9 GHz at the peak gain.

TABLE II. MEASUREMENT RESULTS SUMMARY

Parameter LNA without ESD

Protection LNA with ESD

Protection Noise figure 6.8 dB 7.0 dB

S11 -13.8 dB -13.3 dBS21 5.3 dB 7.9 dB

Comparing the measurement results of the LNA with ESD protection with the LNA without ESD protection, we conclude that:

• LNA with ESD has 0.2 dB higher noise figure

• Both LNAs have adequate S11

• LNA with ESD has 2.6 dB higher S21

C. ESD Test Results The LNA without ESD protection, as expected, has failed

50V HBM, the lowest stress voltage setting of the ESD test equipment, for both RFIN vs. VSS and RFIN vs. VDD. The curve tracer after ESD test indicated a short between RFIN and VSS, as shown in Figure 9.

Figure 9. LNA without ESD Protection, Curve Trace Pre and Post +50 V

Zap, RFIN vs. VSS

All RF parameters showed some degradation. The ones most affected were noise figure that went from 6.9 dB to 27 dB, and S21 that went from 5.1 dB to -20.3 dB.

The LNA with ESD protection passed 2 KV without show-ing any degradation of the RF parameters. Figure 10 is the curve tracer results after the 2 KV ESD zap of RFIN vs. VSS.

During the post ESD RF parameters measurement, it was noticed when measuring a correlation device that there was shift of about +0.5 dB in the S21 and -1 dB for noise figure,

that were attributed to the calibration of the measurement equipment and probe contact, which was subtracted from the post measurement results of the stressed devices. The results after ESD stress is shown in Table III.

Figure 10. LNA with ESD Protection, Curve Trace Pre and Post +2 KV Zap,

RFIN vs. VSS

TABLE III. MEASUREMENT RESULTS PRE AND POST ESD TEST 2 KV, FOR RFIN VS. VSS AND RFIN VS. VDD

RFIN VS. VSS RFIN VS. VDDParameter Pre-ESD Post ESD Pre-ESD Post ESDNoise figure 6.8 dB 6.5 dB 6.9 dB 6.6 dB

S11 -12.2 dB -12.4 dB -12.7dB -12.7dBS21 8.2 dB 8.6 dB 8.7 dB 8.8 dB

The results presented in Table II and table III show that the PI ESD protection while producing minimal degradation of the LNA RF parameters, it provides an ESD threshold voltage higher than 2 KV at the LNA input.

VI. CONCLUSIONS

Although previous work has shown ESD protection at lower frequencies [4], in this work, we have demonstrated that the PI ESD protection can be achieved for a 10 GHz LNA. The protection circuit uses a CLC configuration comprising the primary ESD protection diodes, the LNA gate inductor and the secondary ESD protection diodes, and RC-triggered MOSFET power clamps. The resulting ESD protection thre-shold is higher than 2 KV, while minimizing the degradation of the LNA RF parameters.

REFERENCES

[1] JS-001-2012 ESDA/JEDEC Joint Standard For Electrostatic Discharge Sensitivity Testing Human Body Model (HBM) - Component Level, Rome-NY, Arlington-VA: ANSI/ESDA/JEDEC, 2012.

[2] P. Leroux and M. Steyaert, LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers, Dordrecht: Springer, 2005.

[3] S. H. Voldman, ESD Circuits and Devices, West Sussex, England: John Wiley & Sons Ltd, 2006.

[4] Gonzalez, J.L.; Solar, H.; Adin, I.; Mateo, D.; Berenguer, R., "A 16-kV HBM RF ESD Protection Codesign for a 1-mW CMOS Direct Conversion Receiver Operating in the 2.4-GHz ISM Band," IEEE Transactions on Microwave Theory and Techniques, vol.59, no.9, pp.2318,2330, Sept. 2011

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