A Current-Output DAC for Low-Power Low-NoiseLog-Domain ΔΣ Modulators

Mohamed A. Shaheen and Anas A. Hamoui (deceased)Dept. of Electrical & Computer Engineering

McGill UniversityMontreal, QC, Canada

mohamed.shaheen@mail.mcgill.ca

Yvon SavariaDepartement de genie electriqueEcole Polytechnique de Montreal

Montreal, QC, Canadayvon.savaria@polymtl.ca

Abstract—In this paper, a novel low-noise current-output DACsuitable for incorporation in multibit log-domain ΔΣ modula-tors is proposed, eliminating the need for a voltage-to-currentconversion stage in the feedback path and the associated resistorthermal noise. The paper demonstrates how appropriately scaledswitched-current elements and the introduction of additionalcurrent sources enable the realization of a full current swing atthe proposed DAC output, and evaluates the design parameters toachieve the required signal swing within a ΔΣ modulator loop.Analysis and simulation of the various design tradeoffs involvedis presented, and it is demonstrated that the proposed current-output DAC is suitable for very low-power applications with low-to-medium speed requirements.

I. INTRODUCTION

Log-domain circuit techniques have previously been pro-posed in low-power low-voltage continuous-time (CT) ΔΣmodulators [1] [2]. In contrast to traditional internally-linearimplementations, log-domain systems rely on compression ofthe signal at the input and expansion of the signal at the output,resulting in internally nonlinear signals while maintaining alinear input-output relationship. Therefore, log-domain sys-tems maintain low internal voltage swings, enabling designswith very low supply voltages [3]. Additionally, log-domainimplementations can achieve higher power efficiency than theiractive RC and gm-C counterparts [4]. This is in part due tothe operation of transistors in weak inversion.

Previously proposed quantizer and DAC circuits for log-domain ΔΣ modulators performed single-bit conversion [1],limiting the stability and resolution performance of log-domainΔΣ modulators. To realize multibit log-domain ΔΣ modula-tors [2], new circuit realizations are needed for both the quanti-zation and digital-to-analog conversion. The circuit realizationof the DAC is particularly critical since circuit noise generatedby the feedback DAC appears directly at the ΔΣ modulatorinput, and therefore is not attenuated by the ΔΣ modulatorloop-filter [5].

This paper presents a novel low-power low-noise current-output digital-to-analog conversion stage suitable for multibitlog-domain ΔΣ modulators. The challenge of realizing low-noise digital-to-analog conversion in multibit log-domain ΔΣmodulators is presented in Section II. In Section III, a low-noise multibit DAC implementation is proposed and the param-eters required to generate the DAC transfer curved are derived.The simulation results of the proposed DAC, and the associated

vDACc

t

DC bias

vx t vy tx ty n

vDACc t

x vx vy

t t t

Log-Domain

Loop-Filter

Log-Domain

Compressor

m-Bit Log-Domain

Quantizer

m-Bit Log-Domain

DAC

vDACc

t

if m = 1 if m > 1

Fig. 1. A log-domain ΔΣ modulator, with an m-bit quantizer and DAC.

design tradeoffs, are provided in Section IV, followed by abrief conclusion summarizing this work.

II. DIGITAL-TO-ANALOG CONVERSION IN LOG-DOMAINΔΣ ADCS

Digital-to-analog conversion in traditional ΔΣ modulatorsrequires the generation of an array of linearly-spaced voltagesteps applied to switched-capacitor, RC, or, gm-C integrators.In contrast, continuous-time ΔΣ modulators employing log-domain architectures require the generation of non-linear step-sizes, as demonstrated in Fig. 1 [2]. In [1], a single-bit DACfor log-domain ΔΣ modulators was realized through the useof a current-switching technique, with the output levels (highand low) scaled appropriately to reflect the compressed natureof the signals. However, the generation of multibit DACs forlog-domain ΔΣ modulators is complicated by the need togenerate multiple non-linearly related step-sizes. A practicalrealization to generate these step-sizes is the placement of acompressor following a uniform-step-size DAC [2], as shownin Fig. 2. Since it is necessary to deliver an input current(iComp,in in Fig. 2) into the log-domain compressor [3], theuse of traditional voltage-output DACs in the feedback pathwould necessitate a voltage-to-current conversion stage priorto the compressor (Fig. 2).

Voltage-to-current conversion at the input of a log-domaincompressor can be easily performed through the use of atransimpedance amplifier [6], with a conversion resistor RV I

determining the conversion factor. Unfortunately, a conversionresistor RV I introduces 4kTR thermal noise at the input of

978-1-4799-4885-7/14/$31.00 ©2014 IEEE

281

DC bias

y n

vDACc t

vDAC

t

vDACc

t

Uniform Multibit

DAC

Log-Domain

Compressorm

vDAC t

V/I

RVI

iComp in t

t

iComp in

IComp

Fig. 2. An implementation of the m-bit log-domain DAC in Fig. 1, with anembedded voltage-to-current conversion stage.

the compressor, which appears unattenuated at the output ofthe ΔΣ modulator. Observing Fig. 1 and Fig. 2, the noisecontribution of resistor RV I at the modulator output y is foundto be

V 2N,y(RV I)(f) = 4kTRV I

(LFLD

1 + LFLD

)2

∼= 4kTRV I 0 ≤ f ≤ fBW (1)

Here LFLD is the transfer function of the log-domain loop-filter, which, as is typical inΔΣ modulator implementations, isdesigned to be large (LFLD 1) within the signal bandwidthfBW .

Low-power realizations increasingly require a reductionof bias currents in the analog components (including thebias current of the compressor in Fig. 2). Accordingly, thisnecessitates the reduction of the amplitude of the compres-sor input (iComp,in), in order to avoid distortion. This canbe achieved by increasing the voltage-to-current conversionresistor RV I . However, observing (1), the noise contributionof the voltage-to-current conversion stage is proportional toRV I , complicating low-power design.

In the next section, a current-ouptut DAC is proposed suchthat the voltage-to-current conversion stage and resistor RV I

in Fig. 2 are eliminated. Additionally, the evaluation of thedesign parameters and the design tradeoffs of the proposedDAC are presented.

III. PROPOSED CURRENT-OUTPUT DAC FOR LOW-NOISELOW-POWER APPLICATIONS

A. Circuit Implementation

Traditionally, various architectures have been employedto generate voltage-output DACs [7]. Particularly, current-steering DACs rely on current-steering unit-elements and re-sistors to generate voltage-output step-sizes [8].

Figure 3 proposes a mutlibit current-output DAC that elim-inates the need for a conversion resistor RV I by employingswitched-current unit-elements commonly employed in currentsteering DACs. Here, instead of applying the unit-elements toa resistor to generate an output voltage [8], the unit-elementsare scaled to generate the required current step-sizes.

In Fig. 3, common-gate transistors MGp and MGn feedthe input signals to the feedback splitter-compressor. Theamplifiers ensure that the voltage bias at the output of the

IUnit2IDAC

M---------------=

d1

IDAC

VDD

dM ndMnd1

ioutn

M Switched-Current Elements

IDAC

VBIAS VBIAS VBIAS VBIAS

ioutp

VCM

VDD

ioutnIBias

IBias

VCM

VDD

ioutpIBias

IBias

IUnit2IDAC

M---------------=

MGp

MGn

Fig. 3. Proposed current-output DAC with differential-output amplitudeIDAC , eliminating voltage-to-current conversion resistor RV I in Fig. 2.

current-steering architecture is not left floating. Employing theamplifiers and common-gate transistors does not result in anadditional power penalty when compared to the implementa-tion in Fig. 2, as a similar amplifier and common-gate stage isrequired when a voltage-to-current conversion stage precedesa compressor [6].

The current-sources IUnit, IDAC , and IBias are imple-mented using wide-swing cascode current-mirrors. The op-amps employ a traditional two-stage miller-compensated ar-chitecture [7], in order to operate at aggressively low supplyvoltages. The current IBias is selected to allow the maximumamplitude of ioutp,n (equivalent to IDAC) to flow through thecommon gate transistors, such that IBias > IDAC .

B. Generation of the DAC Transfer Curve

To determine the required step-sizes, ∆DAC , and the indi-vidual current-steering bias-currents, IUnit, in Fig. 3, both thequantization and digital-to-analog conversion processes withinthe multibit log-domain ΔΣ modulator have to be consideredtogether (Fig. 4(a)). Since quantization and digital-to-analogconversion within a ΔΣ modulator are ideally inverse pro-cesses1, the differential-ended DAC step size, ∆DAC,diff istied to the differential quantizer step-size ∆Quan,diff throughthe desired current-to-voltage conversion factor prior to thequantizer (dictated by resistor RIV in Fig. 4(a), applied acrossa transimpedance amplifier), such that

∆DAC,diff (i) =∆Quan,diff

RIV=

2VREF

RIV M(2)

Here VREF is the single-ended quantizer reference voltage,and RIV is the current-to-voltage conversion resistor followingthe expander [2], as shown in Fig. 4(a) and Fig. 4(b).

Since ∆DAC,diff = 2 ∆DAC , where ∆DAC is the single-ended DAC current step-size, and by observing Fig. 3, where∆DAC = 2 IDAC/M , then

4 IDAC

M=

2VREF

RIV M(3)

and

IDAC =VREF

2RIV(4)

1 The additive white noise model assumes no variation in gain whenquantization noise is introduced [9].

282

Uniform

Current-Output

Multibit DAC

Log-Domain

Compressor

m

I/V

Uniform

Multibit

Quantizer

Log-Domain

Expander

yvQuan in i

DAC out

Loop-Filter

FeedbackLoop-Filter

Output

Decimation Filter

RIV

(a)

VREF

y

vQuan in

VREF

M---------------

(b)

iDAC outp

IDAC

y

2IDAC

M------------------

(c)Fig. 4. Realization of the proposed current-output DAC transfer curve,eliminating the voltage-to-current conversion resistor RV I in Fig. 2. a)Quantizer and DAC path, b) Quantizer transfer curve, c) Proposed DAC single-ended transfer curve with (blue) and without (red) IDAC in Fig. 3.

The M switched-current elements facilitate the sinkingof current from the compressor stage during negative signalswings of ioutp or ioutn. However, the current-output DACis expected to generate both positive and negative signalswings. By applying a current source IDAC at the drain ofthe M switched-current elements in Fig. 3, both positive andnegative signal swings can be generated at the output, whichis set to a maximum of ±IDAC in (4) by employing unit-elements with a weight of 2 IDAC/M . Figure 4(c) illustratesthe shift of the DAC transfer curve through the introductionof the current source IDAC , and the generated step-sizes. Theresulting transfer curve is described by

ioutp = IDAC −(nd1

2IDAC

M+ ...+ ndM

2IDAC

M

)(5)

ioutn = IDAC −(d1

2IDAC

M+ ...+ dM

2IDAC

M

)(6)

Here, signals d1 ... dM and their inverse nd1 ... ndM are theDAC logic inputs, and are either high (1) or low (0).

C. Design Tradeoffs

A primary design objective in the proposed DAC is theminimization of noise. The gate-referred noise (thermal andflicker) of the transistors in Fig. 3 can be expressed as [10]

V 2N,G(f) = 4kT UT n

2 Γ

((√IC + 0.25 + 0.5)

IUnit

)+K ′

FOI0f

(IC

L2IUnit

)(1 +

2nUT

√IC

VKF

)2

(7)

Here 4kT , UT , n, K ′FO, I0, VKF are, respectively, the

thermal-noise energy, thermal-voltage, substrate factor, flicker-noise factor, process technology current, and voltage describ-ing the dependancy of K ′

FO on the level of channel inversion.The transistor design parameters: the bias-current, level-of-inversion, and length, are ID, IC, and L, respectively. The

0.2 0.4 0.6 0.8 126

26.2

26.4

26.6

26.8

27

27.2

27.4

27.6

27.8

28

f/fBW

SF

DR

(dB

)

Fig. 5. SFDR variation as a function of the input signal frequency, over thespan of the ΔΣ modulator bandwidth (fBW = 10 kHz).

inversion coefficient is defined as IC = IUnit/I0(W/L),where W is the transistor width.

Observing (7), it is apparent that as IDAC , and subse-quently IUnit, are lowered to suit the needs of low-powerapplications, the noise of the DAC increases. Accordingly, forlow-power applications, it is necessary to bias the DAC tran-sistors in moderate-to-weak inversion (to decrease IC), andincrease their physical dimensions L and W . The increase inthe transistors’ dimensions also results in improved transistormatching, and hence reduced distortion in the ΔΣ modulatorfeedback path. The reduced current-bias and increased phys-ical dimensions do result in a reduction of the DAC speed.However, due to the inherent high-speed of current-steeringDACs, the lower speed resulting from large transistor sizesdoes not result in significant degradation of the performancein low-power low-bandwidth applications.

IV. CIRCUIT SIMULATION RESULTS

In this section, the proposed DAC performance is evaluatedas multiple design parameters are varied. Specifically, the re-sponse of the DAC speed and noise performance is investigatedas the bias current of the DAC unit-elements, the level ofchannel inversion, and the length of the transistor is varied.

The DAC in Fig. 3 was designed using a 0.13 µm CMOStechnology. The circuit was optimized for very low power sys-tems targeting low-frequency biomedical applications. Specif-ically, the resulting DAC was designed to meet the followingspecifications

• 7-level (3-bit) quantizer and DAC.

• ΔΣ Modulator bandwidth fBW = 10 kHz. samplingfrequency fs = 320 kHz.

• Quantizer VREF = 560 mV, and current-to-voltageconversion factor (RIV ) = 800 kΩ [2].

Figure 5 demonstrates the variation of the DAC SFDR as afunction of the signal frequency. The complete DAC simulationresults are summarized in Table I. The DAC was tested byapplying an ideal 3-bit quantized sine-wave at the input.

Table I corresponds to the best trade-off for our targetedapplication [2] 2. Other applications may require differentspecifications. Thus, to demonstrate the variation in dynamicand noise performance as the design parameters are varied, theoptimized DAC (Table I), was resimulated as the bias-current

2 The quantization process performed prior to the tested DAC, reflected inthe SFDR in Table I, is noise-shaped by the ΔΣ modulator loop.

283

0 1 2 3 4 5 6 7 8 90.2

0

0.2

0.4

0.6

0.8

1

1.2

Time (ns)

i out/I

Unit

IUNIT

432nA=

IUNIT

216nA=

IUNIT

108nA=

IUNIT

54nA=

IUNIT

27nA=

Fig. 6. Normalized step-responsevariation as the switched-elementscurrent bias IUNIT is varied.

0 1 2 3 4 5 6 7 8 920

0

20

40

60

80

100

120

Time (ns)

i out (

nA

)

ICx1

ICx2

ICx0.25

ICx0.5

ICx4

Fig. 7. Step-response variationas the inversion coefficient IC ofthe devices comprising the switched-elements are scaled by an equal fac-tor.

9

0.5

0 1 2 3 4 5 6 7 8 920

0

20

40

60

80

100

120

Time (ns)

i out (

nA

) Lx1 Lx2Lx0.5

Fig. 8. Step-response variation as thelength L of the devices comprisingthe switched-elements are scaled byan equal factor (W/L kept constant).

0 100 200 300 4000

2

4

6

8

10

12

IUNIT

(nA)

Nois

e (

nV

2)

Fig. 9. Integrated noise variation(fBW = 10 kHz) as the switched-elements current bias IUNIT is var-ied.

IUnit, the inversion-coefficients, and the lengths of the multipledevices comprising the M switched-elements was varied by anequal factor.

Figures 6 and 9 explore the variation of the DAC’s settling-time and input-referred noise as IUnit is varied. If IUnit isreduced to target lower power applications, the settling-timeof the DAC and the gate-referred transistor noise increases.In contrast, increasing the transistors’ inversion-coefficientsthrough the increase of the transistors’ widths (Fig. 7 and Fig.10), or a decrease of the transistor lengths (Fig. 8 and Fig. 11)results in improved dynamic performance at the expense ofnoise. Accordingly, once the selection of IUnit is performedfor a particular ΔΣ log-domain ADC architecture (the choiceof which is dependant on the power requirements, quantizerVREF , and RIV ), the inversion coefficient, and length of thevarious devices is altered to arrive at the required noise-speedtradeoff (dictated by the ADC resolution and bandwidth).

V. CONCLUSION

A novel low-power low-noise current-output DAC suitablefor multibit log-domain ΔΣ modulators is presented. Theselection of the DAC design parameters was demonstrated inlight of the ΔΣ modulator architecture requirements, enablingfull signal swings while eliminating the use of a voltage-to-current conversion stage and its associated noise in thefeedback path. Realizing the targeted power-resolution-speedtradeoff was explored in light of the multiple design variables.The presented work and design approach can be extended toother applications requiring current-output DACs.

ACKNOWLEDGMENTS

This work was supported in part by the Fonds Quebecoisde la Recherche sur la Nature et les Technologies (FQRNT),

0 0.5 1 1.5 2 2.5 3 3.5 42.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Inversion Coefficient Variation Factor

Nois

e (

nV

2)

Fig. 10. Integrated noise variation(fBW = 10 kHz) as the inversion co-efficient IC of the devices compris-ing the switched-elements are scaledby an equal factor.

Inversion Coefficient Variation Factor

0.5 1 1.5 2 2.5 3 3.5 42.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3

Length Variation Factor

Nois

e (

nV

2)

Fig. 11. Integrated noise variation(fBW = 10 kHz) as the length L ofthe devices comprising the switched-elements are scaled by an equal factor(W/L kept constant).

TABLE I. DAC CIRCUIT-SIMULATION RESULTS.

Design Parameter Value

Single-ended amplitude IDAC 350 nANumber of quantization levels M 7 (3-bit)DAC unit-element size (2 IDAC/M ) 107 nADifferential step size 214 nAUpdate rate 320 kHzDAC input-referred noise Floor: 2.66e−13 V2/Hz

1/F corner: 1 kHzDelay (250 ns clock rise time) 5.11 nsSFDR (over 10 kHz bandwidth range) > 26.7 dBSupply Voltage 800 mVPower consumptionM switched-current elements 560 nAAmplifiers and current buffers 1.41 µA

by Le Regroupement Strategique en Microsystemes du Quebec(ReSMiQ), and by CMC Microsystems. The authors also wishto express their thanks to Prof. Fabrice Labeau of McGillUniversity for his insight.

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[5] R. L. Carley, R. Schreier, and G. C. Temes, ”Delta-Sigma ADCs withmultibit internal converters,” In Delta-Sigma Converters: Theory, Design,and Simulation, S. R. Norsworthy, R. Schreier, and G. C. Temes, Eds.New York: IEEE Press, 1997. ch. 8.

[6] D. Python and C. Enz, ”A micropower class-AB CMOS log-domain filterfor DECT applications,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp.1067-1075, Jul. 2002.

[7] D. Johns and K. Matrin, Analog Integrated Circuit Design, Toronto: JohnWiley & Sons, 1997.

[8] T. Miki, ”An 80-MHz 8-bit CMOS D/A Converter,” IEEE J. Solid-StateCircuits, vol. 21, no.12, pp. 983-988, Dec. 1986.

[9] R. M. Gray, ”Quantization noise in ΔΣ A/D converters,” In Delta-Sigma Converters: Theory, Design, and Simulation, S. R. Norsworthy,R. Schreier, and G. C. Temes, Eds. New York: IEEE Press, 1997. ch. 2.

[10] D. M. Binkley, Tradeoffs and Optimization in Analog CMOS Design,West Sussex: John Wiley & Sons, 2008.

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