A Wideband Unity-Gain Buffer in 0.13-μm CMOSKamyar Keikhosravy, Pouya Kamalinejad, Shahriar Mirabbasi, and Victor Leung

Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, BC

E-mail:{keikhosr, pkamali, shahriar, vleung}@ece.ubc.ca

Abstract—In this paper, an ultra wideband analog voltage-mode buffer is presented which can drive a load impedance of50 Ω. The presented feedback-based buffer uses a compoundamplifier which is a parallel combination of a high-DC gainoperational amplifier and a operation transconductance amplifierto achieve a high unity gain bandwidth. A proof-of-conceptprototype is designed and fabricated in a 0.13 μm CMOS process.The simulation and measurement results of the proposed bufferare in good agreement. The prototype buffer circuit consumes7.34 mW from a 1.3-V supply, while buffering a 2 GHz sinusoidalinput signal with a 0.4 V peak-to-peak (Vpp) amplitude anddriving an AC-coupled 50-Ω load.

Index Terms—Analog buffer, voltage follower, wideband buffer,CMOS.

I. INTRODUCTION

Wide-bandwidth unity-gain analog buffers are used in a

variety of high-speed and agile applications such as analog-to-

digital converters [1], switch capacitors [2], sample-and-hold

circuits[3] and active probes in measurement instruments. A

simple and commonly used architecture for such buffers is a

source-follower-based buffer[3], [2], [4]. However, achieving

high linearity and spurious-free dynamic range (SFDR) as

well as an accurate gain in such buffers are challenging

[4], although different techniques to address these problems

have been investigated[5]. In cases where the gain accuracy

and flatness are not crucial, source-follower architectures are

used for driving low impedance values such as a 50 Ωload (or a large capacitive load). In these cases, a relatively

large driving transistor is required. This large transistor in

effect limits the input bandwidth of the circuit. One way to

ameliorate this issue is to cascade multiple source-follower

stages and gradually increase the size of the transistors.

Each additional stage adds extra pole to the system which

results in deteriorating the stability and overall bandwidth

of the system. Furthermore, testing high-frequency circuits

typically requires a buffer since many high-speed integrated

circuits are not capable of driving the standard 50-Ω input

impedance of the high-frequency measurement instruments.

Thus, having a monolithic unity-gain buffer (voltage follower)

with relatively flat and accurate gain is desirable. To achieve

such a monolithic analog buffer feedback-based buffers are

typically used, e.g, using an operational amplifier in a unity-

gain feedback structure ensures a relatively accurate gain in the

presence of process, supply voltage, and temperature (PVT)

variations. Fig. 1 shows one possible architecture for such

designs. The bandwidth of this buffer is mainly limited by

the bandwidth of the operational amplifier and the size of the

driving transistor.

+

VDD_Buffer

V_Bias

AIn

Out

MD

Fig. 1. The architecture of a conventional amplifier based analog buffer.

M2 M1

M3M4

M5

Fig. 2. Architecture of compound amplifier used in this design.

In this work, we present an ultra-wideband buffer that

uses a compound amplifier similar to that presented in [6].

The presented buffer can drive 50-Ω loads while achieving a

wide bandwidth. The organization of the paper is as follows:

Section II presents the proposed architecture and provides

analytical insights. Section III presents simulation and mea-

surement results and finally Section IV concludes the paper.

II. PROPOSED ARCHITECTURE

To have an accurate flat gain, the open-loop gain of the

buffer has to be relatively large. The overall open-loop gain

of the buffer can be written as follows:

A(ω) · β(ω) = G(ω)× gm0(ω)× Zout(ω)× 1 (1)

978-1-4799-2452-3/13/$31.00 ©2013 IEEE 9

Vbias_OTA

Out

Out

In

In

OutVbias_OTA

Out

Fig. 3. The overall schematic of analog buffer presented in this work.

where G(ω) is the voltage gain of the amplifier A and gm0(ω)is the small-signal transconductance of the driving transistor

(MD in Fig. 1) at the input frequency of ω, Zout(ω) is output

impedance seen at the output node of the buffer, and β(ω) is

the feedback gain which for the structure shown in Fig. 1 is

equal to 1. The closed-loop voltage gain of the buffer can be

written as:

Vout

Vin(ω) =

A(ω)

1 +A(ω) · β(ω) =A(ω)

1 +A(ω)(2)

From (2), the overall gain of buffer in approximately 1 over the

range of frequencies where A(ω) � 1. Since for the most part

the open-loop gain of the buffer is provided by the amplifier

A, a wide bandwidth amplifier is needed. However, designing

amplifiers with both high voltage gain and high bandwidth is

challenging. One elaborate solution is the compound amplifier

introduced in [6]. The architecture of this amplifier is shown

in Fig. 2.

As shown in the figure to achieve high gain at low frequen-

cies, a high DC gain but low bandwidth amplifier, namely

an operational amplifier (opamp), is used. The operational

amplifier is in parallel with a high bandwidth operational

transconductance amplifier (OTA). The generic magnitude

frequency response of the overall buffer along with its typical

pole−zero locations is shown in Fig. 4. As described in [6],

the combination of the OTA and opamp will introduce a zero,

namely zOTA , which helps to compensate for the adverse

effects of the dominant pole of the opamp. Although the buffer

is generally connected to a small load impedance (e.g., 50 Ω),

to ensure the stability of this architecture a zero (zESR) is also

added (using a series combination of a resistor and a capacitor,

i.e., combination of RESR and Cz in Fig. 3) to the output of

the amplifier to compensate for the output load.

A. Circuit Implementation

The schematic of the presented buffer is shown in Fig. 3.

To achieve a large low-frequency gain a telescopic cascode

architecture is used for the opamp. The buffer has an input

impedance of ~8 GΩ in parallel with 127 fF (averaged from

DC to 1 GHz). For the purpose of driving a low-impedance

p

z

pzESR

p

Fig. 4. Pole-zero location of the proposed buffer

load, a relatively large driving transistor, namely, MD, is used.

The simulated frequency response of the opamp as well as that

of the OTA are shown in Fig. 5. Fig. 6 shows the frequency

response of the overall compound amplifier. The drop in the

low-frequency gain of the compound amplifier (as compared

to the opamp low-frequency gain) is due to the loading effect

of the diode-connected active load of the OTA. This gain drop

also results in pushing the dominant pole of the opamp to

higher frequencies (as can be seen in Figs. 5 and 6).

Since the buffer is expected to operate for input signals with

relatively large voltage swing, and the output of the buffer

follows the input signal, special attention should be paid to

biasing of the circuit. To put this in perspective, consider the

case that the input is a step with a large amplitude. Since

the output follows the input, both input terminals of the OTA

will experience large voltage levels which results in lowering

the drain voltage of transistors M24 and M25 of the OTA.

In this case, transistors M24 and M25 may enter the triode

region of operation. A similar scenario applies when the input

signal is at a low voltage level, where the voltage level of the

drain terminal of M26 and M27 of the OTA will increase

and therefore these pmos transistors may enter into triode

region of operation. To maintain a reasonable voltage level

at the drain of these transistors a common-mode feedback

circuitry shown in Fig. 3 consisting of an analog inverter (i.e.,

transistors M6 to M9) along with biasing circiut is used. This

feedback circuit facilitates the operation of the circuit over a

wider input voltage range by properly adjusting the tail current

10

100

102

104

106

108

1010

0

20

40

60

80

frequency (Hz)

Gai

n (d

B)

100

102

104

106

108

10100

50

100

150

200

frequency (Hz)

Pha

se m

argi

n (d

egre

e)

OTAOpamp

5.9 GHz

10.47 MHz

72°

50°

Fig. 5. Frequency response of the opamp and OTA.

100

102

104

106

108

1010

0

20

40

frequency (Hz)

Gai

n (d

B)

100

102

104

106

108

10100

50

100

150

200

frequency (Hz)

Pha

se m

argi

n (d

egre

e)

Zero Introduced by OTA3.5 GHz

45°

Fig. 6. Frequency response of the compound amplifier.

of the OTA. Fig. 7 shows the simulated output voltage of the

OTA with and without the common-mode feedback circuit.

III. EXPERIMENTAL RESULTS

A proof-of-concept prototype of the proposed buffer is

designed and fabricated in a 0.13-μm CMOS process. Fig. 9

shows the chip micrograph along with the layout view of the

buffer (the inset in the figure). The overall circuit occupies

6059 μm2. The the chip consumes 7.34 mW from a 1.3 V

supply voltage while buffering a 2 GHz sinusoidal input signal

and driving an AC-coupled 50-Ω load.

Fig. 8 shows the measured transient step response of the

buffer a small and a relatively large input steps. The simu-

lation results show that the buffer provides almost the same

performance for both small and large input steps which can

be attributed to the common-mode feedback circuit used in

the OTA. In the transient measurements (Fig. 8) the load

including the input impedance of the measurement equipment

(Tektronix DPO4054 Oscilloscope) is a 20 pF capacitive load

in parallel with a 50Ω resistor. The pulse generator used in

0 0.2 0.4 0.6 0.8 10.2

0.4

0.6

0.8

1

Input common voltage level (V)

Out

put D

C v

olta

ge o

f OT

A (

V)

With common−mode feedbackWithout common−mode feedback

Fig. 7. Simulated output voltage level of the OTA with and without thecommon-mode feedback circuit.

(a)

(b)

Fig. 8. Measured step response of the proposed buffer for (a) 350 mV and(b) 700 mV of input step amplitudes.

Fig. 9. Micrograph of the presented buffer.

11

TABLE IPERFORMANCE SUMMARY AND COMPARISON WITH THE STATE-OF-THE-ART ANALOG BUFFERS.

Year Process (μm) Supply (V) Power (mW) Bandwidth (MHz) Slew rate (V/μs) Load Area (μm2)This work 2013 0.13 1.3 7.34 2000 SR− : −185, SR+:254 50 Ω || 20 pF 6059

[7] 2011 0.35 ±0.75 0.153 1.366 − 10 pF 55000[2]* 2011 0.5 1.5 0.0585 10 − 2 pF −[8] 2010 0.5 3.3 0.198 13.4 SR−:−35, SR+ :29 30 pF 17000[9] 2009 0.35 3.3 4.8 90 200 13 pF 29100

* Simulation results.

Fig. 10. Measured magnitude frequency response of the proposed buffer.

these measurements is HP8110A which can generate pulses

with a rise time of 8 ns.

The frequency response of the buffer is measured in the

closed-loop configuration. For an input signal of 400 mVpp, the

frequency response of the closed-loop buffer is measure with

an Agilent vector network analyzer E5061B and is shown in

Fig. 10. As can be seen from the figure, the 3−dB bandwidth

of the buffer is 2 GHz. The total harmonic distortion (THD)

of the buffer is measured using an Anritsu MS2034A for

a ~100 MHz input signal with a peak-to-peak amplitude of

133 mVpp . The measured result is shown in Fig. 11. The

buffer achieves a THD of ~25.5 dB. For a input signal of

1 MHz with a peak-to-peak amplitude of 270 mVppthe THD

of the buffer is −34 dB.

IV. CONCLUSION

An ultra-wide bandwidth analog buffer that uses a com-

pound amplifier in unity-gain configuration is presented. The

experimental results confirm the wideband performance of

the buffer. The bandwidth of this buffer is measured to be

2.0 GHz while it consumes 7.34 mW from a 1.3-V supply.

This design is fully monolithic and can be used in variety of

applications, in particular, for testing high-frequency circuits.

The performance summary and comparison with the state-of-

the-art designs are presented in Table. I.

V. ACKNOWLEDGMENT

This research is funded in part by the Natural Sciences

and Engineering Research Council of Canada (NSERC), a

Fig. 11. Output spectrum for a 133.33 mVpp ~100 MHz input sinusoid.

Collaborative Health Research Project (CHRP) grant, and the

Institute for Computing, Information and Cognitive Systems

(ICICS) at UBC. CAD tool support and access to technology

is facilitated by CMC Microsystems.

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