A 500µA Low Drop-Out Voltage Regulator in 90-nm CMOS Technology

Akhamal Hicham Université Sidi Mohamed Ben Abdellah Faculté des sciences Dhar El Mehraz Laboratoire d’Electronique Signaux – Systèmes et Informatique(LESSI) Fès, Maroc

hichamfsdm@hotmail.com

Hassan Qjidaa Université Sidi Mohamed Ben Abdellah Faculté des sciences Dhar El Mehraz Laboratoire d’Electronique Signaux – Systèmes et Informatique(LESSI)

Fes, Maroc qjidah@yahoo.fr

Abstract –The paper presents a CMOS low-dropout voltage regulator (LDO).By using wideband and low-current circuit techniques, high performances in terms of transient response, Implemented in 90-nm CMOS technology. The proposed LDO voltage regulator with 50-mA driving capability is presented utilizes paralleled input differential pairs and current amplifiers to provide fast transient response, the LDO itself should provide 0.1µs with transient variation of the voltage less than 153mV. Keywords- low-dropout (LDO); Frequency compensation (cap CMOS); Transient response; Power supply rejection; Squared Output Noise; Layout of schematic.

I. INTRODUCTION This Low Drop-Out (LDO) voltage regulators based on feedback provide an accurate and stable voltage with corresponding load current. All times power management in integrated circuits (ICs) has been gaining more and more attention because it allows for drastic reduction in the consumption of battery-powered portable equipment, such as cellular phones, pagers, camera recorders, laptops, and PDAs. The output capacitor is deceased to only several tens or hundreds of pico farads, degrading the stability and the transient response. And Many designs exploit the zero given by the equivalent series resistance (ESR) of the output capacitor [1], [2], while few of them use different techniques for obtaining an internal and more stable zero as the ESR changes both with temperature and frequency. Then LDOs designed for external load regulation are generally compensated for by means of a microfarad range external capacitor which also helps in attenuating the output voltage overshoots. This structure of LDO voltage regulators is implemented in CMOS technology (Fig. 1) often uses the PMOS FET with common source connection as the pass transistor between the input and output voltages[3]. An amplified error signal is fed back to the gate of the pass transistor through the feedback loop to respond to the load current while keeping the output voltage constant. Stability over the full range of load current

and small output voltage variation during load current transient is the state-of-art of the LDO voltage regulators. In this paper, an error amplifier (EA) based on tow parallels differential input pairs and current amplifiers used to increase input swing, speeding up the transient response; Miller compensation is employed to ensure loop stability. This paper is organized as follows. In section II, stability, description of circuit, transient response and power supply rejection characteristics of the proposed LDO voltage regulator are discussed. In section III, the static-state, dynamic-state and noise Squared characteristics are simulated and corresponding simulation results are summarized with comparisons. The conclusion is derived in section IV.

II. LDO DESIGN CONSIDERATIONS

A. DESCRIPTION OF CIRCUIT

Fig. 1. Basic Low Dropout Regulator Circuit.

The basic schematic of a generic LDO voltage regulators based on a PMOS The structure of LDO implemented in CMOS technology (Fig. 1) .This PMOS FET with common source connection as the pass transistor between the input and output voltages. A part of the output voltage is fed back through R1 and R2 to the input of the and is compared to the voltage reference VREF. Capacitor CL stands for the capacitive load. The current generator IL, represents the load whose current is supplied by the power transistor MP [1], [2] [4], [5]. An EA signal is fed back to the gate of the pass

978-1-4673-4766-2/12 / $ 31.00 © 2012 IEEE

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transistor through the feedback loop to respond to the load current while keeping the output voltage constant.

B. LDO SCHEMATIC AND PARAMETERS I Determine the W/L of each transistor of the circuit, we’re used the drain courant equation if will the all transistors are satured . I use the following relationship [3].

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PARAMETER VALUE VIN 1.2 V

VOUT 0.7V VREF 0.6V

ILOAD 500µA CLOAD 500pF

Fig. 2. Schematic of the proposed LDO voltage regulator The small signal loop gain at low frequency can be given as bellow _ss op amp MPG A A�

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1. Error Amplifier

When the tow parallels differential input pairs and current amplifiers used to increase input swing(error amplifier (EA)) is directly connected to the power transistor, it must be designed to rapidly charge (or discharge) the capacitive contribution seen at the gate of MP that, quite often, may be as large as 10 pF to 40 p. On the contrary, the EA itself should provide very low power dissipation (especially in stand-by mode), and its bias currents must be kept as low as possible. It is apparent that a speed/dissipation trade-off arises, and the main limitation is manifested in terms of slew-rate of the error amplifier. As an example, if the EA can deliver to a 50-pF power-MOS gate no more than 2µA of current, producing a 600-mV step will take 2µs of slewing interval. Considering that during this time the control loop of the LDO is interrupted and that the output voltage is out of control, it is apparent that such a long slewing period may negatively impact on the LDO performance, especially in terms of output voltage overshoots which may become unacceptable for many applications. In order to completely avoid SR limitations, we used a tow parallel differential amplifier used to increase input swing topology for the EA. This allows improvement to the transient response without increasing the DC consumption. 2. Pass-transistor The pass-transistor MP is the common source connection between the input and output voltage is shown in (Fig. 2). A part of the output voltage is fed back through R1 and R2 to the input of the EA and is compared to the voltage reference VREF. The capacitor CL stands for the capacitive load which is offered by the interconnection lines in System on chip designs. The current generator, IL, represents the load whose current is supplied by the power transistor, MP. Quite often a voltage buffer (VB) is inserted before the power transistor to decouple the high capacitive load seen at the gate of MP [1], [2], [4]. The VB allows one to relax the EA specifications and facilitates the compensation. 3. Compensation Network The compensation network, represented as a dashed box, is based on the Miller effect and is placed between the EA output and the LDO output (Fig. 2.). In this applications, the load capacitor is determined by interconnection lines and typically spans from 0.1 to 1 nF, [4], [5], [6],[7], [8], [9]. This capacitive value is too small to set a dominant pole at the output node, and the compensation must

be achieved through the Miller effect. Treating the LDO in schematic as a common two-stage amplifier (although very similar), would lead to a compensation capacitor (capCMOS) of a few area and hundred pico farads which may cause serious problems to the integration.

III. SIMULATED AND EXPERIMENTAL RESULTS The LDO Circuit has been implemented in 90-nm CMOS technology. The pass transistor occupies most of the silicon area. this work is improved by the use of CMOs capacity (CT) so the advantage of reducing the area in the Layout is shown in Fig. 3 in which the effective die area is 14.5 µm 15µm = (217.5 µm2).

Fig. 3. Layout of this work (LDO). Each element (transistor, resistor, capacitor) performs the physical placement, the placement goal is to find the minimum storage area each module supports the physical layout of the circuit according to the netlist. This routing is done manually. For testing the LDO and external current mirror was used, and its output impedance is heavily dependent of the amount of current. The LDO regulator is tested forR1 =3 kΩ ,R2 = 1 kΩ ,VDD = 1.2 V, VREF = 0.6 V and multilayer ceramic output CMOS capacitor 500 pF with several bypass CMOS capacitors in the f F range placed in parallel to reduce high-frequency noise. The dc output voltage of the regulator is 0.75V. The ground current consumed by the LDO regulator is 10 µA.

a. Gain with different variations of VIN. The LDO regulator was simulated and the open-loop gain results. The phase response is shown in (Fig.4.). The phase margin is better than 70 for all cases.

Fig. a

Fig. b

Fig. c Fig. 4 : * Fig. a(VDD1.2_5c217a) * Fig. b(VDD1.2-5c15f) * Fig. c(VDD1.2_5c2f)

Loop gain increases further with different voltage VDD; from 1.2 V to 5 V and increasing the capacity CL.

b. Static-state regulation characteristics Line regulation The simulation result illustrates that the input voltage variation is 197.58mV with the output voltage variation is 199.954mV when the drop-out voltage higher than 600mV.

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Load regulation The output voltage of the proposed LDO voltage regulator with the load current swept from 0 to 500µA is given in Fig.

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The current mass The current mass is the sum of all currents polarization including in the regulator: the current feedback, the current error amplifier and the drive current of the power transistor

[10]. 10GNDI µA� DC response

Fig. 5 , , ( )DS VOUT VREF INV V V f V� if Rout = Cte

Noise response Noise is purely physical phenomenon that occurs with transistors and resistors. Transistors generate shot noise and flicker noise. The resistive element of MOSFETs also generates thermal noise like resistors. Thermal and shot noise is truly random in nature and its power is flat over frequency. It remains flat up to the bandwidth of the amplifier. Flicker noise is the noise due to trapped charges at the gate of the MOSFET. It follows Poisson’s Distribution with 1/f roll-off in power versus frequency hence it is higher at low frequencies. This noise dominates until it becomes smaller than thermal noise [11], [12], [13]. Typically noise in an LDO is specified by datasheets in two fashions. One is “Total (Integrated) output noise – in mVrms”, which is Root-Mean Square (RMS) value of the spectral noise density integrated over a finite frequency range. The second method is to show a “Spectral Noise density curve– in V/

√Hz , which is a plot of Noise density vs Frequency. The noise in LDO can be reduced using two Methods: the 1st method to reduce the noise is by reducing the bandwidth of the LDO and the 2end method is by using a low-pass filter

Fig. 6. Squared Output Noise Transient response

Fig.7. Transient ouput voltage of the LDO regulator as VREF is varied. The stability of the proposed scheme is fully tested by applying a pulsed signal (20 mV) on top of the 1.2V reference voltage as shown in the top trace of( Fig.7). The LDO with the

phase compensation (middle trace) is stable showing that the phase margin is good enough. The test results are also taken without activating the frequency compensation scheme to prove that instability present in the circuit is removed when the compensation scheme is used (Fig.7 bottom trace).

IV. CONCLUSIONS LDO dropout is minimized to guarantee high power supply rejection at optimized efficiency. The design procedure for obtaining the proper stability for wide output current and load capacitor ranges has been illustrated and discussed in detail. The proposed LDO is capable of providing 500 µA with a drop-out voltage of 400 mV when powered at 1.2 V

REFERENCES [1] G.A. Rincon-Mora and P.E. Allen,“Optimized Frequency - Shaping Circuit Topologies for LDO’s,”IEEE Trans. CircuitsSyst. II, vol. 45, no. 6, pp. 703-708, Jun. 1998. [2] G.A. Rincon-Mora and P.E. Allen, “A Low-Voltage, Low Quiescent Current, Low Drop Out Regulator,” IEEE J.Solid-State Circuits, vol. 33, no. 1, Jan. 1998, pp. 36-44. [3] Lv Xiaopeng, Bian Qiang, Yue Suge “An on-chip Low Drop-OutVoltage Regulator with 150mA Driving Capability” Proceedings of the World Congress on Engineering and Computer Science 2011 Vol II WCECS 2011, San Francisco, USA .October 19-21, 2011 [4] W. Aloisi, G. Palumbo, and S. Pennisi, “Design Methodology of Miller Frequency Compensation with CurrentBuffer/Amplifier,”IET Circuits Devices Syst., vol. 2, no. 2, Apr. 2008, pp. 227-233. [5] G.A. Rincon-Mora, “Active Capacitor Multiplier in Miller- Compensated Circuits,” IEEE J. Solid-State Circuits, vol. 35, no. 1, Jan. 2000, pp. 26-32. [6] K.N. Leung and P.K.T. Mok, “A Capacitor-Free CMOS Low- Dropout Regulator with Damping-Factor-Control Frequency Compensation,” IEEE J. Solid-State Circuits, vol. 38, no. 10, , pp. 1691- 1702. Oct.2003 [7] W. Oh and B. Bakkaloglu, “A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier,” IEEE Trans. Circuits Syst. II, vol. 54, no. 10, Oct. 2007, pp. 922-926. [8] W. Oh et al., “A CMOS Low Noise, Chopper Stabilized Low- Dropout Regulator With Current-Mode Feedback Error Amplifier,” IEEE Trans. Circuits Syst. I, vol. 55, no. 10, Nov. 2008, pp. 3006-3015. [9] W. Chen, W.H. Ki, and P.K.T. Mok, “Dual-Loop Feedback for Fast Low Dropout Regulators,” Proc. IEEE PESC, vol. 3, Jun.2001, pp. 1265-1269 [10] M. Al-Shyoukh, H. Lee, and R. Perez, “A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer [11] K. W. Chew, K. S. Yeo, and S. F. Chu, “Impact of technology scaling on the 1/f noise of thin and thick gate oxide deep submicron NMOS transistors”Proc. of IEE, Circuits, Devices and Systems, vol. 151, Issue 5, pp.415 – 421,Oct. 2004 [12] A. Bakker and J.H. Huijsing, "A CMOS chopper opamp with integrated low-pass filter," Proc. ESSCIRC’97, Southampton, UK, pp. 200-203, Sept.1997 [13] C. Enz, E. Vittoz, and F. Krummenacher, "A CMOS chopper amplifier," IEEE J. Solid-State Circuits, vol.SC-23, pp. 750-758, June 1988.

Dominated By Fliker noise Dominated

By Thermal noise