A Low Power Inductive-Coupled Transceiver forInter-Chip Communication

Sanyasi Rao Rupiti, Diptaman Hazarika, Naveen Suda and Roy PailyDept of Electronics and Communication Engineering

Indian Institute of Technology, Guwahati

Guwahati, Assam - 781039, India

Email: {sanyasi, diptaman, n.suda, roypaily}@iitg.ernet.in

Abstract—A novel low power 1-Gbps inductive-coupledtransceiver in 0.18 μm CMOS technology is presented in thispaper. It consists of a transmitter section which consumes 0.74mW power and can operate upto 4 Gbps with pulse width ofless than 250 ps. The transmitter generates current pulse throughinductor both for positive as well as negative transitions of theinput signal. The front-end of the receiver is designed usingcascaded inverter stages for amplification. The further stagesof the receiver consists of differential amplifier, a Schmitt triggerand T-flipflop which gives the final digital output. The transceiverconsumes 1.77 mW power for 1-Gbps data rate.

I. INTRODUCTION

With the downsizing of CMOS technology, the integrated

solutions which utilize 3-D stacking of chips are being ex-

plored to reduce the overall system size. Wire-bonded stacks of

processor, memory and display units can be found in modern

electronic gadgets like mobile phones and laptops. However,

high speed wired communication between chips require a large

number of I/O pads. Instead of wired connection, AC coupled

interconnect can be used for communication in 3-D stacking

scenario. AC coupling can be achieved by capacitive coupling

or inductive coupling elements [1] [2].

The major issues in wired mechanical approaches like

silicon via technologies [3] are increased cost because of

additional process complexity and yield degradation due to

difficulty in screening a known good die (KGD). The wireless

approaches such as wireless super-connect (WSC) by capaci-

tive coupling (WSC-C) [4] or inductive coupling [5] [6] have

many advantages in terms of power, speed, and cost. The

interface, which is a metal plate for capacitive coupling and

metal inductor for inductive coupling, can be implemented in

a standard CMOS process without any additional mechanical

process which allows significant cost reduction of fabrication

and high-density channel arrangement can also be achieved

by exploiting the process scaling. Furthermore, the noncontact

interface removes a highly capacitive electrostatic discharge

(ESD) protection devices resulting in reduction of power, delay

and area.

However, capacitive coupling has its limitation due to its

voltage-driven nature and cannot provide adequate transmit

power to accommodate long distance inter chip communica-

tion at low supply voltages. As a result, the capacitively cou-

pled interface is limited for distances less then few microns,

provided the chips are stacked face to face. But inductive

coupling is a current-driven scheme, hence transmit power

can be increased for longer distance communication even at

low supply voltages in scaled devices [7]. Using inductive

coupling data rate of 1.2 Gbps/pin in 300 μm distance is

reported by Mizoguchi et al. in [5] with power dissipation of

43 mW at the transmitter and 2.5 mW at the receiver. In [7],

Miura and Mizoguchi et al. have designed an inductive coupled

transceiver in 0.35 μm technology with a data rate of 1.25

Gbps and power dissipation of 46 mW at the transmitter end.

In this paper, we propose a novel transceiver which operates

at lower power and potentially can cover longer distance of

communication. The lower power is achieved mainly due to

the less complex transmitter circuit and the corresponding

changes in the receiver. The receiver is designed to have high

amplification so that it can be able to detect very low amplitude

signals.

Operation of the proposed transmitter circuit is presented

in section II and the receiver design is given in section III.

The simulation results are included in section IV and section

V concludes the paper.

II. TRANSMITTER DESIGN

The proposed scheme uses differential encoded data, in

which a single pulse is transmitted whenever the data is high

and no pulse is transmitted when data is low. This scheme

achieves higher data rate compared to [7] in which two pulses

are transmitted for logic 1 and single pulse for logic 0.

A. Transmitter Circuit

The schematic of the inverter based transmitter circuit with

power supply as 1.8 V is shown in Fig. 1. It consists of an

inverter circuit M1-M2 with their drains connected through an

onchip inductor. Sizing of M1 and M2 determines the current

drive of the inductor. M3 and M4 act as capacitive load used

for controlling the damping and pulse shaping. On the whole

they all together form a series RLC resonance circuit. The rise

time and fall time of the input data stream also determines the

current pulse width which is to be transmitted. It generates

current pulse only at the rising or falling edge of the input

data rather than the absolute logic levels. So the input digital

data is differentially encoded prior to the transmitter circuit.

978-1-4244-4570-7/09/$25.00 ©2009 IEEE

Vdd

M1

M2

M3

M4

iLLVin

Fig. 1. Transmitter circuit

B. Encoder Logic

The block diagram of the encoder is shown in Fig. 2.

The main purpose of the encoder is to convert the data

into differential data stream similar to as in DPSK. At the

transmitter end a current pulse is generated at every transition

of the input digital sequence that is during low to high as

well as high to low transitions. The encoder logic includes

one delay element and an XOR gate. The delayed output and

the present input data are given to the XOR gate whose output

is given to the transmitter circuit of Fig. 1. The clock of the

delay element decides the data rate, so it can be communicated

to the receiver as the baud rate. The governing principle of the

encoder is given by

dk = bk ⊕ dk−1 (1)

Data-In

Delay

Clock

Encoded datato transmitter

(Baud rate)

bk

dk

Fig. 2. Encoder logic

III. RECEIVER DESIGN

A. Analog Front-end

The RF front-end circuit of the receiver is shown in Fig.3.

It consists of three cascaded inverter stages, each having a

gain of approximately 3. In the first inverter stage a feedback

transistors M11 and M12 are used such that the DC operating

point of inverter M1, M4 is stabilized. This in turn fixes the DC

operating point of the two cascaded inverter stages of both the

differential inputs. Since the received signal through inductor

is of pulse nature, the output of the inverter amplifier stages do

not have a symmetrical swing around Vdd/2. So differential

amplifiers are used in order to get symmetrical swing around

Vdd/2. Though this differential signal swings from 0 to Vdd,

it is not a pure digital signal. To convert it to digital signal, it

is then passed to the digital subsection of the receiver.

Vin+

Vin-

M1 M2 M3

M4 M5 M6

L

M7 M9

M8 M10

M11’M1’ M2’ M3’

M4’ M5’ M6’

Vdd

Vdd

M11M12

M7’ M9’

M8’ M10’M12’

Vout-

Vout+

Fig. 3. Front-end of receiver circuit

B. Digital subsection of Receiver

The digital subsection of the receiver is shown in Fig.4.

It consists of inverters I1, I3 and a Schmitt trigger which

includes inverters I2, I4, I5 and I6. The inverters I1 and I3

are used for converting the output of analog front end to

digital signal. The sizing of I2, I4, I5 and I6 determines the

switching thresholds of the Schmitt trigger. The output of the

Schmitt trigger is a pulse train which is a replica of the input

data transitions, but not the logic levels of the data. A pulse

is received whenever there is an input data transition. This

data transition is extracted by using T-flipflop with the pulse

train as its clock input. High speed T-flipflop is implemented

using clocked CMOS (C2MOS) logic style, which takes the

differential clock from the output of the Schmitt trigger [8].

The output of the T-flipflop is the replica of the encoded data,

which is to be decoded to get the original data.

Vout+

Vout-frontendfrom RF

Vdd

Schmitt Trigger

T-Flipflop

Digital datato Decoder

M13

M14

M15

M16

M17

M19

M18

M20

M21

M22

I1 I2

I3 I4

I5I6

I7

I8

Fig. 4. Digital block of the receiver circuit

C. Decoder Logic

The actual data that is transmitted is differential data and

hence for recovering the original data a decoder is used at

the receiver after the signal has been processed. The decoder

logic is shown in Fig. 5. The output of the analog front-end

consists of pulse train in which the input data transitions are

embedded. This pulse train is given as clock to a T-flipflop

such that the output toggles each time a pulse is received which

is contrary to the logic used at the transmitter. The data stream

at the output of the flip flop is then fed to the differential data

decoder which consists of a XOR gate and a delay element

as shown in Fig. 5. The governing principle of the differential

decoder is given by

bk = dk ⊕ dk−1 (2)

At the start the encoder, the output is set to either logic 0 or

1 and the same information should be known at the receiver.

Delay

Decoded data

Clock

Digital data from

(baudrate)

T-flipflopbkdk

Fig. 5. Decoder logic

IV. SIMULATION RESULTS

The transceiver circuit designed for standard 0.18 μm

CMOS technology has been simulated for 1 Gbps data rate.

The transient response of the transmitter circuit for a pulse

train is shown in Fig. 6. The peak transmitted current is around

3 mA, and it consumes an average power of 0.74 mW at full

speed of 1 Gbps. It gives a pulse width of around 238 ps and

hence can work accurately upto 4 Gbps.

Fig. 6. Transmitted Pulse

The input signal, inverter stages output and the differential

amplifier output of the receiver analog front-end are shown in

Fig. 7. The inverter chain output swings from 0.8 V to 1.4

V, and 0.4 V to 1.0 V. The differential amplifier output gives

symmetrical rail-to-rail swing from 0.2 V to 1.6 V, but it does

not have sharp transitions. The output of the Schmitt trigger

and T-flipflop are shown in Fig. 8. The output of Schmitt

trigger shows sharp transitions. The output of the T-flipflop is

the actual data which will be sent to the decoder. The receiver

is able to work up to 1 Gbps for 15 mV input data and 1.5

Gbps for 40 mV input signal amplitude. Since the receiver has

higher sensitivity, it can potentially cover longer distance of

communication.

Fig. 7. Output of the receiver front-end

Fig. 8. Final output at the receiver

The overall power consumption of the receiver is 1.03

mW, of which 0.71 mW is consumed by front-end and 0.32

mW by digital section. The designed transceiver has been

simulated for process corner variations (tt,ss,ff,snfp,fnsp) of

UMC 0.18 μm CMOS technology, and the circuit performs

well for 1 Gbps data rate. Standard single layered on-chip

spiral inductor provided by UMC technology foundry has been

used for the transceiver design. The simulated performance of

the proposed transceiver is summarized and compared with

those in literature in Table I.

TABLE IPERFORMANCE COMPARISON

Proposed [1]a [7]a

Technology 0.18 μm 0.18 μm 0.35 μmInductor diameter 238 μm 200 μm 300 μm

TX power 0.74 mW 2.17 mW 43 mWRX power 1.03 mW 2.48 mW 3 mW

Total power 1.77 mW 4.65 mW 46 mWData rate 1 Gbps 1 Gbps 1.25 Gbps

a Measured performance

V. CONCLUSION

In this paper, a low power inductive coupled transceiver

designed for standard 0.18 μm CMOS technology has been

presented. The transmitter circuit is based on a simple inverter,

and works up to 4 Gbps data rate. It consumes a power of 0.74

mW. The receiver has an RF front-end which amplifies the

coupled signal, and the subsequent digital section converts the

signal into corresponding digital data. The receiver consumes

a power of 1.032 mW from a 1.8 V source. The receiver is

able to detect 15 mV input signal at 1 Gbps and 40 mV at 1.5

Gbps data rate.

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