Abstract—This paper presents an ULP (Ultra-Low-Power) diodebased voltage multiplier which is used to convert RF input signalto DC supply voltage. This uses an input signal of 1 V peak topeak and 13.56 MHz frequency and reaches 2 to 3 V at its outputwith 10 diodes. The IC is implemented in a 2 μm multiple-threshold voltage SOI CMOS technology. The IC outperforms, bya factor larger than 2, classical MOS diodes based voltagemultiplier, implemented on the same technology, from the point ofview of efficiency (minimum RF input power for given outputspecifications) and impedance.

Index Terms—Radio frequency identification (RFID), Rectifier, Ultra-Low-Power CMOS, voltage multiplier.

I. INTRODUCTION

HE area of radio-frequency-identification (RFID)applications is rapidly increasing. For some of those

applications, the required input power becomes a really criticalparameter. This is the case of in-vivo monitoring, smartsurfaces applications, and many more. Those require highlyefficient energy management and conversion.

Passive transponders generally operate at low frequencies, from 125 kHz to 50 MHz using coils as antennas andoperating in the magnetic near field of the base station coilantenna. The main disadvantage of operating at lowfrequencies is the limited reading distance (few cm with a 2 cmx 2 cm coil). Another limitation is the bandwidth, limited tofew kilohertz in Europe and other regions. However, thosefrequencies are in use in some important fields and, amongthem particularly, the 13.56 MHz frequency is in use forbiomedical applications [1]. The goal of the development presented here was to design avery efficient voltage multiplier while using a low-coststandard, multiple threshold voltages, CMOS process. Thechallenge is to reduce the cost of RFID input stages by using astandard process while keeping efficiency equal or even betterto the one provided nowadays using specific diodes and moreexpensive processes [2] [3]. Indeed, most of the voltagemultipliers or rectifiers nowadays use specific diodes like

This work was supported in part by the Fonds pour la formation à laRecherche dans l’Industrie et dans l’Agriculture (F.R.I.A.). The authors are with the Microelectronics laboratory (DICE) of the Universitécatholique de Louvain, 1348 Louvain-la-Neuve, Belgium. (e-mail:geoffroy.gosset@uclouvain.be).

Schottky diodes which complicate the process. As we willshow, the use of specially designed ULP CMOS diodesallowed us to considerably improve the characteristics of therectifier compared to rectifiers using MOS diodes whileguarantying cheaper process than the one requiring the use ofspecific diodes.

This paper focuses firstly, on the demonstration of theadvantage provided by using ULP diodes from the point ofview of efficiency and impedance; secondly, on thepresentation of a method allowing the correct and fast designof such voltage multipliers.

Section II presents the typical RFID input stage voltagemultiplier basic block, the differences between MOS and ULPdiodes as well as the differences due to the capacitances used. In Section III, the design of the voltage multiplier, includingthe simulation results, is presented. The experimental resultsare discussed in section IV, and a conclusion is provided inSection V.

II. RFID INPUT STAGE COMPONENTS

The basic block of a common RFID input stage voltagemultiplier is presented in figure 1. As we will see later, thevoltage multiplier is made of a cascade of such voltagedoublers. The voltage doubler is constituted of twocapacitances and two diodes. First, during the AC inputvoltage negative phase, diode D1 is forward biased and D2reverse biased. The current charges the C1 capacitance to aDC voltage ideally equal to the AC input voltage amplitude. Then, during the AC positive phase, D2 is forward biased andD1 reverse biased. The capacitance C2 is then charged, whichleads to an output voltage ideally equal to twice the inputvoltage amplitude. As one can understand, diodes are thecritical components of the designed architecture. We proposehere to use ULP CMOS diodes instead of Schottky or classicalMOS devices.

Fig. 1. Basic block of the voltage multiplier architecture. AC-DC voltagedoubler.

Very High Efficiency 13.56 MHz RFID InputStage Voltage Multipliers Based On Ultra Low

Power MOS DiodesGeoffroy Gosset, student Member, IEEE, Bertrand Rue, student Member, IEEE , Denis Flandre,

senior Member, IEEE

T

2008 IEEE International Conference on RFIDThe Venetian, Las Vegas, Nevada, USAApril 16-17, 2008

1C1.2

978-1-4244-1712-4/08/$25.00 ©2008 IEEE 134

In CMOS technology, classical MOS diodes are realized byconnecting the transistor drain to its gate as shown in figure 2ain forward bias. But when those diodes are reverse biased, thesource now appears connected to the gate. The leakage currentin reverse mode is then equal to the transistor drain current atgate-source voltage Vgs=0, which becomes higher than thejunction leakage current for low threshold voltage (Vth) orhigh temperatures. So, the higher the reverse voltage appliedon the diode, the higher the drain-source voltage, which leadsto an increase of current. Using transistors with a higherthreshold voltage, it is possible to reduce the leakage currentbut this also reduces the forward bias current and hence theefficiency.

Fig. 2. Diodes implemented on CMOS process. (a) standard architecture. (b)ULP architecture.

Ultra-low-Power (ULP) diodes do not feature this problem. The leakage current is strongly reduced while maintaining agood forward current [4]-[7]. Those diodes are obtained bycombining a pair of pMOS and nMOS transistors as shown infigure 2b. When ULP diodes are forward biased, they can beconsidered as 2 classical MOS diodes in series, both forwardbiased. Their forward currents are then similar to those ofstandard MOS diodes. ULP diodes become of higher interestwhen they are reverse biased. In this case, both transistorsources are connected together and both transistors work inweak inversion, with Vgs<0 for the nMOS and Vgs>0 for thepMOS. If reverse voltage is increased, starting at 0V, twophenomena appear one after the other. Firstly, the currentincreases accordingly to the increase of the drain-sourcevoltage. Secondly, the current exponentially decreases as thecut-off gate-source voltages are increased. This induces a verysmall leakage current up to several orders of magnitude lowerthan the off current at Vgs=0 as will be shown in section III.

The capacitance value is a compromise between size andoutput voltage. We decided here to use 5 pF capacitancesbecause further increasing this value leads to a small increaseof the output voltage as well as to a small decrease of thevoltage ripple but leads to a high increase of the area. So, over5 pF, the increase of size seemed to us too penalizing incomparison with the obtained advantages.

A remark must be made here about the technology underuse. As one will notice in section III.D, the capacitances areasare much larger than diodes ones due to a very low capacitancedensity in the present process. It would be about 10 timesbetter using a dedicated analog CMOS technology or anadvanced thin-gate oxide process.

III. DESIGN

A. Specifications

This circuit was designed as a very low power RFID inputstage. In this context, circuit simulations have been realizedsupposing a load current of 1.5 μA at the output of the voltagemultiplier. The aim is to reach a 1.5 to 3 V DC output voltagefrom 1 V peak-to-peak AC input voltage. The efficiency has tobe kept as high as possible and the input impedance has to behigher than 2 k� to ensure a good inductive link voltage gain.

Our simulations use the models available for the 2 μmmultiple-threshold voltage UCL SOI CMOS technology. Suchprocess has demonstrated very high performance for low-power operation of analog, digital and RF circuits in anextended range of temperatures [5]. Furthermore, it inherentlyprovides (i.e. at no additional process costs), 4 different Vthfor nMOS and pMOS transistors as given in Table I.

TABLE I

THRESHOLD VOLTAGES OF UCL FULLY-DEPLETED SOI CMOSTRANSISTORS

nMOSFETs Vth [V] pMOSFETs Vth [V]

NIN -0.3 PIP -0.95NP1N 0.24 PP1P -0.4NP2N 0.46 PP2P -0.08NP12N 0.77 PP12P 0.5

Let us define standard nMOS devices by NP2N (“N” standsfor source and drain heavy doping while P2 stands for thestandard nMOS channel doping). Similarly, in this process [5]standard pMOS devices are accumulation-mode devices andwill be noted PP1P with P1 being the standard pMOS channeldoping. Other devices can then be introduced which are basedon permutation, addition or omission of both initial dopingmasks. The NP1N nMOSFET takes advantage of the standardpMOS device doping level while the PP2P pMOS takesadvantage of the standard nMOS device doping level. Addition of both doping levels P1 and P2 (called P12) allowsdevices such as NP12N and PP12P to be implemented. Omission of any doping level allows implementing deviceswithout any channel doping implantation. Such devices arenoted NIN and PIP with “I” standing for intrinsic.

Fig. 3. Diode currents [A] versus applied voltage [V], W=2 μm and L=2 μm.

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We compare in figure 3 the characteristics of 2 standardMOS and 2 ULP diodes combining different transistors ofTable I. As we previously said, the reverse current is reducedby more than 2 orders of magnitude while keeping a similarforward current.

B. Methodology

As presented above, the typical RFID input stage voltagemultiplier is constituted of a number of cascaded basic blocks, each of them constituting a stage of the voltage multiplier (fig. 4).

Fig. 4. Voltage multiplier architecture with n stages.

The optimal diode types and sizes varying with the source tobackgate voltage, which is different for every stage, simulations were firstly realized on the basic block of thevoltage multiplier, which is a voltage doubler, as shown infigure 1, while modifying its source-backgate voltage (Vsb)from 0 to 3 V, with a 0.5 V step. Indeed, the output voltage ofone stage is the Vsb voltage of the upper one.

For those 7 different Vsb voltages, and each of the 16 ULPdiodes and 8 MOS diodes available from Table I, wedetermined the optimum voltage that can be achieved at theoutput of the block as well as the size of the diode providing it. The intermediate values have been determined byinterpolation. As both optimal diodes types and sizes vary withthe Vsb voltage and conditions the output voltage, it wasimportant to treat both results together. So, we insist here onthe fact that figures 5 and 6 have to be analyzed together andcan’t be understood separately.

We focused on the design of different voltage multipliers. The differences being based on the kind of diodes used, MOSor ULP, and on the capacitance type, poly-metal or MOS. Oneassumption made in this design is that both diodes of eachstage of the voltage multiplier are the same.

In figures 5 and 6, we present the best results obtained foran input voltage of 1 V peak-to-peak. Firstly, we present thehighest rectified voltage obtained. We then present the sizes ofthe corresponding diodes. Finally, the analysis of the presentedresults gives rise to the design of 2 different rectifiers: MOSand ULP. The output voltages of their different stages arefurther given in figures 8a and 8b.

Figure 5 gives the rectified voltage at the output of the basicblock (fig. 1) as a function of the Vsb voltage for the mostinteresting diodes.

Fig. 5. Rectified voltage at the output of the basic block vs. backgate voltagefor best MOS and ULP diodes.

One can notice that the rectified voltage obtained for eachstage can reach about 0.7 V using the best diode. Moreover, the diodes providing the best results, at low backgate voltage, are the PP2P and the NIN-PP2P and, at high backgate voltage, the NIN and the NIN-PP2P.

Once the diodes giving the best results have been found, wecan present the sizes required to get those voltages (fig. 6).

(a)

(b)

Fig. 6. Size of the diodes giving the rectified voltages presented in figure 5 vs. backgate voltage. (a) MOS diodes. (b) ULP diodes. L=2 μm.

One remark has to be made here about ULP diodespresented in figure 6b. The “W over L” value is the globalvalue of both nMOS and pMOS transistors. The size of the

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nMOS can then be extracted by multiplying “W over L” by afactor “y” and the pMOS by multiplying by a factor “(1-y)”. The values of those “y” factors can be found in Table II.

TABLE II

SIZE FACTOR OF THE ULP DIODES PRESENTED IN FIGURE 6

Diode “y”

NIN-PP12P 0.4NIN-PP2P 0.2NIN-PP1P 0.2

Using the results presented previously, it is now possible todetermine the appropriate diode we want to use as well as itssize, whatever the kind of rectifier we want to design: MOS orULP. The results obtained with a 1 V peak-to-peak AC inputvoltage are given in Tables III and IV respectively for eachstage.

To get a 3 V DC output voltage, one can see that it requires5 stages whatever the kind of rectifier. The first column of thetables tells us which stage is considered. One can then find therectified voltage of the stage, i.e. the �V provided by the givenstage (�V). The next column provides the rectified voltage atthe output of the stage taken into account (Vout). The fourthcolumn gives us the diode used and the two last ones give ustheir sizes.

TABLE III

MAIN CHARACTERISTICS OF THE MOS RECTIFIER EXTRACTED FROM

FIGURES 5 AND 6. L=2 μM

Stage�V[V]

Vout[V]

DiodeWnMOS

[μm]WpMOS

[μm]

0-1 0.6655 0.6655 PP2P / 2201-2 0.6360 1.301 PP2P / 1182-3 0.5833 1.8848 PP2P / 703-4 0.5996 2.4844 NIN 50 /4-5 0.6516 3.136 NIN 88 /

TABLE IV

MAIN CHARACTERISTICS OF THE ULP RECTIFIER EXTRACTED FROM

FIGURES 5 AND 6. L=2 μM

Stage�V[V]

Vout[V]

DiodeWnMOS

[μm]WpMOS

[μm]

0-1 0.7313 0.7313 NIN-PP2P 168 2521-2 0.7561 1.4874 NIN-PP2P 148 2212-3 0.7428 2.2299 NIN-PP2P 136 2043-4 0.7016 2.9315 NIN-PP2P 136 2044-5 0.6341 3.565 NIN-PP2P 136 204

The results have been obtained from circuit simulations atschematic level. Next, the efficiency of the different rectifiersas well as the magnitude of their input impedance with a 1 M�load have been extracted and are presented in Table V. Theinput AC power has been calculated by integrating the productof input current and voltage. The output DC power has beencalculated as the square of the output voltage divided by the

output impedance. In both cases, the ULP voltage multiplierprovides the most interesting characteristics.

TABLE V

EFFICIENCY AND IMPEDANCE OF THE TWO DIFFERENT DESIGNEDRECTIFIERS WITH NO LOAD

Rectifier Efficiency [%] Impedance [kOhms]

MOS 20.4 4.74ULP 64.8 8.10

C. Generalization

As shown in Table VI, the design of the rectifiers combinedwith the analysis of diodes allowed us to light up which are thediode characteristics to take into account. So, we are able topropose a design scheme considering those characteristics andusing them to systematically eliminate the inappropriatediodes. Three steps are required: firstly, the most importantcriterion according to us is the ability to drive a sufficientcurrent (1.5 μA). This is the reason why we propose to beginby eliminating the diodes which are not able to drive thecurrent required by the load with a reasonable size (W/L=500). The threshold voltage, which determines the range of voltagein which the diode will drive a useful current and has to be aslow as possible, is the second criterion to be used. Finally, ifmore than one diode remains, the last criterion that we proposeto use is the ratio of the forward current over the reverse one. The best diode will then be the one having the highest ratio.

Table VI gives the parameters used in the proposedgeneralization for the diodes presented in figure 5. Vtd value isthe forward voltage to be applied to the diode to drive a 0.1 μA current. The purpose is to illustrate the method onthose 7 diodes for a 0 V Vsb voltage. As seen previously, thesizes of those diodes are all smaller than the limit (W/L=500). If we then pay attention to the diode threshold voltage (Vtd), one can see that PP1P, NP1N and NIN-PP1P diodes can beeliminated. Finally, taking into account the current ratio, theNIN diode can also be eliminated.

As we saw it in figure 5, the rectifiers providing the higherrectified output voltages are the NIN-PP2P, PP2P and NIN-PP12P which demonstrates the validity of the proposedgeneralization as those diodes are the remaining ones fromTable VI. The same result would have been obtained if onehad started with the 24 possible diodes.

TABLE VI

THRESHOLD VOLTAGES AND CURRENT RATIO OF THE 7 DIODES GIVEN INFIGURE 5

Diodes Vtd [V] Ion/Ioff

PP2P 1.20e-1 144NIN 7.53e-3 8.2PP1P 4.38e-1 6.04e5NP1N 2.32e-1 5.64e4NIN-PP12P 1.56e-2 2.96e1NIN-PP2P 1.21e-3 1.24e4NIN-PP1P 4.38e-1 7.22e5

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D. Layout

Sizes of the designed rectifiers are presented on table VII. Each of them, MOS and ULP, have been realized in twodifferent versions: the first one using only poly-metalcapacitances and the second one using poly-metal capacitancesat RF signal input nodes and MOS capacitances at the outputof each stage. The later feature a much higher density, compared to poly-metal capacitances which allow designingsmaller circuits but have a degraded behavior at highfrequency due to the channel resistance so that they can onlybe connected to the DC nodes.

TABLE VII

LENGTH AND WIDTH OF THE TWO DIFFERENT DESIGNED RECTIFIERSWITHOUT PADS

Rectifier Length [μm] Width [μm]

MOS with poly-metal capacitances 1010 710MOS with MOS capacitances 790 540ULP with poly-metal capacitances 1050 727ULP with MOS capacitances 900 700

We present the layout of two rectifiers in figure 7: thesmallest one and the largest one. As can be observed, most ofthe die area is consumed by the poly-metal capacitors whichare not optimized in the available process. The use of poly-poly capacitors, standard in analog CMOS processes, woulddecrease the die size by about 50 %.

(a)

(b)

Fig. 7. (a) MOS based voltage multiplier layout with MOS capacitances. (b)ULP based voltage multiplier layout with poly-metal capacitances.

E. Simulations Results

We present here the results of post-layout simulationsperformed on the CADENCE net lists extracted from thelayouts of the rectifiers of the previous paragraph. Figure 8agives (from bottom to top) the output rectified voltages ofevery successive stage of the MOS rectifier; figure 8b gives itfor the ULP rectifiers with poly-metal capacitances.

One can notice that, with no load, the output voltage of theMOS rectifier presented in figure 8a is about 2.78 V instead ofthe 3.14 V expected from Table III. This can be explained bythe fact that results provided by figure 8 come from circuitsimulations using CADENCE net lists. This means thatparasitic capacitances and resistances of the different parts ofthe circuit as well as the interconnecting line ones are takeninto account by simulating the real layout given in figure 7. So, it seems obvious to get slightly less promising results at thisdevelopment level than intrinsically expected.

(a)

(b)

Fig. 8. Rectified voltage at the output of each successive stage (from bottomto top) of unloaded rectifiers using CADENCE extracted net list. (a) MOS

rectifier. (b) ULP rectifier.

Figure 8b gives the results for the ULP rectifier. For thesame reasons as enunciated above, the output voltage is now3.02 V instead of the 3.57 V expected from table IV. However, the most important remarks come now from thecomparison between both rectifiers: MOS vs. ULP. Indeed, one can see that the ULP rectifier provides a higher outputvoltage with a smaller ripple than the MOS one, leading to adouble advantage in terms of efficiency.

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IV. EXPERIMENTAL RESULTS

Experimental results were obtained by measuring thecircuits fabricated on basis of the layout presented above. Thefabrication was realized in UCL clean rooms andmeasurements realized with the PA-200 prober from SUSSMicroTec. We have already seen the impact of the layout onthe obtained performances. Indeed, results presented in figure8, giving the output voltages of every stages of the unloadedvoltage multiplier, were less promising than the schematicdesigns let us hope.

Before we present the measurements results, it seemedimportant to realize new simulations taking into account theexperimental output load. Table VIII presents simulationsobtained using CADENCE with extracted ELDO net lists withan output resistance of 1 M� and an output capacitance of 20 pF, corresponding to the estimated cables load.

TABLE VIII

SIMULATED OUTPUT VOLTAGE OF THE TWO DIFFERENT DESIGNED

RECTIFIERS WITH A 1 M� AND 20 PF LOAD

Rectifier Output voltage [V]

MOS 2.15ULP 2.38

Figure 9 presents a comparison between measured diodesand simulated ones: figure 9a for nMOS, figure 9b for pMOSand figure 9c for ULP diodes.

(a)

(b)

(c)

Fig. 9. Diode current [A] versus applied voltage [V]. (a) NIN MOS diodesW=88 μm L=2 μm. (b) PP2P MOS diodes W=118 μm L=2 μm. (c) NIN-

PP2P ULP diodes WnMOS=168 μm, WpMOS=252 μm and L=2 μm

As one can notice, in each case, the simulated diode onwhich are based the results given until now provides a forwardcurrent almost equal to the one given by the measured diodewith a 0 V Vsb voltage. However, in each case, the reversecurrent of the simulated diode is smaller than the one given bythe equivalent measured diode with a Vsb voltage of 0 Vwhich is due to the fabrication or modeling imprecision. So, one can understand that simulation results must be better thanmeasurements realized using a 0 V Vsb voltage.

Figures 10a and 10b present the MOS and ULP rectifiersmeasured output voltages with a 0 V Vsb voltage. Main valuesare summarized in Table IX. Firstly, it can be noticed that themeasured rectifier provide indeed worse results than expected, confirming the negative impact of leakage currents. Finally, one can see that MOS rectifier provides a lower rectifiedoutput voltage and higher ripple than ULP one as predicted bysimulations, confirming the interest of the later.

TABLE IX

MEASURED OUTPUT VOLTAGE OF THE TWO DIFFERENT DESIGNED

RECTIFIERS WITH A 1 M� AND 20 PF LOAD

Rectifier Output voltage [V] Ripple [mV]

MOS 1.4 130ULP 2.0 80

(a)

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(b)

Fig. 10. Measured rectified output voltages. (a) MOS rectifier. (b) ULPrectifier.

(for Vin (resp. Vout): 200 mV (resp. 500 mV) per vertical grid graduation and0 V reference at M1 level (resp. M2), 40 ns per horizontal grid graduation).

V. CONCLUSION

We presented here the improved voltage multipliers resultsobtained while using ULP CMOS diodes instead of classicMOS ones. As we showed, this allows to use a classical low-cost CMOS process while providing an intrinsic increase ofthe efficiency by a factor 3, reaching about 60 % for 5 stages. This corresponds to an efficiency of 90 % by basic block ofvoltage doublers like shown in figure 1. Experimental resultsconfirmed the superiority of the ULP design and pointed outnon-idealities and optimization guidelines.

We also demonstrated a general design scheme in 3 stepsallowing for choosing the most appropriate diodes to be usedin a voltage multiplier or simple rectifier. This scheme is basedon simple diode’s parameters and allows simplifying thedesign. Those parameters are the forward current, the diodethreshold voltage and the forward over reverse current ratio.

As demonstrated in [4]-[7], the ULP design technique canbe generalized to any bulk or SOI CMOS advanced process, aswell as to high temperature applications, in order tosignificantly reduce the negative impact of leakage currents.

ACKNOWLEDGMENT

Geoffroy Gosset would like to thank the Fonds pour laformation à la recherche dans l’industrie et dans l’agriculture(F.R.I.A.) for supporting his research.

REFERENCES

[1] Klaus Finkenzeller. RFID Handbook. Wiley, second edition edition, 2003. Fundamentals and applications in Contactless Smart Cards andIdentification.

[2] Udo Karthaus and Martin Fisher. Fully integrated passive uhf RFIDtransponder IC with 16.7 uw minimum RF input power. IEEE Journal ofsolid states circuits, 38(10) :1602–1608, October 2003.

[3] Fatih Kocer and Michael P.Flynn. A new transponder architecture withon-chip ADC for long range telemetry applications. IEEE Journal ofsolid states circuits, 41(5) :1142–1148, May 2006.

[4] Levacq, D; Liber, C; Flandre, D. Ultra low-power design techniquesusing special SOI MOS diodes. SOI conference, 2003, IEEEinternational. pp:19-20.

[5] Rue, B; Levacq, D; Flandre, D. Low-Voltage Low-Power HighTemperature SOI CMOS Rectifier. International SOI conference, Oct. 2006, IEEE. pp:65-66.

[6] Levacq, D.; Dessard, V.; Flandre, D. Low Leakage SOI CMOS StaticMemory Cell With Ultra-Low Power Diode. IEEE Journal of Solid-State Circuits, Volume 42, Issue 3, March 2007. pp:689-702.

[7] D. Levacq, C. Liber, V. Dessard, D. Flandre. Composite ULP diodefabrication, modeling and applications in multi-Vth FD SOI CMOStechnology. Solid-State Electronics, 48 (2004). pp:1017-1025.

[8] Intellectual property: EP Patent Application n° EP00870313.4. (Prioritydate : 2000-12-21). EP1344253 A1 2003-09-17. US6870229 B2 2003-06-23.

Geoffroy Gosset was born in Brussels, Belgium in1983. He received the Industrial Engineer degreefrom the Ecole Centrale des Arts et Metiers(ECAM), Belgium, in 2005, and the M.S. degree inelectro-mechanical engineering from the Universitécatholique de Louvain (UCL), Louvain-la-Neuve, Belgium, in 2007. In 2007, he joined the electronic circuits and deviceslaboratory (DICE) at the Université Catholique deLouvain (UCL) where he is currently pursuing thePh.D degree. His research interests are in the field ofvery low-power analog circuits, MEMS interface

circuits and RFID design.

Bertrand Rue was born in Obernai, France, in1980. He received the M.S. degree in electro-mechanical engineering from the UniversitéCatholique de Louvain-la-Neuve (UCL, Belgium). In 2003, he joined the electronic circuits anddevices laboratory (DICE) at UCL where he iscurrently pursuing the Ph.D degree. His researchinterests include low-power and/or high temperatureintegrated circuits design, MEMS interface circuitsand wireless sensor systems.

Denis Flandre (S’86–M’91–SM’03) was born inCharleroi, Belgium, in 1964. He received theElectrical Engineer degree, the Ph.D. degree and thePost-doctoral thesis degree from the Universitécatholique de Louvain (UCL), Louvain-la-Neuve, Belgium, in 1986, 1990 and 1999, respectively. Hisdoctoral research was on the modeling of Silicon-on-Insulator (SOI) MOS devices for characterizationand circuit simulation, and his Post-doctoral thesison a systematic and automated synthesis

methodology for MOS analog circuits. Since 2001, he is a full-time Professor at UCL. He is currently involved in theresearch and development of SOI MOS devices, digital and analog circuits aswell as sensors and MEMS, for special applications, more specifically high-speed, low-voltage low-power, microwave, rad-hard and high-temperatureelectronics and microsystems. He has authored or co-authored more than 400technical papers or conference contributions. He holds 6 patents. Prof. Flandre was the recipient of the 1992 Biennial Siemens—FNRS Awardfor an original contribution in the fields of electricity and electronics, of a1997 Wernaers Award for innovation in pedagogical presentation ofadvanced research work, and of the 1999 SCK-CEN Prof. Roger Van GeenPrize for innovation in nuclear science instrumentation. He participated inmany short courses on SOI technology in universities, industrial companiesand conferences, as well as organized and lectured several Eurotrainingcourses on SOI technology, devices and circuits. Prof. Flandre is a co-founderof CISSOID S.A., a start-up company, which spun-off of UCL in 2000, focusing on SOI circuit design services.

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