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A Reconfigurable 0.1 8-rtm CMOS Equalizer IC with an ImprovedTunable Delay-Line for 10-Gb/sec Backplane Serial I/O Links

Franklin Bien', Hyoungsoo Kim', Youngsik Hur', Moonkyun Maeng', Edward Gebara" 2, and Joy Laskar"2

'Georgia Electronic Design Center (GEDC), School of Electrical and Computer Engineering,Georgia Institute of Technology, 85 5th Street NW, Atlanta, GA USA

2Quellan, Inc., 75 5th Street NW, Suite 210, Atlanta, GA USA

Abstract - In this paper, a reconfigurable CMOS equalizeris presented to accommodate vast variety of backplane channelloss characteristics. Backplane channels over different tracelengths and dielectric materials were measured andcharacterized. Feed-Forward Equalizer (FFE) topology withFinite Impulse Response (FIR) architecture was chosen foroptimal equalization for the corresponding backplaneconfigurations. For a reconfigurable FEE IC implementation,wide-range tunable delay-line (15-ps - 74-ps) and variable tap-gain amplifier were fabricated in a 0.18-[tm standard CMOStechnology. The proposed reconfigurable FFE demonstratedsuccessful equalization at 10Gb/sec over various channelconfigurations with 26mW power dissipation from a 1.8-Vsupply.Index Terms - Backplane, CMOS, FFE, FIR Filter, Tunable

Delay-Line, Reconfigurable Equalizer, 10Gb/sec.

I. INTRODUCTION

Strong demands for higher data rate in broadbandcommunications have raised the limit of data transfer rate up tomulti-Gb/sec over the existing legacy backplane serial I/Olinks. However, this high-speed data communication isimpeded by the frequency-dependent loss that is a function oftrace geometry and board material as it is dominated by skineffect and dielectric loss 11]. This channel loss severelydeteriorates the signal integrity with higher data rate and longertrace length that contributes to the Inter-Symbol Interference(ISI). Replacing the legacy backplane with lower loss materialmay ameliorate the ISI effects. However, this requires theentire infrastructure to be upgraded at a tremendous cost. Thus,channel compensation technique, namely channel equalizationhas been regarded as a cost effective solution for the legacybackplane serial I/O links [2,4].

Fig. l(a) and (b) show a typical legacy backplaneconfiguration and the corresponding channel losscharacteristics, respectively. The loss characteristics are quitedifferent depending on the trace length and the board material asshown in Fig. 1(b). Therefore, the amount of channelequalization needs be adjusted to each channel configuration.

In order to compensate this backplane channel loss, anequalization technique using Finite impulse Response (FIR)filter structure was suggested for 10Gb/sec backplaneapplication [2,3]. On-chip passive components were adopted tooffer a bandwidth benefit necessary for 10Gb/sec equalization.However, this passive component-based equalizer cannot

provide adjustable compensation to diverse channelconfigurations.Meanwhile, a pre-emphasis technique was suggested to

realize adjustable equalization [1]. This equalization schemepre-distorts transmit signal waveform to enhance the datatransition. As channel loss increases due to longer tracegeometry, this technique needs to increase the amount of pre-distortion. However, the maximum voltage swing is limitedby the system constraints as well as the voltage headroomissue in the IC implementation. Thus the resulting decreasedaverage signal level thereby leads to reducing the overallsignal-to-noise ratio. Furthermore, this equalization techniquemay increase the amount of near-end cross talk (NEXT), whichis another major signal impairment factor in backplaneapplications.

This paper suggests a receiver-side feed-forward equalizer(FFE) to provide a reconfigurable feature that enables adjustingto diverse backplane channel environments. Backplanechannels with different trace lengths and dielectric materials arecharacterized to investigate the corresponding optimal equalizersystem requirements. For reconfigurable equalizer integratedcircuit (IC) implementation, a tunable delay-line and a variabletap gain multiplier cell are designed. Finally, the feasibility ofa reconfigurable equalization technique is demonstrated withmeasurement results over various channel configurations at 10Gb/sec.

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~40 ------Type "B", Short

-501 2 3 4 5 6 7 8 9 10

Frequency (GHz)(b)

Fig. 1. (a) Backplane channel configuration including 8-in and20-in FR-4 trace length and (b) the corresponding channelfrequency response.

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II. SYSTEM REQUIREMENTS

An equalization technique compensates the frequency-dependent channel loss characteristics. The band-limitedchannel has low-pass frequency response, as shown in Fig.1(b). The larger loss in high frequency range obstructs fast datatransitions of high-speed data. This slow data transition causesthe signal power to smear into the neighboring symbols. Theequalization technique restores the high frequency componentof the original transmitted signal. Fig. 2 shows the conceptualillustration of three backplane channels and the correspondingoptimal equalizer responses. With more loss across thechannel, more frequency boost is required in the equalizer.

In order to make the system adjustable to various channelenvironments, a reconfigurable FFE with FIR structure isintegrated at the receiver side as illustrated in Fig. 3. The FIRfilter consists of tunable tap delay-lines and variable tap gainamplifiers (VTGAs) for tap gain control. Based on themeasured channel response, system simulation is performed toderive optimal equalization requirements, including the optimalnumber of taps, tap delay value, and tap coefficients. In orderto ameliorate the noise enhancement problem such as NEXT,the minimum-mean-squared error algorithm is used forcalculation of the tap coefficients [2].

Fig. 4 illustrates the simulated eye-diagram of a 10Gb/secsignal before and after equalization over 8-in and 20-inbackplane, respectively. Optimal requirement for differentbackplane configurations is summarized in table I,demonstrating the need for a reconfigurable equalizationtechnique to adjust over various backplane signalingenvironments. Deterministic jitter and eye-mask margin wereused as the performance parameter. For comparableequalization performance, configuration with less number oftaps was chosen to minimize the power dissipation.

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corresponding optimal equalizer responses.

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Fig. 3. Functional block diagram of the proposed receiver-sidereconfigurable equalizer system architecture.

(a) (b) (c)Fig. 4. System simulation result (a) before equalization, (b)equalization over 8-in backplane, and (c) 20-in backplane.

TABLE IOPTIMAL EQUALIZER SYSTEM REQUIREMENTSBackplane type # of taps Tap delay"A", short (8-in) 2 50ps (Ts/2)"A", Iong (20-in) 4 |33ps (Ts/3)"B", short (8-in) 3 25ps (Ts/4)"B", long (20-in) 4 33ps (Ts/3)

III. CMOS IC IMPLEMENTATION

The suggested reconfigurable equalizer IC requires threeessential features: tunable tap delay, variable tap gain andswitchable number of taps control. Fig. 3 shows thearchitecture of the proposed reconfigurable FFE IC. Thebackplane channel output signal goes through the tap delayline. Fractional tap spacing of Ts/4 (=25-ps) up to Ts/2 (=50-ps) is determined by system simulation. Then, these delayedsignals are multiplied by the tap weights given by systemsimulation. The resulting amplified signals are combined incurrent domain. Finally, the output voltage signal swing isobtained with the total current applied to the common load thatis illustrated as a summation node in Fig. 3. Since this signalprocessing is performed in the analog domain, the suggestedanalog equalizer consumes less power and provides broadbandwidth compared to the digital equalization approaches.

A. Wide-Range Tunable Delay-Line

From the system simulation, tap delay line of the proposedFFE requires the delay tuning range to include from Ts/4 toTs/2 for a 10-Gb/sec data transfer. An active delay lineapproach is chosen to provide such wide tunable delay feature.The active delay line consists of cascaded differential

amplifiers, as shown in Fig. 5(a). The delay amount isdetermined by the RC response at the dominant pole thatconsists of the parasitic capacitance and the load impedance.These R, C values are highly sensitive to process variation.

In order to ensure that the required delay range is coveredover process variations, the delay-line was designed with amplemargin to cover from 15-ps to 74-ps as illustrated in Fig. 5(b).Such wide range was achieved with three differential amplifiersstages cascaded with multiple signal paths. The delay weightbetween the two signal paths is controlled by a current-steeringmodified-Gilbert cell as illustrated in Fig. 5(a). The twodifferential inputs are connected to Ml, M2 and MI1, M12.

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(a)80

70

60 -E

50

40

30

20 E

100.6 0.8 1.0 1.2 1.4 1.6 1.8

Control Voltage [V](b)

Fig. 5. Wide-range tunable delay-line with improvedbandwidth (a) Schematic and (b) delay performance over controlvoltage.

Meanwhile, this delay-line is inserted in series along the datapath as shown in Fig. 3. Therefore the bandwidth of eachdelay-line must be large enough for a 10Gb/sec data transfer. Inorder to enhance the bandwidth, active inductance load withresistive feedback is used[6] and achieved >7GHz -3dBbandwidthfromeachdelay-line. M3, M4, M7, M8, M13, andM14 along with Rf represent such active inductance loads. Inaddition, M1M4, and M7-M13 were interdigitated in thelayout to minimize parasitic capacitance for higher bandwidthoperation while achieving minimum phase-offset errors.With control voltage Vcd connected to MIS, the delay

amount can be varied. In other words, with maximum Vcdapplied, Vin+ and Vin- follows MI, M2, MS, M6, M9 andM10 resulting in a slow delay path. With minimum Vcdapplied, Vin+ and Vin- signals follow through only M 1I andM12 resulting in a fast delay path. With analog controlvoltage applied, delay value can vary continuously.

Fig. 5(b) shows the building block performance of thetunable delay-line for the designed fractional tap spacing. Widetuning range is achieved from 15 ps (fast delay path) up to 74ps (slow delay path) for control voltage from 0.6 volts to 1.75volts.

B. Variable Tap Gain Amplifier (VTGA)

From the system simulation results, the tap gain amplifierneeds linear bi-polar gain values between -1 to +1. TheGilbert-cell architecture is adopted to meet this requirement asshown in Fig. 6(a).

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-150 -100 -50 0 50 100 150Input [mV]

(b)Fig. 6. Bi-polar variable tap gain amplifier with improvedheadroom (a) Schematic and (b) Linearity and dynamic rangeperformance over control voltage (Vc) from 0.6 to 1.2 volts.

The proposed FFE has four VTGAs connected to thecommon load. Each amplifier flows DC current, resulting infour times the DC current flow through the 50-ohm resistor.This phenomenon induces the voltage headroom issue. In orderto ensure proper voltage headroom for each VTGA,conventional Gilbert-cell is modified with a current steeringbias scheme. Instead of applying control voltage directly to thedifferential pair below the common source, control voltages,Vcont and Vref are applied to MS and M6, respectively toprovide the bias currents proportional to the control input.This modified architecture reduces the total number of stackeddevices resulting in alleviated headroom condition[2].

In addition, both linearity and voltage headroom are enhancedby applying a active resistive degeneration scheme betweendivided common source branches. The ML transistors representsuch active degeneration with M7 and M8 being the dividedcurrent sources. Active degeneration was chosen over resistivedegeneration to further reduce the associated parasiticcapacitance, and hence increasing the bandwidth of the tap gainamplifier blocks. Fig. 6(b) illustrates the linearity and dynamicrange performance of the proposed VTGA.

C. Switchable Number of Taps Control

As mentioned in the previous section, not all channelsrequire 4 tap equalization. On the contrary, for shorter lengthbackplanes, lower number of tap can maximize the bit errorrate performance by limiting the unnecessary boost of thehigher frequency component of a clean eye while reducingpower consumption. For this matter, a switchable number of

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taps feature is added for reconfigurability. Switch is integratedin each delay-line and VTGA to perform the followingfunction:

y(t) = a,*x(t) + al*x(t-T) + a2*x(t-2*T) + a3*x(t-3*T) (1)

y(t)=a,*x(t)+al *x(t-T) + SW] *a2 *x(t-2 *r) + SW2 *a3*x(t-3*T) (2)

(1) represents the time-domain output of the FFE from Fig.3 without the switches. (2) adds SW1I2 variable that can beeither turned on or off. Switches are integrated to the DC biasonly, but not on the data path to maximize the bandwidthwhile reducing the power consumptions. For shorter tracelengths with low loss material backplanes, this feature canreduce the overall power consumption down to 14mW withonly two taps used for the equalization.

IV. MEASUREMENT RESULTS

Measurements were taken with 10Gb/sec PRBS 27-1 dataover two typical backplane materials with 8-inch and 20-inchtrace lengths as shown in Fig. 7. First, the signal after 20-inchbackplane is shown in Fig. 7(a) with completely closed eye-diagram. No data information can be retrieved from suchcondition. Fig. 7(b) shows an eye-diagram after equalizationover 20-inch backplane that successfully opens the eye at10Gb/sec with 4 taps and Ts/3 delay. Fig. 7(c) is the outputwaveforn over 8-inch backplane with 20-inch backplaneequalizer setup applied. As the channel configuration changes,signal integrity is impaired due to over-equalization. Fig. 7(d)shows the reconfigured FFE perfornance to correctly equalizethe 8-inch backplane with 3 taps and Ts/4 delay. These testresults demonstrates the need for a reconfigurable equalizer ICshown in Fig. 8.

(a) Vu)

(c) (d)Fig. 7. Eye-diagram with 10Gb/s PRBS data (a) beforeequalization after 20-in backplane (b) after equalization after 20-inbackplane (c) over-equalized for 8-in backplane (d) reconfiguredequalization for 8-in backplane.

Fig. 8. Micrograph of the proposed reconfigurable FFE IC.

V. CONCLUSION

Various channel configurations with different trace lengthsand dielectric constants were investigated to find optimalequalization requirements. System simulations suggested theneed for reconfigurable equalization for various backplanechannel configurations. A reconfigurable equalizer IC wasimplemented in a 0.18-rim CMOS process with a FIRstructure. Wide-range tunable delay-line that covers fractionaltap spacing from Ts/4 up to Ts/2 was implemented. Thetunable delay-line was design with active inductance load forbandwidth improvement. A variable tap gain multiplier wasdesigned with a modified Gilbert-cell structure for headroomalleviation. The proposed reconfigurable FFE successfullycompensated various channel loss characteristics with differentbackplane materials and trace lengths at 10Gb/sec. Total powerconsumption is 26mW from a 1.8-V power supply.

REFERENCES

[1] J. T. Stonick, G. Wei, J. L. Sonntag, and D. K. Weinlader, "Anadaptive PAM-4 5-Gb/s Backplane Transceiver in 0.25-umCMOS," IEEE J Solid-State Circuits, vol. 38, pp. 436-443,Mar. 2003.

[2] M. Maeng, F. Bien, Y. Hur, S. Chandramouli, H. Kim, Y.Kumar, C. Chun, E. Gebara, and J. Laskar, "A 0.18um CMOSEqualizer with an Improved Multiplier for 4-PAM/20GbpsThroughput Over 20-in FR-4 Backplane Channels," in 2004IEEE MTT-S Int. Microwave Symp. Dig., June 2004.

[3] H. Wu, J. A. Tierno, P. Pepeljugoski, J. Schaub, S. Gowda, J. AKash, and A. Hajimiri, "Integrated Transversal Equalizers inHigh-Speed Fiber-Optic Systems," IEEE J Solid-StateCircuits, vol. 38, no. 38, pp. 2131-2137, Dec. 2003.

[4] D. Mijuskovic, "Backplane Communication: 5Gb/sec andBeyond," presented in the Smart Network Developer Forum2003, Mar. 2003..

[5] J. L. Zerbe, C. W. Werner, V. Stojanovic, F. Chen, J. Wei, G.Tsang, D. Kim, W. F. Stonecypher, A. Ho, T. P. Thrush, R. T.Kollipara, M. A. Horowitz, and K. S. Donnelly " Equalizationand Clock Recovery for a 2.5-10 Gb/s 2-PAM/4-PAMBackplane Transceiver Cell," IEEE J Solid-State Circuits,vol. 38, pp. 2121-2130, Dec. 2003.

[6] C. C. Hsiao, C. W. Kuo, and Y. J. Chan, "Improved quality-factor of 0.1 8-urm CMOS active inductor by a feedbackresistance design," IEEE Microwave Wireless ComponentsLetters, vol. 12, no. 12, pp. 467-469, Dec. 2002.

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