A Novel 43Gb/s 0.2m PHEMT 1:4 Demultiplexer

Jingfeng Ding, Zhigong Wang and En Zhu

Institute of RF- & OE-ICs, Southeast University

210096 Nanjing, China

zgwangWseu.edu.cn

Abstract A novel 43Gb/s 1:4 demultiplexer (DEMIJX) applied

in SONET OC-768 was realized in OMMIC's 0.2gm GaAs

PHEMT. This DEMUX is featured for achieving one stage

demultiplexing by using a long transmission line. This method

not only reduces the components of the DEMIJX but also

lowers its power dissipation. The fabricated DEMIJX operates

error free at 43Gb/s with 231_1 pseudorandom bit sequences

(PRBS) via on-wafer testing. The chip size is 1.9x1.9mm2 and

the power dissipation is 2.0W with a single -5.OV supply.

Key words Demultiplexer, Latch, divider, GaAs, Optical

Receiver

I. INTRODUCTION

To meet the rapidly growing demand of the information

infrastructure, the 2.5Gb/s and 10Gb/s SDH backbone

transmission networks of today must be expanded. While a

multiplexer plays a dominant rule on the transmitter side of a

optical system, a demultiplexer (DEMUJX) is one of the keycomponents on the receiver side. The DEMUX has the

function to recover the original low speed parallel bit streams

from the high speed serial input. Until now, most DEMUJXsoperating at 10Gb/s and above were generally designed in a

tree-type structure [1, 2]. But they all have the same

drawback of high complexity and high power dissipation.The adoption of transmission lines and the differential

technique makes modern circuits design more flexible. Rightnow, transmission lines are usually used in distributed

circuits for impedance match elements [3]. K. Sano designeda Demux with a quarter-rate four-phase clock generated by a

Toggle flip-flop, which reduced the number of elements and

the power consumption [4]. To simplify the DEMUX

architecture further, a novel 1:4 DEMUX was realized in this

paper It was designed in OMMIC 0.2gm GaAs PHIEMT and

for the application in a SONET OC-768 system.

This DEMUX is featured for achieving one stage

demultiplexing by using a long transmission line. This

method reduces not only the number of elements of the

DEMUX but also its power dissipation. The fabricated

DEMUX can operate error free at 43Gb/s with 23-1pseudorandom bit sequences (PRBS) via on-wafer testing.The chip size is 1.9x .9mm2 and the power dissipation is

2.0W with a single -5.OV supply.

II. BLOCK DIAGRAM AND TIMING

The block diagram of the 1:4 DEMUX is shown in Fig.1. This architecture allows to demultiplex one serial data

stream in one stage into four parallel data streams. It consists

of one divide-by-two circuit, one long distance transmission

line, two 1:2 DEMUX controlled by quarter-rate clock and

several buffers. The 1:2 DEMUX consists of one MSDFF

(Master Slave D-type Flip-Flop) and one MSMDFF (MasterSlave Master D-type Flip-Flop). An extra latch is used in

MSMDFF for phase aligning. As shown in Fig. 2, the two

MSDFFs capture the lead bit on the positive-edge of the

quarter-rate clock respectively and the two MSMDFFs

capture the lead bit on the negative-edge of the quarter-rate

clock respectively. Thus the input data is divided into four

different data streams every four bits and aligned with the

*Supported the National High Technology Research and Development Program ofChina (No. 2002AA3 12230 and 2003AA3 1G030)

2831-4244-0126-7/06/$20.00 02006 IEEE.

positive-edge of the quarter-rate clock. Compared the

traditional tree topology, the one-stage 1:4 DEMUX have the

following advantages:

* Less components

* Simpler structure

* Lower power dissipation

The number of latches in this topology is just 12

including the two latches used in the divide-by-two circuit,while a traditional tree type DEMUJX usually has 17 latches.

Buffers in the middle of the tree type used to adjust the time

condition are also eliminated because they are not needed in

this structure. As the first high speed stage in tree type which

consumes much more power is eliminated, this DEMNUX

achieves power saving substantially.

Buffer TA

Data K K

III. CIRCUIT DESIGN

The circuit design becomes challenging when the

operation speed of the circuit is comparable with thefT of the

transistors. In this case, a suitable circuit design is

indispensable. The circuits presented in this paper are

exclusively designed in source coupled FET logic (SCFL)which is important for ultra high speed circuit design to

reduce the voltage swing and the common mode distortions.

As the input data has a wide bandwidth and will be distorted

when passed though a long transmission line. Therefore, the

data distribution is carefully designed. Fig. 3 depicted the

data distribution technique used in this design, which

contains a transadmitance amplifier driving two rear blocks.

And the design of this circuit has been optimized bysimulator ADS2004A.

50Q (W=10pm, G=5pm, L=3290pm)

Figure 1. Block diagram of the One-stage DEMUX

Data UUUData'

Clk/2

Clk/4

Outl

Out2

Out3 E MOit4iunini

Figure 3. Block diagram of data distribution

284

Figure 2. Time chart of the one-stage DEMUX

A. Latch circuit

The schematic of the SCFL type latch is shown in Fig. 4.

It samples the input data during the high level of the clock

and holds the sampled data during the low level of the clock.

At the speed of 40 Gb/s, it is very difficult to precisely

sample and hold the input data. To improve the performance,all transistors in the data path have the same size and are 3/4

of clock transistors. The small width of devices in the data

path reduces the parasitic capacitance. The increased gate

width of the clock transistors accelerates the slew rate of the

tail current when the input clock signal switches. A pair of

inductors is used as shunt peaking inductors to enhance its

bandwidth. The two diodes (D1, D2) are used to shift the DC

level and let the latches function with proper gain.

B. Output Drive Circuit

Fig. 5 shows the schematic of the buffer used to create

sufficient output voltage swing. It consists of a preamplifierand an output driver. One pair of source followers is added

in front of the first amplifier for the interest of reducing the

load of the MSTFF and enhancing its driving ability. The

preamplifier is featured for a differential configuration with

an ac-coupled push-pull active source-follower which will

broaden the circuit bandwidth without consuming additional

power. The time constant:

r = R5xCI=R6xC2

Figure 4. Schematic ofthe latch.

iLVSS. 4 Preamplifler - Output driver -_

Figure 5. Schematic ofthe output drive circuit.

(1)

should be smaller than half the period of the maximum

bit-rate input signal. The resistance value of R5 and R6determines the dynamic peak load current. The shunt

peaking inductors (L1 and L2) extends its bandwidth further.

The output driver is designed to offer enough voltage swingover 504- off-chip load. As the off-chip parasiticcapacitance would greatly limit the bandwidth of this

amplifier, inductors (L3 and L4) were used as shunt peakinginductors. The comparison of simulation results with and

without peaking technique is shown in Fig. 6. A pair of

on-chip output termination 100Q2 resistors (R3 and R4) is

provided to reduce the output return loss compared to the

open drain configuration.

.

35Frequency(GHz)

Figure 6. Comparison of simulation results with and without peaking

technique.

285

IV. LAYOUT & FABRICATION

Symmetry layout of the differential clock and data

paths is diligently respected to suppress the common mode

noise and stabilize the high frequency ground. Minimum

interconnections are preferred. As far as practically possible,

air-bridges are added between high frequency signalinterconnections to reduce parasitic capacitor and ohmic

resistances. Octagonal pads are applied at data and clock

terminals to reduce the parasitic capacitance.

The DEMUX was fabricated in a 0.2pm standard

PHIEMT technology with GaAs Dielectric (£r 12.9) through

MPW of our institute. The micro-photo of the fabricated

chip is shown in Fig. 7 whose size is l.9xl.9 mm2.

V. MEASUREMENT & RESULT

The performance of the fabricated DEMUX was

measured on-wafer on a Caccade Microtech's probe station.

The differential 231-1 PRBS input data and sinusoidal clock

were generated by Agilent 81250. The outputs were

measured by a wide-bandwidth oscilloscope, Agilent86100A.

Figure 8. One ofthe output eye-diagrams at 43Gb/s input.

4 ' ~ VI*~~Vtd~fl T t Splu

Fig. 8 shows one of the measured eye-diagram with a

43Gb/s 23-1 PRBS input and a 21.5GHz sinusoidal clocksignal. The measured rms jitter is 4.2ps. According to 4

parallel eye-diagrams in Fig. 9, their skew is less than 20ps

(5%) and it confirms that the time adjusting method adoptedin this chip is practicable. The power consumption is 2.0W

at double supply voltage of-5V.

Figure 7. The microphotograph ofthe chip

Figure 9. All the outputs at 40Gb/s input

VI. CONCLUSIONS

A novel 43Gb/s 1:4 DEMUX in 0.2gm PIHEMT hasbeen designed, fabricated and measured. By using a longdistance transmission line, the topology is simplified and its

power dissipation is reduced. The DEMUX works from

38Gb/s to 43Gb/s with 2.0W power dissipation.

REFERENCES

[1] M. Lang, Z. Wang and Z. Lao, et al. "20-40 Gb/s 0.2-ptm GaAsHEMT chip set for optical data receiver", IEEE Journal of Solid-StateCircuits., Vol. 32, pp.1384-1399, Sept. 1997.

[2] M. Meghelli, A. V. Rylyakov, and L. Shan "50Gb/s SiGe BiCMOS4:1 multiplexer and 1:4 demultiplexer for serial communicationsystems", pp. 260-261, ISSCC 2002.

[3] G. Drew and T. K. Kevin, " Design of a differential distributedamplifier an oscillator using close-packed interleaved transmissionline", Vol. 40, pp. 1997-2007, Oct. 2005

[4] K. Sano, K. Murata, H. Kitabayashi, et al. 50-Gbps InP HEMT 4:1Multiplexer/1:4 Demultiplexer chip set with a multiphase clockarchitecture. IEEE Trans. on Microwave Theory and Technique. Vol.51, pp. 2548-2554, Dec. 2003.

[5] Jingfeng Ding, Zhigong Wang, "Time division 1:4 Demultiplexer",China Pantent Pending.

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