A 0.125.5-GHz Differential Cascaded-Distributed Amplifier in 0.18-m CMOS Technology

Chihun Lee

Dept. of Electronics Engineering National Taiwan University

Taipei, Taiwan 10617, R. O. C. d1943013@ee.ntu.edu.tw

Lan-Chou Cho Dept. of Electronics Engineering

National Taiwan University Taipei, Taiwan 10617, R. O. C.

d2943009@ee.ntu.edu.tw

Shen-Iuan Liu Dept. of Electronics Engineering

National Taiwan University Taipei, Taiwan 10617, R. O. C.

lsi@cc.ee.ntu.edu.tw

Abstract—A differential distributed amplifier employs a loss-compensation L section to increase the bandwidth of the interstage by a factor of 3.5. To demonstrate the proposed circuit, a cascaded distributed amplifier with five stages is presented. It has been fabricated in a 0.18um CMOS process and achieves a gain of better than 15 dB and a pass bandwidth of 100 MHz to 25.5 GHz while consuming 171 mW from a 1.9-V supply.

I. Introduction Broadband data and RF transceivers typically incorporate a wideband amplifier to increase the signal level and suppress the noises. The recent wideband amplifiers realized in CMOS technology have been reported [1]-[5] to operate at tens of gigabits per second, as shown in Table I. While the distributed amplification technique was introduced by [6], the distributed amplifier (DA) has been recognized as one of the most popular broadband configurations for the past decades. This paper describes a differential cascaded distributed amplifier (CDA), yielding a gain of 15dB and a bandwidth around 25.5 GHz. This paper is organized as follows. Section II presents the design of this CDA and discusses the loss-compensation L section. Section III presents the circuit implementation, and Section IV summarizes the experimental results.

II. Cascaded distributed amplifier The distributed amplification technique [6] is to

(a)

(b)

Fig. 1 (a) A basic distributed amplifier with lumped inductors. (b) A cascaded one. absorb the transistor’s gate/drain capacitances into artificial transmission lines, as shown in Fig. 1(a). In the frequency range below 20 GHz, we incorporate a chain of

Table I. Performance comparisons of CMOS wideband amplifiers with lumped inductors.

Ref. Technology Gain (dB)

BW (GHz)

GainBW (GHz)

VDD

(V) Power (mW) Design Features

[1] 0.6 µm CMOS 6.5 4 8.5 3 83.4 Single-ended DA

[2] 0.6 µm CMOS 5.5 7.5 14.1 3 216 Differential DA

[3] 0.18 µm CMOS 7.3 22 51 1.3 52 Single-ended DA,

Cascode

[4] 0.18 µm CMOS 9 25 70.5 3.5 60 Single-ended DA, Cascode and cascaded

[5] 0.18 µm CMOS 15 22 124 2.2 190 Differential, Triple-resonance

This work

0.18 µm CMOS 15 25.5 143 1.9 171 Differential DA, Cascaded

5-1

1290-7803-9162-4/05/$20.00 ©2005 IEEE

inductors and parasitic capacitances to approximate the transmission line. It can reduce the long-line resistive loss. While the Miller multiplication capacitances from each transistor’s gate-drain overlap capacitances accumulate through the chain. The increase of the input effective capacitance per unit length leads to the bandwidth constraint.

The Miller multiplication capacitances can be alleviated by using the cascaded architectures, such as the cascaded distributed amplifier [(Fig. 1(b)], to decompose the gate chain into the smaller equal length per stage to uniformly multiply the gain. The so-called triple-resonance amplifier (TRA) [5] has been presented to widen the bandwidth of the cascaded stage as shown in Fig. 2(a). It interposes the combination of a π -network composed of CD, CG, and L1 and an inductive load composed of RT and L2. Then, the small-signal model is simplified as shown in Fig. 2(b). It exhibits a gain peak of 1.8 dB and gives the bandwidth improvement by a factor of 3.5 under the assumption that both CD and CG are equal. In fact, since CG is often larger than CD due to the Miller effect, this technique [5] suffers more capacitive loss from the low-pass L section beyond the resonance of CG and L1. And it will decrease the bandwidth. Assumed that GD C.C 50= , the TRA improves the bandwidth by a factor of only 2.3 from the simulations of Fig. 2(b). In this paper, a cascaded distributed amplifier (CDA) is presented as shown in Fig. 2(c) and it offers two advantages: 1) since the cascaded topology separates transmission lines into each stage, the cumulative capacitance along a transmission line can be lowered to obtain a uniform gain; and 2) since one moves the inductive load composed of RT and L2 from the drain to the gate, the larger CG may meet the loss-compensation L section as depicted in Fig. 2(d). Thus, it provides a desired peaking in the cascaded path. To increase the bandwidth, the inductor load in Fig. 2(d) must serve as an artificial transmission line and require [7] [8]

21 2LL = (1) It becomes a T-network composed of L1, L2, and CG instead of a π -network composed of CD, CG, and L1. Moreover, to minimize the in-band ripple, the resistive load can be

( ) 21

/CCL

RGD

T+

= (2)

to approach the impedance

GL C

LZ 1= (3)

at the frequency

G

LCL1

1=ω (4)

where ZL and Lω denote the characteristic impedance and the resonant frequency of the T-network [9], respectively. Simultaneously, the T-network and the inductive load form a loss-compensation L section. At Lω , it provides an amount of impedance, not a short, to amplify the greater

(a)

(b)

Out

M1V i n

M2

CD CG

RT

L1

L2

(c)

(d)

Fig. 2 (a) Triple-resonance amplifier (TRA), (b) simplification of (a), (c) cascaded distributed amplifier (CDA), (d) simplification of (c).

fraction current of Iin through CG, and contributes a zero

2LRT

Z =ω (5)

to improve the bandwidth of the L section. To demonstrate the effects, the frequency behaviors of Fig. 2(b) and Fig. 2(d) for these two amplifiers are simulated. As illustrated in Fig. 3, it reveals that 1) the TRA explores band degradation because the low-pass L section that, around Lω , acts as a short and absorbs the greater current without the peaking causes the capacitive loss at voltage VX; and 2) because the resonance of loss-compensation L section still provides relative impedance to maintain VX, the CDA obtains a gain rollup to voltage VOUT from Lω to

πω ,

where πω denotes the resonant frequency of the

π -network.

Lω πω Zω

TR

in

out

IV

TR

in

x

IV CDA |V

OUT / I

in|

CDA |VX / I

in|

TRA |VOUT

/ Iin|

TRA |VX / I

in|

Fig. 3 Simulated frequency response in the presence of

GD CC < .

130

0ωω0 1 2 3 4

-6

-3

0

3

6

9

(TRA)C

D=0.5C

G

CD=0.67C

GC

D=0.8C

G

CD=C

G

(CDA)C

D=0.5C

G

CD=0.67C

GC

D=0.8C

G

CD=C

G

N

orm

aliz

ed |V

out /

I in| (

dB)

(a)

0ωω0 1 2 3 4

-6

-3

0

(TRA)C

D=0.5C

G

CD=0.67C

G

CD=0.8C

G

CD=CG

(CDA)C

D=0.5C

G

CD=0.67C

G

CD=0.8C

G

CD=CG

Nor

mal

ized

|Vou

t / I in

| (dB

)

(b)

Fig. 4 Simulated frequency responses of amplifiers with (a) ideal inductors and (b) realistic inductors.

Fig. 4(a) plots the transfer functions of two amplifiers: a CDA and a TRA. The graphical comparison is clear represented that as the ratio of CG over CD arises, the -3 dB bandwidth increases in the CDA, but decreases in the TRA. However, the CDA peaking is too large to introduce the ISI in random data. Fortunately, that the on-chip inductors with the finite Q of 8 ease the peaking issue to keep the advantage of large bandwidth is confirmed from Fig. 4(b).

Then, compared with the TRA, the CDA even with Miller multiplication loss and the finite Q of the inductors still leads to a larger bandwidth by a factor of 3.5.

III. Circuit Implementation

Fig. 5 illustrates the differential five-stage CDA circuit. Since the inductor load in this circuit has the Miller-multiplication compensation to enhance the bandwidth, the differential transistor pairs can be widen, yielding a simulated gain of 16 dB and obtaining a overall bandwidth of 26 GHz. The on-chip inductors are simulated with a full-wave EM simulator, achieving a Q of 8 around 25 GHz. Fig. 6 plots the simulated gain of four amplifiers with the realistic inductors: a single-ended DA, a differential TRA, and both a single-ended CDA and this differential circuit. From the observation, we summarize

Ω Ω

ΩΩ

Fig. 5 Differential cascaded-distributed amplifier.

0 5 10 15 20 25 30 35-20

-10

0

10

20

30

Gai

n (d

B))

Frequency (GHz)

Fig. 6 Simulated gain responses for 5-stage CDA and TRA amplifiers.

the respective feature: 1) although the DA has the maximum bandwidth, yet the cumulative capacitance introduces the in-band ripple; 2) if the TRA increases the slight gain, then the Miller effect may expose the extreme bandwidth degradation; and 3) because the differential CDA doubles the output voltage, thus it provides a more 6 dB gain than the single-ended counterpart without the penalty of the bandwidth. Moreover, the CDA compensates the transistors capacitance and the substrate loss in CMOS technologies.

IV. Experimental results The CDA circuit has been fabricated in a 0.18-m CMOS technology. Fig. 7 shows a photo of the die, which measures 2170 .. × mm2. The circuit is tested on a probe station. The differential mixed-mode S-parameters are measured by an Agilent E8364B 10 MHz-50 GHz network

Fig. 7 Die photo.

131

0 10G 20G 30G 40G

-20

-10

0

10

20

Frequency (Hz)

Mag

nitu

de (d

B)

-1200

-900

-600

-300

0

300

SD

D21 P

hase (DE

G)

Fig. 8 Measured frequency response of the differential CDA.

analyzer, using the 4 port-end 2-port calibrations. Fig. 8 exhibits the measured differential frequency response, providing a pass bandwidth of 25.5 GHz, a differential gain SDD21 of larger than 15 dB with the input/output return loss of less than -8 dB. It is noted that the slight gain rolloff under 9 GHz results from the Q degradation of only 6 at 25 GHz by the re-simulation and the prediction. Then, 100 mVpp 25 Gb/s and 28 Gb/s data are generated by an Anritsu MP1758A 40 Gb/s random data generator.

(a)

(b)

Fig. 9 Measured single-ended output eye with input voltage of 100 mVpp and input data of (a) 25 Gb/s of PRBS 231-1 and (b) 28 Gb/s of PRBS 231-1. [Vertical scale: 50 mV/div.; horizontal scale: 6.8 ps/div. in (a) and 5.7 ps/div. in (b)].

Fig. 9 shows the measured eye diagrams, while the circuit drives 171 mW from a 1.9-V supply.

V. Conclusions

This work demonstrates that the differential CDA

achieves the highest gain-bandwidth product in the 0.18-m CMOS technology. The CDA topology incorporates a loss-compensation L section at the inter stages to achieve the bandwidth of 25.5 GHz. The proposed circuit is also compared with the TRA.

Acknowledgment

The authors would like to thank National Chip Implementation Center for chip implementation. Special thanks to Dr. Huang of Radio Frequency Technology Center (RFTC) and Prof. Jri Lee, NTUEE, Taiwan for measurement supporting. This work was supported in part by MediaTek Inc.

References [1] B. M. Ballweber, R. Gupta, and D. J. Allstot, “A fully

integrated 0.5–5.5-GHz CMOS distributed amplifier,” IEEE J. Solid State Circuits, vol. 35, pp. 231-239, Feb. 2000.

[2] H. Ahn and D. J. Allstot, “A 0.5–8.5-GHz fully differential CMOS distributed amplifier,” IEEE J. Solid State Circuits, vol. 37, pp. 985-993, Aug. 2002.

[3] R.-C. Liu, C.-S. Lin, K.-L. Deng, and H. Wang, “Design and analysis of DC-to-14-GHz and 22-GHz CMOS cascode distributed amplifier,” IEEE J. Solid State Circuits, vol. 39, pp. 1370-1374, Aug. 2004.

[4] M.-D. Tsai, K.-L. Deng, H. Wang, C.-H. Chen, C.-S. Chang, and Chern, J. G.., “A miniature 25-GHz 9-dB CMOS cascaded single-stage distributed amplifier,” IEEE Microwave and Wireless Components Letters, vol. 14, pp. 554-556, Dec. 2004.

[5] S. Galal and B. Razavi, “40-Gb/s amplifier and ESD protection circuit in 0.18-µm CMOS technology,” in IEEE J. Solid-State Circuits, pp. 2389-2396, Dec. 2004.

[6] E. L. Ginzton, W. R. Hewlett, J. H. Jasberg, and J. D. Noe, “Distributed amplification,” in Proc. Inst. Radio Eng., pp. 956-969, Aug. 1948.

[7] B. Y. Banyamin and M. Berwick, “Analysis of the performance of four-cascaded single-stage distributed amplifiers,” IEEE Trans. Microwave Theory Tech., vol. 48, pp. 2657-2663, Dec. 2000.

[8] K.-L. Deng, T.-W. Huang, and H. Wang, “Design and analysis of novel high-gain and broad-band GaAs pHEMT MMIC distributed amplifiers with traveling-wave gain stages,” IEEE Microwave Theory and Techniques, Transactions, vol. 51, pp. 2188-296, Nov. 2003.

[9] T. T. Y. Wong, Fundamentals of Distributed Amplification Norwood, MA: Artech House, Oct. 1993.

132