Approaches and Options for Modeling sub-0.lym CMOS Devices

Mansun Chan, Xuemei Xi, Jin He and Chenming Hu

Department of Electrical Engineering and Computer Science, University of Califomia at Berkeley, 502 Cory Hall, Berkeley, CA 94720-1770

Tel: 1-(510) 642-3393; E-mail: mchan@eecs.Berkeley.edu

ABSTRACT

This paper attempts to provide a general guideline to develop a practical model for MOSFETs in the sub 0,lpm generations. It statts by giving an overview of the different modeling approaches and options including charge based approach, surface potential based approach, and conductance based approach. Their relative advantages and weaknesses will be discussed. The evolution of the BSlM models from its first generation to the most recent release will be used as an example for the development of a practical device model. It will be followed by a discussion on how the accelerated technology development may impact the traditional modeling approaches. A new paradigm to incorporate modem software engineering methodology to shorten model development cycle will be presented.

Keywords: CMOS Device, Circuit Simulation, Device model, SPICE, BSIM

1 INTRODUCTION

Device models play a very important role in the . advancement of CMOS technology and they appeared

everywhere from fabrication process development to IC design and manufacturing as shown in Fig. 1. However, the requirement of a good device model varies among different user groups as illustrated in Table I . For a long time, model development has been done by many individual teams in companies and institutions without coordination. In order to reduce the confusion that the modeling community brings to the users, the EIA Compact Model Council (CMC) [ I ] was formed to standardize the model to be used for circuit simulation. BSIM3 version 3 [2] developed at UC Berkeley is the first model to be standardized by the CMC. Since then, the requirements of a industrial model become more well defined and a number of alternative approaches were proposed to model more advance features in the high-end CMOS technologies.

2 VARIOUS MODELING APPROACHES

While there are many approaches to model MOSFETs, they can he categorized to charge based model, surface potential based model and conductance based model.

Charged based model Charge based model is the descendent of the Meyer

model [3] first developed to model MOSFET behavior. The model starts with formulating the inversion charge by QjnS= C,(V,-VT). Then by integrating the current equation

ID=WQj,,,v, the strong inversion region I-V equation is obtained as shown in Fig. 2. While this method is simple, it handles the triode operation region, velocity saturation region and subthreshold region separately. As a result, smoothing functions have to be used to connect various I-V curves in different operation regions. The BSlM family adopted this approach due to the flexibility it provides.

Surface potential based model Surface potential based model was first developed by

Pao and Sah [4] in which the surface potentials at the source and drain are first evaluated (as shown in Fig. 3) and then use it to derive the various charges. While this approach is more accurate in the device physics, it is very complicated as no explicit expression of surface potential as a function of extemal voltages exists. As a result, iterations are often required to solve the surface potentials. This approach is also not flexible to add structural dependent non-ideal effects. Some advanced surface potential based models are MOS 11 [ 5 ] from Philips and HiSlM [ 6 ] .

Conductance based model While the surface potential based models are physical, it

is not an ideal choice for analog designers who care the conductances more than the actually cuments. The Meyer based model, on the other band, may not be able to give the accuracy required in the near threshold region. The conductance based model is then developed to serve the need of analog designer by performing an empirical fitting to g A D instead of the current itself as shown in Fig. 4. While empirically fitted, this kind of model gives a very nice behavior in both current and conductances and thus attracted the attentions of some circuit designers. An example of conductance-based mode is the EKV model [7].

3 CURRENT MODELING TREND

The requirements of a good model are very difficult to define, as different interest groups have different foci. The role of compact model represents a hadeoff between numerical simulator and table look-up based simulator in term of accuracy and speed as shown in Fig. 5. In practice, more issues have to be included in the form of model tradeoff polygon as shown in Fig. 6 . Most of the entities in the model tradeoff polygon often contradict each others. The current trend, as partially defined by the CMC, is geared towards the direction of accuracy while simplicity and number of parameters seem to receive less ahention. The emphasis in model application is also targeted towards accurate representation of device characteristics from wafer foundries rather than simplicity for circuit design.

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4 EVOLUTION OF THE BSlM MODEL

The development a practical model requires a detail planning and careful execution. The evolution of the BSlM family can be used as a case study in the development of a practical model. BSlMl was the first family member developed one and a half decade ago [8]. It distinguished itself as an “engineering” model rather than a “purely physical model”. The differences are very subtle, and have a lot to do with the constraints imposed by the circuit simulator architecture such as SPICE. As a result, a purely physical model may not be implementable. BSlMl starts out a simple DC model to address the need of predicting the transfer characteristics of short channel MOSFETs. BSIMZ was built on the BSlMl core which further included an accurate conductance and capacitance model for transient and AC simulations. Both BSlMl and BSIM2 were semi-empirical based. Entering the 3‘d generation, BSIM3 incorporate a more complete physical-based core and implemented in a very efficient way. While fitting parameters are introduced to improve accuracy, they only act as a secondaly conection to overcome the inaccuracy in describing some structural features such as dopant profiles.

In the BSIM development, emphasis has been placed on mainly 3 aspects: physical formulation, computational efficiency and ability to accommodate a large variety of technologies. Physical formulation provides the predictive capability of the model that can be used beyond simple circuit simulations. The BSlM models have been frequently used to predict circuit performance at different technology generations, and a web-based technology performance prediction platform based on BSIM3 has been developed [9]. In addition, a physical based approach can be used for statistical simulation, which is getting more and more important due to the more significant device-to-device variation in nanometric devices.

To achieve high computational efficiency, smoothing functions are introduced (Fig. 7) since BSIM3v3 to ensure the smoothness and continuity of the currents and charges as well as their derivatives (conductances and capacitances) for fast convergence in the SPICE engine. The formulation is an engineering solution that slightly compromised the accuracy in the small transition area between 2 operation regions. This minor imperfection has been compensated by introducing a few fitting parameters to allow users to refine the curves in the transition regions.

Fitting of device data from different technologies across the industry with high accuracy is the most challenging task. However, it is one of the most essential features in an industrial standard model and represents the final test of the practicality of the model. BSIM3 achieves the task by introducing a lot of parameters to allow engineers to adjust the simulated I-V characteristics. The tradeoff is the continuous increase in the number of parameters with time as shown in Fig. 8. The trend is similar to the increase in circuit and device complexity with time as predicted by the Moore’s law, to which model complexity has to follow. It should be noted that lots of the fitting parameters should only he handled by an efficient and powerful device extraction tool. The core equations of BSIM3 can be fitted by using only a few parameters. An example is given in Fig. 9 that a set of simplified equations given in Table 2 is used to fit the data

from a TSMC 0.18pm technology with only 9 parameters. A reasonable fitting is observed.

BSIM4 represent the forth generation of the family, which is a more research-type model, with many advanced features included. Compared with previous members of the family, it has lots of improvement in functionalities at the cost of more complicated formulation and more difficult to maintain.

5 MODELING IN NANO-TECHNOLOGY ERA

While the forth generation model like BSIM4 is a comprehensive model for existing technologies, catching up with the cunent pace of technology development is difficult. In addition, the model development time keep increasing with technology generation as shown in Fig. IO. The next generation modeling methodologies should be more proactive and should provide a simple methodology to adopt new features in the early development stage. An example is the gate-tunneling model to be used for different high-k dielectrics introduced. Instead of describing all the physical effects into a single equation, they should be broken up into modules as shown in Fig. 11. All internal nodes should be generated with a set of given parameters. As some features maybe mutually exclusive in real applications, users (or parameter extractors) can pick the important effects to be included in the model, or even add their own effects.

The tradeoff between model development time and simulation time is another issue worth considering. A good example is the need to recalculate all analytical derivatives even a minor change is introduced into the I-V equations. As a result, most of the valuable model development time will be spent on doing algebra and debugging. With the modem computer capability, numerical differentiation bas almost become a standard math library function and should be used. A minor drawback is the slight increase in computation time. But the real bottleneck in speed is the use of traditional programming methodology in a modem computer era. The speed of computation can he increased by methods such as parallel evaluation that is particularly suit for numerical differentiation.

Another important issue that bas always been overlooked is the job division between different simulation platforms in the CAD hierarchy. Modeling has been mostly done independently from other CAD tools. However, as device performance become more and more layout dependent, the job division between device model and layout extraction tools should be revisited.

6 CONC1,USION

With the tremendous development of advanced technology, device modeling is the key to the communication between technology developers and application engineers. The definition of a good model varies among different interest groups, and no single model can meet all the requirements. As a result, tradeoffs have to he made among the different and often conflicting criteria. The traditional way of model development is govemed by the FORTRAN style of programming methodology makes it difficult to catch up with the technology. New elements based on advanced software engineering methodology should be introduced in the next generation of models.

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ACKNOWLEDGEMENT

BSlM research was conducted by past and present team members at UC Berkely with support by SRC, EIA Compact Model Council, TI, Conexant, IBM, MICRO, DARPA and also Hong Kong RGC with a earmarked grant.

REFERENCES

[ I ] httu:N\~u?u.eierouo.oreicmc [2] httu:liwww-de~~icc.eecs.her~clcv.edu~sim3 [3]

[4]

[SI hrl~:ilu~ww.scmiconductors.vhilios.comlPhilius Model [6]

171

J. E. Meyer, “MOS models and circuit simulation”, RCA Rev., vol. 32, pp. 42-63, 1971 H . C. Pao et. al, Solid-state Electronics, vol. 9, pp. 927- 931, 1966

M. Miura-Mattausch el. al, Jap. J. Appl. Phys., vol. 29, pp. L2279-L2282.1990 C. C. Enz et. al. Low-Voltage Low-Power Design, vol.

I ? *‘I I I

. . 8,pp. 83-114, 1995 B. Sheu et. al., IEEE JSSC, vol. 22, pp. 558-566. [XI

[9] httii:Ii~~~\iww-device.eecs.berkelev.edul-ptni

.................... .................... : Foundrv : i Design house I , .

>..................; i ............... ..: Fig. 1: MOSFET model acts as a bridge between

designers and chip foundry

Fittine Accuracv

Short development time

Table 1: Primary foci of various interest groups

ID

I ( Y ) = I , = WQ, ( Y M Y )

Fig. 2:Fonulation of a charge-based model.

VSS = ov

VD = 1-5V 0.4

0.2

. . . . . . . . 0 1 2 3 4 5

VGS (VI

0 . 0 ’ .

6.0 I

Vcs = 1 -5V

2.0

1.0

0 1 2 3 4 5 VDS (v)

Fig. 3: Surface potential (a) at the source (&,) as a function of VGs and (b) at the drain (&) as a function of VOs

ut‘,,(-+ 0.5) \ 6 1 . 0 &= 1

I , uV,,(-+0.5) I 0.11 . . - . . ’ . . ’

0.01 0.1 1.0 10 100 Inversion ~ o e f i c i e n ~ = 1 ~ 2 n ~ ~ ~ ~ ~ ( W/L) v,&:

Fig. 4: Fitting of gJIO with current bias

10

3 , p e - 2 2%

- +

c

Table Lookup Model

Fig. 5: Positioning of compact model in the CAD hierarchy

81

ity

physical

accuracy

parameters

Fig. 6: Modeling tradeoff polygon

Fig. 7: Smoothing function used to connect the subthreshold and strong inversion region

19h5 1980 1990 2000 Year of introduction

Fig. 8: Number of parameters in various generations of models

-able 2: Simplified BSlM equation for hand calculation

"0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.82.0 VG (V)

vD

Fig. 9: Comparison of current-voltage curves from the full BSlM equations and the simplified equations. Model parameters taken from TSMC 0.18pm process with t0,=4.1nm. WlOpm, and VT0=0.39V

Engineering time and bug fix

improvement in model features

.- c / Engineering time and bug fix

...................... _ _ - - - - e d .............................. _ _ - - _ _ - - - - -

improvement in model features I

Technology Generation

Fig. I O : Result of current modeling practice

S D

U

Fig. 11: A modularized modeling approach

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