A 5.5-GHz Prescaler in 0.1 8-pm CMOS Technology Aruna B. Ajjikuttira Wei Liat Chan Yong Lian

Institute of Microelectronics 11 Science Park Road

National University of Singapore ECE Dept., 10 Kent Ridge Crescent

Singapore - 11 7685 Singapore - 119260 Singapore - 119260 +65 6770-5491 +65 6874-2993

aruna@ime.org.sg Ilmchan@singnet.com.sg eleliany@nus.edu.sg

National University of Singapore ECE Dept., 10 Kent Ridge Crescent

ABSTRACT A high-speed dual-modulus divide-by-32/33 prescal~r (DMP)

has been fabricated in a standard 0.18-pm CMOS process. It consists of a divide-by-4i5 synchronous divider implemented in MOS current-madc logic and a divide-by-8 asynchronous counter realized in differcntial cascode voltage-switch logic. A fully differential architecturc is adopted, which offers immunity against noise, fabrication process and upp ply voltage variation. The measurcd operating frequency rangc is from 4.6 to 6.2 GHr. making it suitable for WLAN applications. Including thc buffers, the circuit draws about 29 mA from a 1.8-V power supply aiid occupics lcss than 1 mm' die area.

Keywords CMOS, dual-modulus prescaler, WLAN

1. INTRODUCTION The dcvclopment of 5-GHz wircless applications has

generated much interest. Morc RF front-end circuits, implcmcnted in standard CMOS technologies. have emcrgcd. The design of such wirclcss transceivers requires the usc of high-performance frequency synthcsizcrs. The phase-locked loop (PLL) frequency synthesizer, shown in Fig. 1, is most commonly used [ I ] . The voltage-controlled oscillator (VCO) and dual-modulus prescaler (DMP) remain the most critical components in the facc of the ever increasing carrier frequency.

Operating at the highest frequency, the DMP divides the output frequency of thc VCO by one of the twv fixed ratios to a lower frcqucncy. This division ratio is controlled by a modulus control (MDC) signal generated by the programmable counter. Bcsides the high operating speed, thc DMP has also to he efticicnt in tenns of current consumption. and be able to work at low voltage supply. Unlike digital circuits which receive rail-to-rail input signals, the DMP has to work from sinall sinusoidal input signals. With these stringent requirements, dcsigning a DMP beconics challenging.

I . I

Figure 1. PLL frequency synthesizer block diagram

In this papcr, the design of a high-speed CMOS DMP is prrsentcd. The targeted frequency is thc allowed WLAN bands in the 5 to 6 GHz range. In section 2, the DMP topology is described, followcd by section 3 which explains thc circuit design. Section 4 ICQOI~S the measured performancc of the DMP. Finally, the last section draws some conclusions.

2. PRESCALER TOPOLOGY Thc high-speed DMP consists of a dividc-by-4E synchronous

divider and a divide-by-8 asynchronous divider. Differential implementation of this architecture, shown in Figure 2, is preferred tv the usual single-ended topology for common mode noise, fabrication process and supply voltage variation immunity. The division ratio (32 or 33) of this DMP is dctcmined by the MDC signal. When the MDC signal is at logic low, the output frequency of the synchronous divider is dctcrmined by the loop over the first 2 D flip-flops (DFFs) and this frequency equals to 'A of the input frequency. This frcqucncy is further divided by 8 in the asynchronous divider to give an output frequency. which cquals to 1/32 of the input frequency. This is a divdc-by-32 operation.

When the MDC signal is at logic high, thc DMP will perform a dividc-by-33 operation. The DMP continues to perform dividc- by-32 operation until the outputs (Q) of all the 3 DFFs of the asynchronous dividcr arc at logic low. At this point, a logic low signal from the output of the last static OR gate, together with an inverted signal, is sent to the synchronous divider. This C ~ U S C S the loop in thc latter to be mvmcntarily closed over the 3 DFFs instead of 2 in the previous case. This extra delay is equivalcnt to a divide-by-5 opcration. Thus, the DMP divides once by 5 and 7 times by 4, which gives an overall division by 33.

0-7803-7363-41028 17.00 02002 IEEE.

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Figure 2. Differential DMP architecture

D Q D Q

CLKCLK CLKCLK

Figure 3. Master-slave DFF

3. CIRCUIT DESIGN 3.1 Synchronous Divider

The divide-by-415 synchronous counter consists of 3 DFFs, 2 NAND gates and 2 NOR gales. As this divider operates at the maximum frequency, MOS current-mode logic (MCML) is used entirely in this block. It achieves high-speed by limiting thc voltage swings of all the nodes as the l o~ ,c r voltage swings nccd shorter time to toggle. The speed bottleneck of [he DMP, caused by the gates of the synchronous divider [2], will he removed as the gates are able to operate as fast as the DFFs.

Figure 3 shows a master-slave DFF, where the master and slave latches are clocked by differential clock signals, used in the synchronous divider. The schematic of the latch is given in Figure 4 [3]. It consists of a clocked differential sensing amplifier pair and an inversely clocked latch pair. To increase the switching speed, the current source connecting to the source terminals of

~ - - ~

Figure 4. Circuit schematic of a MCML hi-phase latch

D

Figure 5. Dynamic differential DFF

M1 and M2 is omitted. Also, the operating speed of the DFF can he incrcascd by allowing more current to flow through the latches. Vhias is grounded or the sires of M I , M2. M7 and M8 are incrcascd to push the maximum operating frequency. Besides the speed, the input sensitivity of the DFF is also paramount as the small sinusoidal voltage outputs of the VCO must be able to drive the DMP. To do so, the transconductance of the clock transistors, MI and M2, have to be large. However, this increased sensitivity comes at the expense of more powcr consumption, as thc sizes of M I and M2 have to be increased.

The NAND and NOR gates needed are shown in [4]. The schematics of both gates are exactly the same, except that the input cunnections are different. As these gates arc also drivcn by the same input source, their transconductance have to he large. The output signals of the synchronous divider cannot be directly applied to the asynchronous divider, where the latter needs almost rail-to-rail signals. A level-shifter is needed to fulfil this function.

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3.2 Asynchronous Divider The divide-by-8 asynchronous divider is made of 3 cascaded

divide-by-2 circuits. Figure 5 151 shows the DFF used in this divider. At each final output of the DMP, a 4-stage inverter buffer is added to drive the 50R system.

4. MEASUREMENT RESULTS The prescaler was realized in a standard 0.18-pm CMOS

technology. The dies wcre bonded to a 24-pin quad flat package and tested on a FR-4 PCB. From a 1.8V power supply. the circuit draws about 29 mA current, including the buffcrs. Figures 6 through 9 show thc output spectrum and the output waveform when connected to 50Q loads.

ATTEN ZBdB MKR . 5 8 d B m RL I 0 .0dBm IEdB/ 187.57PlHz

CENTER 187.58MHz SPAN 1 8 . BBPlHz RBW l E 8 k H z UBW IEBkHz SWP SB.0ms

Figure 6. Output spectrum of 6GHz divide-by-32 operation

i : \A...: . . . . :U: . LJ 'q I . .

. .

Figure 7. Output waveform of 6GHa divide-by-32 operation

ATTEN 2EdB CNT .JJdBm RL 1 0 . 0 d B m IEdB/ 181.82 RHr

CENTER lSl.82MHz SPAN 18. 8EMHz YRBW IBEkHz UBW l 8 0 k H z SWP 50 .0ms

Figure 8. Output spectrum of 6GHz divide-by-33 operation

Figure 9. Output waveform of 6GHz divide-by-33 operation

+Sample 2

4 6 4 8 5 5 2 5 4 5 6 5 8 6 6 2

Frequency (GHz)

Figure 10. Input power versus frequency for 132 at 1.W

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-Sample 1 -Sample 2 i +Sample 3

4 6 4 6 5 5 2 5 4 5 6 5 6 6 6 2 6 4

Frequency (GHz)

Figure 11. Input power versus frequency for133 at 1.8V

Figure 12. IC Microphotograph TABLE I

SUMMARY OF MEASUREMENT RESULTS 6. ACKNOWLEDGMENTS

in the layout of thc circuit.

7. REFERENCES [ I ] Seog-Jun Lee et al., “A Fully Integrated Low-Noise I-GHz

Frequency Synthesizer Design for Mobile Communication, Application,” IEEE I. Solid-State Circuits, vol. 32, no. 5 , pp. 760-764, May 1997

[2] Jan Craninckx et al.. ”A 1.75-GHz13-V Dual-Modulus Divide-by-I281129 Prescaler in 0.7-pm CMOS,’’ IEEE J . Solid-State Circuits, vol. 31, no. 7, pp. 890-897. July 1996

[ 3 ] Chih-Ming Hung et al.. “Fully Integrated 5.35-GHr CMOS VCOs and Prescalers,” lEEE Trans. Microwave Theory and Techniqucs, vol. 49, no. 1. pp. 17-22, January 2001

[41 Jason M. Musiccr C t al., “MOS Current Mode Logic for Low Power, Low Noisc CORDIC Computation in Mixed-Signal Environments,” in Proc. 2000 International Sym. Low Power Electronics and Design, 2000, pp. 102-107

Thc authors would like to thank Miss Doreen Tan for her help

Figures 10 and 1 I shows the input sensitivity of the measured samples. For this measurement, the losscs in thc PCB and package have not been taken into account. The pcrfonnance of the DMP is summarized in Table 1. Figure 12 shows the microphotograph of the chip. The total active area is 235km X 125pm.

~

5. CONCLUSION [5] Bram De Muer et al., “A single-ended ISGHz 819 dud(- modulus prescaler in 0.7pm CMOS with low phase noise A high-speed dual-modulus prescaler is implemented in 0.18-

km CMOS process [6]. An apcrating frequency range of 4.6 to and high input sensitivity,” in Proc. 1998 European Solid- 6.2 GHz with input sensitivity of bcttcr than -5 dBin for the 5 to 6 State Circuits Confcrence, 1998, pp. 256-259 GHr band i s achieved, making the design suitable for usc in [6] Wei Liat Chan, “Design of a High-speed Prescaler,” WLAN applications. Including the buffer, thc circuit draws about Bachelor of Enginccring Dissertation (submitted), National 29 mA from a 1.8-V supply. Univcrsity of Singapore, March 2002.

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