[IEEE 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San...
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• 2001 IEEE International Solid-State Circuits Conference 0-7803-6608-5 ©2001 IEEE ISSCC 2001 / SESSION 23 / ANALOG TECHNIQUES / 23.8 23.8 A 50GHz VCO in 0.25μm CMOS HongMo Wang Bell Labs, Murray Hill, NJ Integrated VCOs with fundamental frequencies in the millimeter- wave (mmW) bands have thus far been realized mainly in III-V technologies and the designs are mostly waveguide or transmis- sion-line based [1,2]. As CMOS technology progresses to deep sub- micron, however, the possibilities of integrating next-generation broadband communication transceivers of high bit-rate on a single chip using this low-cost technology are investigated. In so doing, one of the first questions is that whether a quality signal source or, more preferably, a VCO can be designed in such a technology. This work demonstrates feasibility of an LC-resonator based VCO in 0.25μm CMOS for operation at 50GHz consuming less power than its counterparts in other technologies while providing comparable phase noise and tuning performance. The technology used for the design is a 0.25μm (minimum L eff = 0.24μm) 1-poly-5-metal digital CMOS with a modified substrate, which consists of a 10Ω-cm bulk topped with a p + buried layer for latch-up suppression and an epi, and a thickened top metal [3]. The transistor characteristics and parasitics are not affected by the modification while higher quality inductors (peak Q around 16) can be realized. The minimum length nMOS transistor in sat- uration region with V GS – V T = 0.5V has an f T typically between 25GHz to 30GHz. Yet even with the 20Ω/❏ gate resistance and source-drain related resistances, a properly designed transistor can still have an f max >50GHz, which makes it possible to design an oscillator for operation at this frequency. Waveguide or transmission-line based resonators are commonly seen in mmW oscillator designs using other high-speed technolo- gies. In CMOS technology, however, an inductor-based LC type resonator can still compare favorably with other choices even at 50GHz. The low characteristic impedance normally associated with the waveguide or transmission line require higher gm from the transistors which results in a higher power consumption and/or a larger parasitic capacitance. Although oscillators using waveguide or transmission line resonators are able to deliver rel- atively higher output power directly to a matched low-impedance load, this advantage may become less important in an integrated environment. In comparison, an inductor based LC-resonator with a quality-factor (Q) around 10 can present considerably higher impedance at the resonant frequency. This high impedance lowers the required gm from the transistor, which in turn can lead to lower power consumption and a smaller parasitic capacitance. Impedance matching also appears to be lesser an issue in the inductor base designs. As pMOS transistors are unsuitable for operation at the frequen- cy of interest, a cross-coupled nMOS topology is used for the oscil- lator where pMOS transistors are used only in the bias circuitry. The simplified circuit diagram of the oscillator is shown in Figure 23.8.1. Rather than using the conventional approach wherein the bias current is injected at the middle of the inductor(s), two chokes are used for the purposes so that the tank inductor can be left alone without center-tapping or being broken into two. The two advantages associated with this arrangement are higher inductor Q and less mismatch in the inductor(s). One disadvantage is that additional chip areas may be needed to accommodate the two chokes. For a CMOS design at frequency well beyond its f T, proper design and modeling of both active and passive devices are essential. For the transistor model, a sub-circuit is constructed to include the parasitics and other phenomena usually ignored at lower frequen- cies. For accurate estimation of the inductor parameters, a 2.5-D electromagnetic field simulator [4] is used. Since the skin depth at 50GHz is only a small fraction of a micrometer, a fine mesh struc- ture is needed to capture the current distribution in the inductor that, in turn, demands a simulator capable of handling a large number of the meshed elements. The simulated Q of the inductor is about 16 at 50GHz. For the chokes, a large-enough inductance and a high-enough self-resonant frequency are the primary design goals as its Q has little effect on the overall Q of the tank. For tun- ing, an nMOS transistor within an n-tub is used as a varactor. The main design objective of the varactor is to maximize its Q. As the result, its tuning ratio (∆C/C 0 ) is limited at about 30%. The over- all tank capacitance has an estimated Q around 18. The VCO is tested by wafer probing. The bias condition for the VCO is set at 10mA from a 1.3V supply although the VCO is capa- ble of starting and oscillating with only 5mA bias current from a 1V supply. The on-chip buffers deliver the differential VCO output through external bias-TEEs to the 50Ω loads while consume a total of 4mW. The loss in the probe and cable is >7dB in the fre- quency band where the oscillator operates. The measured spec- trum from one end of the differential output shown in Figure 23.8.2 is free of any spurious. A close-in spectrum measurement is shown in Figure 23.8.3. The difference between the measured fre- quency and that predicted by the simulation is <5%. The phase noise measured at the center of the tuning range is shown in Fig- ure 23.8.4. As indicated by the marker, the single-side-band phase noise is below -99dBc/Hz at 1MHz offset from the carrier. For the phase noise measurement, a pre-amp with 10dB noise figure is used prior to the analyzer to overcome noise from the source with- in the analyzer. The phase noise measured at 1MHz offset from the carrier varies from –97dBc/Hz at low end to –100dBc/Hz at high end of the frequency tuning range. The degradation of phase noise towards lower frequency reflects the influence of the varac- tor on the overall Q of the tank. The tuning characteristics of the frequency and output power variation (from one end of the differ- ential output with cable and probe loss adjusted) are shown in Figure 23.8.5. The tuning range is about 1.1GHz with a 2.6V vari- ation in tuning voltage and the output power variation is about 3dB over the tuning range. The chip occupies 519x390μm 2 includ- ing pads. A micrograph is shown in Figure 23.8.6. Acknowledgements: Contributions by S. Kapur, D. Long, C. Ma, S. Moinian and help from Y. Baeyens, J. Brown, Y-K. Chen, G. Georgiou and J. Weiner are acknowl- edged. References: [1] H. Wang, et al., “Low Phase Noise Millimeter-Wave Frequency Sources Using InP-Based HBT MMIC Technology,” IEEE J. Solid-State Circuits, vol. 31, Oct. 1996, pp. 1419-1425. [2] M. Funabashi, et al., “Millimeter-Wave AlGaAs/InGaAs Heterojunction Finite-Element MMIC Oscillators,” Electr. and Com. in Japan, Part 2, vol. 78. May 1995, pp. 49-56. [3] M. R. Frei, et al., “Integration of High-Q Inductors in a Latch-up Resistant CMOS Technology”, IEDM Digest, Dec. 1999, pp. 757-760. [4] S. Kapur, D. E. Long, “IES3: Efficient Electrostatic And Electromagnetic Simulation”, IEEE Computational Sci. and Engr., vol. 5, Dec. 1998, pp. 60- 67.
Transcript of [IEEE 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San...
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• 2001 IEEE International Solid-State Circuits Conference 0-7803-6608-5 ©2001 IEEE
ISSCC 2001 / SESSION 23 / ANALOG TECHNIQUES / 23.8
23.8 A 50GHz VCO in 0.25µm CMOS
HongMo Wang
Bell Labs, Murray Hill, NJ
Integrated VCOs with fundamental frequencies in the millimeter-wave (mmW) bands have thus far been realized mainly in III-Vtechnologies and the designs are mostly waveguide or transmis-sion-line based [1,2]. As CMOS technology progresses to deep sub-micron, however, the possibilities of integrating next-generationbroadband communication transceivers of high bit-rate on a singlechip using this low-cost technology are investigated. In so doing,one of the first questions is that whether a quality signal source or,more preferably, a VCO can be designed in such a technology. Thiswork demonstrates feasibility of an LC-resonator based VCO in0.25µm CMOS for operation at 50GHz consuming less power thanits counterparts in other technologies while providing comparablephase noise and tuning performance.
The technology used for the design is a 0.25µm (minimum Leff =0.24µm) 1-poly-5-metal digital CMOS with a modified substrate,which consists of a 10Ω-cm bulk topped with a p+ buried layer forlatch-up suppression and an epi, and a thickened top metal [3].The transistor characteristics and parasitics are not affected bythe modification while higher quality inductors (peak Q around16) can be realized. The minimum length nMOS transistor in sat-uration region with VGS – VT = 0.5V has an fT typically between25GHz to 30GHz. Yet even with the 20Ω/ gate resistance andsource-drain related resistances, a properly designed transistorcan still have an fmax >50GHz, which makes it possible to designan oscillator for operation at this frequency.
Waveguide or transmission-line based resonators are commonlyseen in mmW oscillator designs using other high-speed technolo-gies. In CMOS technology, however, an inductor-based LC typeresonator can still compare favorably with other choices even at50GHz. The low characteristic impedance normally associatedwith the waveguide or transmission line require higher gm fromthe transistors which results in a higher power consumptionand/or a larger parasitic capacitance. Although oscillators usingwaveguide or transmission line resonators are able to deliver rel-atively higher output power directly to a matched low-impedanceload, this advantage may become less important in an integratedenvironment. In comparison, an inductor based LC-resonator witha quality-factor (Q) around 10 can present considerably higherimpedance at the resonant frequency. This high impedance lowersthe required gm from the transistor, which in turn can lead tolower power consumption and a smaller parasitic capacitance.Impedance matching also appears to be lesser an issue in theinductor base designs.
As pMOS transistors are unsuitable for operation at the frequen-cy of interest, a cross-coupled nMOS topology is used for the oscil-lator where pMOS transistors are used only in the bias circuitry.The simplified circuit diagram of the oscillator is shown in Figure23.8.1. Rather than using the conventional approach wherein thebias current is injected at the middle of the inductor(s), two chokesare used for the purposes so that the tank inductor can be leftalone without center-tapping or being broken into two. The twoadvantages associated with this arrangement are higher inductorQ and less mismatch in the inductor(s). One disadvantage is thatadditional chip areas may be needed to accommodate the twochokes.
For a CMOS design at frequency well beyond its fT, proper designand modeling of both active and passive devices are essential. Forthe transistor model, a sub-circuit is constructed to include the
parasitics and other phenomena usually ignored at lower frequen-cies. For accurate estimation of the inductor parameters, a 2.5-Delectromagnetic field simulator [4] is used. Since the skin depth at50GHz is only a small fraction of a micrometer, a fine mesh struc-ture is needed to capture the current distribution in the inductorthat, in turn, demands a simulator capable of handling a largenumber of the meshed elements. The simulated Q of the inductoris about 16 at 50GHz. For the chokes, a large-enough inductanceand a high-enough self-resonant frequency are the primary designgoals as its Q has little effect on the overall Q of the tank. For tun-ing, an nMOS transistor within an n-tub is used as a varactor. Themain design objective of the varactor is to maximize its Q. As theresult, its tuning ratio (∆C/C0) is limited at about 30%. The over-all tank capacitance has an estimated Q around 18.
The VCO is tested by wafer probing. The bias condition for theVCO is set at 10mA from a 1.3V supply although the VCO is capa-ble of starting and oscillating with only 5mA bias current from a1V supply. The on-chip buffers deliver the differential VCO outputthrough external bias-TEEs to the 50Ω loads while consume atotal of 4mW. The loss in the probe and cable is >7dB in the fre-quency band where the oscillator operates. The measured spec-trum from one end of the differential output shown in Figure23.8.2 is free of any spurious. A close-in spectrum measurement isshown in Figure 23.8.3. The difference between the measured fre-quency and that predicted by the simulation is <5%. The phasenoise measured at the center of the tuning range is shown in Fig-ure 23.8.4. As indicated by the marker, the single-side-band phasenoise is below -99dBc/Hz at 1MHz offset from the carrier. For thephase noise measurement, a pre-amp with 10dB noise figure isused prior to the analyzer to overcome noise from the source with-in the analyzer. The phase noise measured at 1MHz offset fromthe carrier varies from –97dBc/Hz at low end to –100dBc/Hz athigh end of the frequency tuning range. The degradation of phasenoise towards lower frequency reflects the influence of the varac-tor on the overall Q of the tank. The tuning characteristics of thefrequency and output power variation (from one end of the differ-ential output with cable and probe loss adjusted) are shown inFigure 23.8.5. The tuning range is about 1.1GHz with a 2.6V vari-ation in tuning voltage and the output power variation is about3dB over the tuning range. The chip occupies 519x390µm2 includ-ing pads. A micrograph is shown in Figure 23.8.6.
Acknowledgements:Contributions by S. Kapur, D. Long, C. Ma, S. Moinian and help from Y.Baeyens, J. Brown, Y-K. Chen, G. Georgiou and J. Weiner are acknowl-edged.
References:[1] H. Wang, et al., “Low Phase Noise Millimeter-Wave Frequency SourcesUsing InP-Based HBT MMIC Technology,” IEEE J. Solid-State Circuits, vol.31, Oct. 1996, pp. 1419-1425. [2] M. Funabashi, et al., “Millimeter-Wave AlGaAs/InGaAs HeterojunctionFinite-Element MMIC Oscillators,” Electr. and Com. in Japan, Part 2, vol.78. May 1995, pp. 49-56. [3] M. R. Frei, et al., “Integration of High-Q Inductors in a Latch-upResistant CMOS Technology”, IEDM Digest, Dec. 1999, pp. 757-760. [4] S. Kapur, D. E. Long, “IES3: Efficient Electrostatic And ElectromagneticSimulation”, IEEE Computational Sci. and Engr., vol. 5, Dec. 1998, pp. 60-67.
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• 2001 IEEE International Solid-State Circuits Conference 0-7803-6608-5 ©2001 IEEE
Figure 23.8.1: Simplified circuit diagram of the oscillator. Figure 23.8.2: Measured spectrum of the oscillator.
Figure 23.8.3: Measured close-in spectrum of the oscillator. Figure 23.8.4: Measured phase noise of the oscillator at center of the tuning range.
Figure 23.8.5: Measured frequency tuning curve and output power variation. Figure 23.8.6: Chip micrograph.
ISSCC 2001 / February 7, 2001 / Salon 7 / 4:30 PM
