FDL100N50F N-Channel MOSFET,FRFET · FDL100N50F N-Channel MOSFET,FRFET 500V, 100A, ... Programmable...
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Transcript of FDL100N50F N-Channel MOSFET,FRFET · FDL100N50F N-Channel MOSFET,FRFET 500V, 100A, ... Programmable...
May 2009
FDL100N
50F N-C
hannel MO
SFET
©2009 Fairchild Semiconductor CorporationFDL100N50F Rev. A
www.fairchildsemi.com1
UniFETTM
FDL100N50F N-Channel MOSFET,FRFET 500V, 100A, 0.055Ω
Features• RDS(on) = 0.043Ω ( Typ.)@ VGS = 10V, ID = 50A
• Low gate charge ( Typ. 238nC)
• Low Crss ( Typ. 64pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• RoHS Compliant
DescriptionThese N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology.
This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficient switched mode power supplies and active power factor correction.
MOSFET Maximum Ratings TC = 25oC unless otherwise noted
Thermal Characteristics
Symbol Parameter FDL100N50F UnitsVDSS Drain to Source Voltage 500 VVGSS Gate to Source Voltage ±30 V
ID Drain Current-Continuous (TC = 25oC) 100
A-Continuous (TC = 100oC) 60
IDM Drain Current - Pulsed (Note 1) 400 AEAS Single Pulsed Avalanche Energy (Note 2) 5000 mJIAR Avalanche Current (Note 1) 100 AEAR Repetitive Avalanche Energy (Note 1) 73.5 mJdv/dt Peak Diode Recovery dv/dt (Note 3) 20 V/ns
PD Power Dissipation(TC = 25oC) 2500 W- Derate above 25oC 20 W/oC
TJ, TSTG Operating and Storage Temperature Range -55 to +150 oC
TLMaximum Lead Temperature for Soldering Purpose,1/8” from Case for 5 Seconds 300 oC
Symbol Parameter Min. Max. UnitsRθJC Thermal Resistance, Junction to Case - 0.05
oC/WRθCS Thermal Resistance, Case to Sink Typ. 0.1 -RθJA Thermal Resistance, Junction to Ambient - 30
*Drain current limited by maximum junction temperature
D
G
S
TO-264FDL SeriesG SD
FDL100N
50F N-C
hannel MO
SFET
FDL100N50F Rev. A www.fairchildsemi.com2
Package Marking and Ordering Information
Electrical Characteristics TC = 25oC unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Device Marking Device Package Reel Size Tape Width QuantityFDL100N50F FDL100N50F TO-264 - - 30
Symbol Parameter Test Conditions Min. Typ. Max. Units
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V, TC = 25oC 500 - - V∆BVDSS ∆TJ
Breakdown Voltage Temperature Coefficient ID = 250µA, Referenced to 25oC - 0.5 - V/oC
IDSS Zero Gate Voltage Drain CurrentVDS = 500V, VGS = 0V - - 10
µAVDS = 400V, TC = 125oC - - 100
IGSS Gate to Body Leakage Current VGS = ±30V, VDS = 0V - - ±100 nA
VGS(th) Gate Threshold Voltage VGS = VDS, ID = 250µA 3.0 - 5.0 VRDS(on) Static Drain to Source On Resistance VGS = 10V, ID = 50A - 0.043 0.055 ΩgFS Forward Transconductance VDS = 20V, ID = 50A (Note 4) - 95 - S
Ciss Input CapacitanceVDS = 25V, VGS = 0Vf = 1MHz
- 12000 - pFCoss Output Capacitance - 1700 - pFCrss Reverse Transfer Capacitance - 64 - pFQg(tot) Total Gate Charge at 10V
VDD = 400V, ID = 50AVGS = 10V
- 238 - nCQgs Gate to Source Gate Charge - 74 - nCQgd Gate to Drain “Miller” Charge - 95 - nC
td(on) Turn-On Delay TimeVDD = 250V, ID = 50ARG = 4.7Ω
- 63 - nstr Turn-On Rise Time - 186 - nstd(off) Turn-Off Delay Time - 202 - nstf Turn-Off Fall Time - 105 - ns
IS Maximum Continuous Drain to Source Diode Forward Current - - 100 AISM Maximum Pulsed Drain to Source Diode Forward Current - - 400 AVSD Drain to Source Diode Forward Voltage VGS = 0V, ISD = 100A - - 1.5 Vtrr Reverse Recovery Time VGS = 0V, ISD = 100A
dIF/dt = 100A/µs- 250 - ns
Qrr Reverse Recovery Charge - 1.5 - nC
Notes:1. Repetitive Rating: Pulse width limited by maximum junction temperature
2. L = 1mH, IAS = 100A, VDD = 50V, RG = 25Ω, Starting TJ = 25°C3. ISD ≤ 100A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test: Pulse width ≤ 300µs, Duty Cycle ≤ 2%
5. Essentially Independent of Operating Temperature Typical Characteristics
FDL100N
50F N-C
hannel MO
SFET
FDL100N50F Rev. A www.fairchildsemi.com3
Typical Performance Characteristics
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics
Figure 3. On-Resistance Variation vs. Figure 4. Body Diode Forward Voltage Drain Current and Gate Voltage Variation vs. Source Current
and Temperature
Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics
0.1 1 100.5
1
10
100
300
*Notes: 1. 250µs Pulse Test 2. TC = 25oC
VGS = 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V
I D, D
rain
Cur
rent
[A]
VDS, Drain-Source Voltage[V]4 6 8 10
1
10
100
400
-55oC
150oC
*Notes: 1. VDS = 20V 2. 250µs Pulse Test
25oC
I D, D
rain
Cur
rent
[A]
VGS, Gate-Source Voltage[V]
0.0 0.5 1.0 1.51
10
100
300
*Notes:1. VGS = 0V2. 250µs Pulse Test
150oC
I S, R
ever
se D
rain
Cur
rent
[A]
VSD, Body Diode Forward Voltage [V]
25oC
0 50 100 150 200 2500.03
0.04
0.05
0.06
0.07
*Note: TC = 25oC
VGS = 20V
VGS = 10V
RD
S(O
N) [
Ω],
Dra
in-S
ourc
e O
n-R
esis
tanc
e
ID, Drain Current [A]
10-1 1 10 300
5000
10000
15000
20000
25000
30000
Coss
Ciss
Ciss = Cgs + Cgd (Cds = shorted)Coss = Cds + CgdCrss = Cgd
*Note: 1. VGS = 0V 2. f = 1MHz
Crss
Cap
acita
nces
[pF]
VDS, Drain-Source Voltage [V]0 50 100 150 200 250
0
2
4
6
8
10
*Note: ID = 50A
VDS = 100VVDS = 250VVDS = 400V
V GS,
Gat
e-So
urce
Vol
tage
[V]
Qg, Total Gate Charge [nC]
FDL100N
50F N-C
hannel MO
SFET
FDL100N50F Rev. A www.fairchildsemi.com4
Typical Performance Characteristics (Continued)
Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation vs. Temperature vs. Temperature
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs. Case Temperature
Figure 11. Transient Thermal Response Curve
-100 -50 0 50 100 150 2000.8
0.9
1.0
1.1
1.2
*Notes: 1. VGS = 0V 2. ID = 1mA
BV D
SS, [
Nor
mal
ized
]D
rain
-Sou
rce
Bre
akdo
wn
Volta
ge
TJ, Junction Temperature [oC]-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
*Notes: 1. VGS = 10V 2. ID = 50A
RD
S(on
), [N
orm
aliz
ed]
Dra
in-S
ourc
e O
n-R
esis
tanc
e
TJ, Junction Temperature [oC]
1 10 100 10000.01
0.1
1
10
100
100030µs
100µs1ms
10ms
I D, D
rain
Cur
rent
[A]
VDS, Drain-Source Voltage [V]
Operation in This Area is Limited by R DS(on)
*Notes: 1. TC = 25oC
2. TJ = 150oC 3. Single Pulse
DC
25 50 75 100 125 1500
20
40
60
80
100
120
I D
, Dra
in C
urre
nt [A
]
TC, Case Temperature [oC]
10-5 10-4 10-3 10-2 10-1 10.0001
0.001
0.01
0.1
0.01
0.1
0.2
0.05
0.02
*Notes: 1. ZθJC(t) = 0.05oC/W Max. 2. Duty Factor, D= t1/t2 3. TJM - TC = PDM * ZθJC(t)
0.5
Single pulse
Ther
mal
Res
pons
e [Z
θJC]
Rectangular Pulse Duration [sec]
t1
PDM
t2
FDL100N
50F N-C
hannel MO
SFET
FDL100N50F Rev. A www.fairchildsemi.com5
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
FDL100N
50F N-C
hannel MO
SFET
FDL100N50F Rev. A www.fairchildsemi.com6
Peak Diode Recovery dv/dt Test Circuit & Waveforms
D U T
V D S
+
_
D r i v e rR G
S a m e T y p e a s D U T
V G S • d v / d t c o n t r o l l e d b y R G
• I S D c o n t r o l l e d b y p u l s e p e r i o d
V D D
LI S D
1 0 VV G S
( D r i v e r )
I S D
( D U T )
V D S
( D U T )
V D D
B o d y D i o d eF o r w a r d V o l t a g e D r o p
V S D
I F M , B o d y D i o d e F o r w a r d C u r r e n t
B o d y D i o d e R e v e r s e C u r r e n t
I R M
B o d y D i o d e R e c o v e r y d v / d t
d i / d t
D =G a t e P u l s e W i d t hG a t e P u l s e P e r i o d
- - - - - - - - - - - - - - - - - - - - - - - - - -
D U T
V D S
+
_
D r i v e rR G
S a m e T y p e a s D U T
V G S • d v / d t c o n t r o l l e d b y R G
• I S D c o n t r o l l e d b y p u l s e p e r i o d
V D D
LLI S D
1 0 VV G S
( D r i v e r )
I S D
( D U T )
V D S
( D U T )
V D D
B o d y D i o d eF o r w a r d V o l t a g e D r o p
V S D
I F M , B o d y D i o d e F o r w a r d C u r r e n t
B o d y D i o d e R e v e r s e C u r r e n t
I R M
B o d y D i o d e R e c o v e r y d v / d t
d i / d t
D =G a t e P u l s e W i d t hG a t e P u l s e P e r i o d
- - - - - - - - - - - - - - - - - - - - - - - - - -D =G a t e P u l s e W i d t hG a t e P u l s e P e r i o d
- - - - - - - - - - - - - - - - - - - - - - - - - -
FDL100N
50F N-C
hannel MO
SFET
FDL100N50F Rev. A www.fairchildsemi.com7
Mechanical Dimensions
Dimensions in Millimeters
FDL100N
50F MO
SFET
FDL100N50F Rev. A www.fairchildsemi.com8
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*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONSDefinition of Terms
Auto-SPM™Build it Now™CorePLUS™CorePOWER™CROSSVOLT™CTL™Current Transfer Logic™EcoSPARK®
EfficentMax™EZSWITCH™ * ™*
Fairchild®
Fairchild Semiconductor®FACT Quiet Series™FACT®
FAST®
FastvCore™FETBench™FlashWriter® *FPS™
F-PFS™FRFET®
Global Power ResourceSM
Green FPS™Green FPS™ e-Series™Gmax™GTO™IntelliMAX™ISOPLANAR™MegaBuck™MICROCOUPLER™MicroFET™MicroPak™MillerDrive™MotionMax™Motion-SPM™OPTOLOGIC®
OPTOPLANAR®®
PDP SPM™Power-SPM™
PowerTrench®
PowerXS™Programmable Active Droop™QFET®
QS™Quiet Series™RapidConfigure™
™Saving our world, 1mW /W /kW at a time™SmartMax™SMART START™SPM®
STEALTH™SuperFET™SuperSOT™-3SuperSOT™-6SuperSOT™-8SupreMOS™SyncFET™Sync-Lock™
®*
The Power Franchise®
®
TinyBoost™TinyBuck™TinyLogic®
TINYOPTO™TinyPower™TinyPWM™TinyWire™TriFault Detect™TRUECURRENT™*µSerDes™
UHC®
Ultra FRFET™UniFET™VCX™VisualMax™XS™
tm
®
tm
tm
Datasheet Identification Product Status Definition
Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
Preliminary First ProductionDatasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.
No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.
Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.
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Rev. I40