Concurrent Triple Band Low Noise Amplifier Design

1

Concurrent Triple-Band Low Noise Amplifier Design

Presenter: Halil İbrahim Kayıhan

Supervisor: Assoc. Prof. Nil Tarım

Department: Electronic and Communication Engineering

JUNE 2015

www.hikayihan.com

www.hikayihan.com 2

Overview

Low noise amplifierCircuit topologies and biasingMatching networks and load circuits

Single band designTriple band design

Simulation results (0.18μm TSMC)S-parameter resultsNoise figure1dB compression point Third order intercept point

www.hikayihan.com 3

Low Noise Amplifier

Low noise figure Sensitivity of the total receiver chainFriis’ formula

Enough gainS21 parameter

Good input matchingS11 parameter

LinearityP1dB and IP3

www.hikayihan.com 4

LNA Structures

Common gateCommon source with resistive feedbackCascode with current mirrorCascode with source degeneration

Zi ZiZi

(a) (b) (c)

www.hikayihan.com 5

Single Band Cascode LNA

Source degeneration inductor provides the real part of the input impedance.

Zi

M1

M2

Ls

𝑍 𝑖=1¿¿

www.hikayihan.com 6

Biasing and Sizing the MOSFETs

M1

M2

Ls

Matching Network

DC

RFC

Cc

AC

50ohm

+VDD

VDD = 1.8VGate of M1 is VDD/2Equal overdrive voltages (Vgs-Vt)

and transconductance (gm)Coupling capacitorRFC

www.hikayihan.com 7

Biasing and Sizing the MOSFETs

W/L ratio is selected considering:TransconductanceParasitic capacitances

Source inductanceGate inductance

W/L = (20 X 5μm)/(0.18μm) with 20 fingers

www.hikayihan.com 8

Input Matching Network

Zi

M1

Ls

Lg

Cgs

Cgd

www.hikayihan.com 9


Inductors are modeled with series resistance

Modified input impedance expression

L

=>L

rL

www.hikayihan.com 10

Load Resonance Circuit

Load resonance circuit is a simple parallel LC circuit.

LoCo


Element Values

CC RFC Lg Ls Lo Co M1 M2

107.5pF 100nH 23.416nH 64pH 808.6pH 4.397pFW=100µm L=0.18µm

W=100µm L=0.18µm

LoCo

M1

M2

Ls

+VDD

Lg

Zi


Simulation Results

S11 and S21 parameters


Simulation Results

S12 parameter


Simulation Results

Noise figure


Simulation Results

1dB compression point


Simulation Results

Third order intercept point


Simulation Results

Total results

Output port impedance is 50ohm.ZO = 53.67+j*38.3.The proper LC network for output matching

can be used for a specific impedance.

fO S11 S21 S12 S22 NF P1dB IIP3

2.4GHz -42.22dB 19.44dB -44.91dB -5.48dB 2.61dB -18.23dBm -15.91dBm


Concurrent LNA Design

Simultaneous multiband operation without switching structures

Lower power consumptionReduced chip areaThree frequencies: 1.8GHz, 2.4GHz and

5.2GHzInput matching to 50ΩDesign for ideal and nonideal inductors and

capacitors


Cascode Structure and Biasing

Transistor circuit and biasing are the same for concurrent LNA

Concurrent LNA is designed with ideal elements and nonideal elements separately

For ideal case W/L ratio is (50μm/0.18μm)For nonideal case W/L ratio is

(100μm/0.18μm)Some values for ideal case:



Zi

M1

Ls

Lg

Cgs

Cgd

C2

L2

C1

L1



Equivalents for 1.8GHz, 2.4GHz and 5.2GHz

Lga2*L2a1*L1

Lga3*L2

Lg

(a)

(b)

(c)

b1/L1

b3/L2b2/L1



Coefficients and frequency values

a1 a2 a3 b1 b2 b3

1.8GHz 2.4GHz 5.2GHz 2.079GHz 3.533GHz



Input impedance expressions


Load Resonance Circuits

Conventional:


Load Resonance Circuits

Proposed:

L18 C18

L24 C24

L52 C52


Element Values

L1 L2 Lg Ls C1 C2

6.5664nH 19.647nH 27.766nH 213.64pH 922fF 104fF

L18 L24 L52 C18 C24 C52

100pH 100pH 100pH 78pF 43.975pF 9.35pF


Simulation Results

All circuit diagram:

Zi

M1

Ls

Lg

Cgs

Cgd

C2

L2

C1

L1

L18 C18

L24 C24

L52 C52

M2

Vout

Vin


Simulation Results

S11 and S21 parameters


Simulation Results

S12 parameter


Simulation Results

S22 parameter


Simulation Results

Noise figure


Simulation Results

Total results

Total results with nonideal capacitors

Frequency S11 S21 S12 NF P1dB IIP3

1.8 GHz -23.59dB 25.76dB -41.17dB 422mdB -15.80dBm -13.98dBm








Nonideal Case Input Matching

Zi

M1

Ls

Lg

Cgs

Cgd

C2

L2

C1

L1

rLg

rLp2rLp1

rLs



Parallel effective resistancesLga2*L2a1*L1

Lga3*L2

Lg

(a)

(b)

(c)

b1/L1

b3/L2b2/L1

rLp1 rLp2

rLp1 rLp2

rLp1 rLp2



Parallel RC and RL circuit expressions


Load Resonance Circuit Values

L18 L24 L52 C18 C24 C52

1.4nH 852.9pH 870pH 4.75pF 5.51pF 1.171pF


Simulation Results for Q=10

L1 L2 Lg Ls C1 C2

3.413nH 9.966nH 13.939nH 64.038pH 1.648pF 206.88fF


1.8 GHz -6.475dB 18.61dB -48.03dB 5.27dB -13.02dBm -20.00dBm





L1 L2 Lg Ls C1 C2

3.309nH 9.932nH 14.08nH 114pH 1.648pF 206.88fF







L1 L2 Lg Ls C1 C2

3.295nH 9.853nH 14.128nH 120pH 1.8056pF 204.72fF






Total Simulation Results

Q Frequency S11 S21 S12 NF P1dB IIP3

10

1.8 GHz

-6.475dB 18.61dB -48.03dB 5.27dB -13.02dBm -20.00dBm

30 -15.38dB 23.21dB -43.62dB 3.04dB -13.36dBm -20.07dBm

40 -20.14dB 24.16dB -42.71dB 2.45dB -14.20dBm -18.30dBm

Ideal -23.59dB 25.76dB -41.17dB 422mdB -15.80dBm -13.98dBm

10

2.4 GHz

-5.959dB 14.80dB -49.34dB 5.91dB -11.22dBm -17.36dBm

30 -17.48dB 20.87dB -43.46dB 2.69dB -12.61dBm -20.28dBm

40 -21.95dB 21.67dB -42.68dB 2.20dB -13.13dBm -20.32dBm


10

5.2 GHz

-43.91dB 15.63dB -41.81dB 2.70dB -9.08dBm -17.48dBm

30 -17.59dB 17.12dB -40.43dB 1.34dB -9.37dBm -17.25dBm

40 -16.56dB 17.31dB -40.25dB 1.14dB -9.35dBm -17.25dBm



Comparison with Other Works

Reference Frequency S11 S21 NF P1dB IIP3 Power

[1]

945 MHz -7.0dB 18.0dB 4.6dB - -12.8dBm

32.4mW2.4 GHz -15.0dB 24.0dB 4.4dB - -15.3dBm

5.25 GHz -10.0dB 23.0dB 4.4dB - -14.7dBm

[2]

2.4 GHz -10.3dB 11.8dB 3.8dB - -3.0dBm

13.5mW3.5 GHz -10.4dB 11.7dB 4.0dB - -2.1dBm

5.2 GHz -13.5dB 10.0dB 3.7dB - -0.4dBm

[3]

1.8 GHz -10.6dB 10.1dB 3.69dB -7.8dBm 1.7dBm

39.14mW2.45 GHz -10.4dB 10.8dB 4.75dB -9.8dBm 0dBm

5.25 GHz -19.9db 11.8dB 6.36dB -6.9dBm 4.5dBm

This Work

(Q=30)

1.8 GHz -15.38dB 23.21dB 3.04dB -13.36dBm -20.07dBm

21.35mW2.4 GHz -17.48dB 20.87dB 2.69dB -12.61dBm -20.28dBm

5.2 GHz -17.59dB 17.12dB 1.34dB -9.37dBm -17.25dBm


References[1] C.W. Ang, Y. Zheng, and C. H.Heng, “A multi-band CMOS low noise

amplifier for multi-standard wireless receivers,” in IEEE Int. Circuits

Syst. Symp. Dig., 2007, pp. 2802–2805.

[2] C. Y. Kao, Y. T. Chiang, and J. R. Yang, “A concurrent multi-band

low-noise amplifier for WLAN/WiMAX applications,” in IEEE Int.

Electron./Inform. Technol. Conf. Dig., 2008, pp. 514–517.

[3] Christina F. Jou , Kuo-Hua Cheng , Eing-Tsang Lu and Yang Wang, "Design Of A Fully Integrated Concurrent Triple-Band CMOS Low Noise Amplifier", IEEE, 2004

Concurrent Triple Band Low Noise Amplifier Design

Engineering

Transcript of Concurrent Triple Band Low Noise Amplifier Design