Resistors

CMOS - Devices

sheet resistance – If Z = cte, a square (L = W) has a resistance value which is independent of W : R = ρ L / A =ρ L / (W Z) =ρ / ZA rectangle has a resistance:R = ρ L / (W Z) = R L / W

AL

Z

W

RAB = ( 3 + 0,5 + 0,55 ) R

1 1 0,5

1

0,55

A

BEx:

Mobility

)( pAnD NNq µµσ ×+××=

CMOS - Devices

Resistivity of semiconductors

)( pAnD NNq µµσ ×+××=

CMOS - Devices

Resistors

CMOS - Devices

Implementation of linear resistors:

- With poly (+salicide block if available)

- With diffusion (+salicide block if available)

Depending on the PDK can be extracted as 2 or 3 terminal devices: Large resistor values require large areas (long devices) hence large parasitic capacitances may result.-Usually the main tradeoff consists on AREA x POWER

Resistors

CMOS - Devices

Due to the large Ω/sq values poly resistors (AND well) are very sensitive toward variations in L and W which results in fairly large tolerance levels (30% tolerance simulations are required).

–The absolute accuracy is quite poor.–The relative match is much better.

Resistors

CMOS - Devices

Non-linear resistors or voltage dividers can be implemented with MOS transistors (1/2, 1/3, 2/3, …)

VDD

VDD / 2The thresholdvoltage must beachieved ineach transistor

Capacitors

Capacity – An overlap area A causes a capacitance C = A Cx, , where Cx represents the capacity density.

tAkC 0ε=

k = dielectric constant (SiO2 = 3.9)εo = 8.85 x 10-12 F/mA = capacitor area (m2)T = dielectric thickness (m)

CMOS - Devices

Capacitors

•Metal Insulator Metal (MIM)

•MOSCAP

•POLY capacitors

•varactor

CMOS - Devices

Capacitors

Metal Insulator Metal (MIM):–MIMCAP’s require no analog-specific processing steps and are readily implemented in any IC process.–Implements only relatively small capacitance values. A combination of large ’h’ and the resulting moderate inter-metal coubling the area efficiency is limited.–Suffers from back-plate parasitic capacitance which makes their use limited in differential designs.–The MIMCAP is a linear device with respect to voltage.–Has relative small temperature dependency.- If more than two metal layers are available one would NEVER use the bottom two, unless the bottom plate effect is desired.

CMOS - Devices

MOSCAP:-MOS and MIMCAP’s are close relatives. The only difference is that MOSCAP use gate oxide as isolator.–Gate oxide is a key parameter and is tightly controlled. This implies that h is small (equal to tox) resulting in fairly large and accurate capacitance values.- MOS (unlike MIM) requires contacts to access the N+ layer which adds parasitic resistors.

CMOS - Devices

Capacitors

MOSCAP:-When evaluated the C(Vg) characteristic reveals three distinctively different areas:

CMOS - Devices

Capacitors

POLY:-If available, double-poly capacitors represent a better solution if linear operation is desired. -Here two poly layers are available and these are used to form the two plates of the capacitor.-Parasitics are still present but as the two poly plates are very closely spaced the capacitance is dominated by the plate capacitance.

CMOS - Devices

Capacitors

POLY:

-To limit parasitic resistance quite a few contacts have to be used to form the connections to the poly plates.

–To help minimize this effect a finger structure like that used for the MOSFET may be utilized for capacitors as well.

CMOS - Devices

Capacitors

Varactors:

-Finely tunable capacitances are needed for different designs

-MOSCAP C(V)

-PN junction on nwell

CMOS - Devices

Capacitors

Junction capacity:

C = A Cj + P Cjsw

• A represents the junction bottom area and Cj is the capacitance density,

• P represents the junction perimeter• Cj and Cjsw are spice parameters that depend on the junction

voltage

CMOS - Devices

Capacitors

Diodes

Vss

Vdd

CMOS - Devices

Diodes are useful for:

-voltage reference circuit design (bandgap)-voltage clamping

Process limited connectivity:

n+

subs. p

p+

Vss

poço n-

p+

A BA

n+

subs. p Vss

p+

AA B

p+

B

•In a P substrate •In a Nwell

CMOS - Devices

Diodes

CMOS - Devices

LATCH-UP

CMOS - Devices

LATCH-UP

Parasitas

• Dispositivos parasitas formados durante o processo de fabrico• Podem reduzir o desempenho ou até impedir o funcionamento

• Resistências parasitas:• Todos os caminhos condutores do circuito têm uma resistência

associada• As resistências atrasam a propagação dos sinais• É a razão da passagem do routing de Al para Cu

• Capacidades parasitas:• Há capacidades parasitas entre cada dois níveis condutores

sobrepostos e em cada junção PN• Os condensadores atrasam a propagação dos sinais

CMOS - Devices

Efeitos Parasitas (CMOS)

Lineares

Não Lineares

Interligações: • capacidades: Cpoly, Cm1, etc• resistências: Rpoly, Rn+, etc

TMOS:• cap. sobreposição (CGSO,CGDO,CGBO)

Interligações: • capacidades: Cpoly, Cm1, etc• resistências: Rpoly, Rn+, etc

TMOS:• cap. sobreposição (CGSO,CGDO,CGBO)

Capacidades não lineares• de junção (plana e curva)• de porta-canal

Capacidades não lineares• de junção (plana e curva)• de porta-canal

TMOS parasitas (fora das áreas activas)TMOS parasitas (fora das áreas activas)

Díodos de Junção (junções n+/sub, p+/well)Díodos de Junção (junções n+/sub, p+/well)

Transistores de Junção Bipolar (hor., vert.)Transistores de Junção Bipolar (hor., vert.)

+ indutâncias ...

Parasitas

CMOS - Devices

Parasitas• Transístores parasitas:

• Formam-se pela alternância de junções PN (na vertical ou horizontal)

• A entrada em condução destes dispositivos é denominada “Latch-Up”

• Usados em alguns circuitos (ex: bandgap)

p +

D r a in S o u r c e

n - w e l l

p + n +

n - w e l lc o n t a c t

p +

s u b s t r a t ec o n t a c t G a t e

CMOS - Devices