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A 0.16mm2 12b 30MS/s 0.18μm CMOS SAR ADC Based on Low-Power Composite Switching

Jong-Min Jeong, Tai-Ji An, Hee-Wook Shin, Gi-Wook Lee, and Seung-Hoon Lee Dept. of Electronic Engineering, Sogang University, Seoul, Korea

hoonlee@sogang.ac.kr

Abstract— This work proposes a 12b 30MS/s 0.18μm SAR ADC based on a low-power composite switching technique to reduce the required number of capacitors and switching energy. The proposed composite switching employs VCM-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. A split capacitor topology implements the VCM-based switching scheme effectively without extra switches in the DAC and the SAR logic. Moreover, the proposed C-R hybrid DAC architecture minimizes the DAC area by reducing the total number of unit capacitors in the DAC up to 32. The prototype ADC in a 0.18μm CMOS technology occupies an active die area of 0.16mm2 and consumes 1.93mW at a 1.8V supply voltage without on-chip I/V references.

Keywords- analog-to-digital converter (ADC); composite switching; C-R hybrid digital-to-analog converter (DAC); split capacitor; image sensor

I. INTRODUCTION Nowadays, it has become increasingly important to develop

a system-on-a-chip (SoC) which integrates various functional circuits for medical ultrasound devices, image sensors, and other applications on a single chip with advances in semiconductor integration technology. Especially, the SoCs for sensor applications require low-power high-resolution analog-to-digital converters (ADCs). Furthermore, the ADCs need to be implemented in a small chip area with high power efficiency since so many circuits are implemented on a single chip [1]. Hence, the successive-approximation register (SAR) ADC based on digital logic circuits is more competitive than the pipeline, delta-sigma, and algorithmic ADCs with advances in micro- to nanometer-scale CMOS technologies to minimize chip area and power consumption simultaneously [2].

II. PROPOSED SAR ADC ARCHITECTURE The proposed 12b 30MS/s 0.18μm SAR ADC based on a

low-power composite switching scheme consists of a C-R hybrid digital-to-analog converter (DAC), a comparator, a SAR logic block, and on-chip current and voltage (I/V) references, as shown in Fig. 1. The proposed composite switching scheme is composed of common-mode voltage (VCM)-based switching and monotonic switching methods in sequence to minimize the switching power consumption and the dynamic offset caused by DAC output common mode voltage (VDAC,CM) variations. The typical signal-dependent charge injection is alleviated through a bottom-plate sampling. The proposed

DAC employs a split capacitor topology instead of a lumped capacitor to implement an equivalent VCM-based switching scheme without extra switches in the DAC and the SAR logic. A reference scaling technique matches an input range with the reference voltage range. The total number of unit capacitors in the DAC is much more reduced by adopting a C-R hybrid DAC.

Fig. 1. Proposed 12b 30MS/s 0.18μm CMOS SAR ADC.

III. CIRCUIT IMPLEMENTATION

A. Proposed Composite Switching Scheme The proposed composite switching scheme reduces the

dynamic offset of the DAC as much as required for a 12b accuracy. As an example, the DAC output voltage is shown in Fig. 2 when a digital output code of the proposed SAR ADC is set at ‘100000000000’.

Fig. 2. Example of composite switching.

This work was supported by the Ministry of Science, ICT and Future Planning, Korea, under the Information Technology Research Center support program (IITP-2015-H8501-15-1002) supervised by the Institute for Information & communications Technology Promotion, and the Basic Science Research Program through the National Research Foundation of Korea funded by the Ministry of Education (Grant No. 2013R1A1A2004829).

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The proposed composite switching scheme decides the digital output codes in two steps. The two most significant bits (MSBs) and the remaining bits are decided through the VCM-based switching and the monotonic switching, respectively. By deciding the two MSBs through the VCM-based switching, a maximum VDAC,CM variation is considerably decreased, as shown in Fig. 3. On the other hand, the monotonic switching decreases the VDAC,CM variation furthermore with two different monotonic switching paths, which are down-transition switching for the third bit and up-transition switching for the other remaining bits. As a result, the maximum VDAC,CM variation is less than 1/16VREF while the dynamic offset degrading the SAR ADC linearity is considerably minimized. The VDAC,CM variations of the proposed composite switching scheme and the conventional monotonic switching scheme are simulated and compared in Fig. 3.

Fig. 3. Comparison of VDAC,CM variations

B. Split Capacitor Topology The proposed DAC employs a split capacitor topology

rather than a single lumped capacitor to implement an equivalent VCM without extra switches and logic circuits in the DAC. The operation of split capacitors is illustrated in Fig. 4. A single large capacitor is divided up into two small identical capacitors. With the VCM-based switching, two different top and bottom reference voltages, VREF+ and VREF-, are connected to each bottom plate of two identical capacitors for the two MSBs, just before comparison operation. It is equivalent that VCM is connected to the bottom plate of two split capacitors for the two MSBs. After comparison operation is completed, each bottom plate of two identical capacitors can be connected with the same reference voltage, VREF+ or VREF-, depending on the finalized digital output code, as shown in Fig. 4. Thus, the VCM-based switching is implemented without additional switches and the corresponding digital logic circuits.

Fig. 4. Operation of split capacitors.

IV. SIMULATION RESULTS The prototype 12b 30MS/s ADC is implemented in a

0.18μm CMOS technology as shown in Fig.5. The simulated ADC with an active die area of 0.16mm2 consumes 1.93mW excluding on-chip I/V references. When multi-purpose on-chip I/V references for various applications are included, the ADC has an active die area of 0.25mm2 and a power consumption of 5.6mW.

Fig. 5. Chip layout of the prototype ADC.

The simulation results of the proposed SAR ADC in a 0.18μm CMOS are summarized in Fig. 6. When 5 major input signals, VIN, are sampled at a sampling frequency of 30MS/s, CLKSAM, each input signal is accurately converted into a corresponding digital output of 12b as expected with an input range of 1.4VP-P at a 1.8V supply.

Fig. 6. Simulation results of the proposed 0.18μm CMOS SAR ADC.

V. CONCLUSIONS This work proposes a 12b 30MS/s 0.18μm CMOS SAR

ADC based on a low-power composite switching scheme to minimize the required number of capacitors and switching energy. The simulated ADC with an active die area of 0.16mm2 consumes 1.93mW at 30MS/s and a 1.8V supply voltage.

REFERENCES [1] M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, “A 10b

50MS/s 820uW SAR ADC with on-chip digital calibration,” in ISSCC Dig. Tech. Papers, Feb. 2010, pp. 384-385.

[2] C. C. Liu, et al., “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010.

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