arithmetic circuits-2 2004 - Duke...

ECE 261 James Morizio 1

Arithmetic Circuits-2

• Multipliers– Array multipliers

• Shifters– Barrel shifter

– Logarithmic shifter


Binary Multiplication

Z = X * Y

= Σ (Σ XiYj2i+j)

i=0

N-1

j=0

M-1

Partial products

Product

• Product = Sum of partial products

Y = Σ Yi 2ii=0

X = Σ Xi 2i

i=0

M-1 N-1

Multiplicand Multiplier


Multiplication

• Example:

1100 : 1210

0101 : 510


Multiplication

• Example:

1100 : 1210

0101 : 510

1100


Multiplication

• Example:

1100 : 1210

0101 : 510

1100

0000


Multiplication

• Example:

1100 : 1210

0101 : 510

1100

0000

1100


Multiplication

• Example:

1100 : 1210

0101 : 510

1100

0000

1100

0000


Multiplication

• Example:

1100 : 1210

0101 : 510

1100

0000

1100

0000

00111100 : 6010


Multiplication

• Example:

• M x N-bit multiplication

– Produce N M-bit partial products

– Sum these to produce M+N-bit product

1100 : 1210

0101 : 510

1100

0000

1100

0000

00111100 : 6010

multiplier

multiplicand

partial

products

product


The Binary Multiplication

1 0 1 1

1 0 1 0 1 0

0 0 0 0 0 0

1 0 1 0 1 0

1 0 1 0 1 0

1 0 1 0 1 0

1 1 1 0 0 1 1 1 0

+

Partial Products

AND operation

Multiplicand

Multiplier


General Form• Multiplicand: Y = (yM-1, yM-2, …, y1, y0)

• Multiplier: X = (xN-1, xN-2, …, x1, x0)

• Product:

1 1 1 1

0 0 0 0

2 2 2M N N M

j i i j

j i i j

j i i j

P y x x y− − − −

+

= = = =

= =

∑ ∑ ∑∑

x0y

5x

0y

4x

0y

3x

0y

2x

0y

1x

0y

0

y5

y4

y3

y2

y1

y0

x5

x4

x3

x2

x1

x0

x1y

5x

1y

4x

1y

3x

1y

2x

1y

1x

1y

0

x2y

5x

2y

4x

2y

3x

2y

2x

2y

1x

2y

0

x3y

5x

3y

4x

3y

3x

3y

2x

3y

1x

3y

0

x4y

5x

4y

4x

4y

3x

4y

2x

4y

1x

4y

0

x5y

5x

5y

4x

5y

3x

5y

2x

5y

1x

5y

0

p0

p1

p2

p3

p4

p5

p6

p7

p8

p9

p10

p11

multiplier

multiplicand

partial

products

product


Dot Diagram• Each dot represents a bit

partial products

multip

lier x

x0

x15


The Array Multiplier

HA FA FA HA

FA FA FA HA

FA FA FA HA

Z1

Z2

Z3Z4Z5Z6

Z0

Z7

y0

y3

y1

x0x1x2x3 y2

x0x1x2x3

x0x1x2x3

x0x1x2x3

FA: Full adder

HA: Half adder

(two inputs)

Propagation delay = ?


The MxN Array Multiplier

— Critical Path

HA FA FA HA

HAFAFAFA

FAFA FA HA

Critical Path 1

Critical Path 2

Critical Path 1 & 2


Carry-Save Multiplier

HA HA HA HA

FAFAFAHA

FAHA FA FA

FAHA FA HA

Carries saved for next

adder stage

Unique critical path

Trade offs?


Adder Cells in Array Multiplier

A

B

P

Ci

VDD

A

A A

VDD

Ci

A

P

AB

VDD

VDD

Ci

Ci

Co

S

Ci

P

P

P

P

P

Identical Delays for Carry and Sum


Multiplier Floorplan

SCSCSCSC

SCSCSCSC

SCSCSCSC

SC

SC

SC

SC

Z0

Z1

Z2

Z3Z4Z5Z6Z7

X0X1X2X3

Y1

Y2

Y3

Y0

Vector Merging Cell

HA Multiplier Cell

FA Multiplier Cell

X and Y signals are broadcasted

through the complete array.


Multipliers —Summary

• Optimiz a tion Goa ls Diffe re nt Vs Binary Adde r

• Onc e Aga in: Ide ntify Critic a l P a th

• Othe r pos s ible te c hnique s

- Data e nc oding (Booth)

- P ipe lining

- Logarithmic ve rs us Line ar (Wallace tree

multiplier)


Comparators

• 0’s detector: A = 00…000

• 1’s detector: A = 11…111

• Equality comparator: A = B

• Magnitude comparator: A < B


1’s & 0’s Detectors

• 1’s detector: N-input AND gate

• 0’s detector: NOTs + 1’s detector (N-input NOR)

A0

A1

A2

A3

A4

A5

A6

A7

allones

A0

A1

A2

A3

allzeros

allones

A1

A2

A3

A4

A5

A6

A7

A0


Equality Comparator

• Check if each bit is equal (XNOR, aka equality

gate)

• 1’s detect on bitwise equality

A[0]B[0]

A = B

A[1]B[1]

A[2]B[2]

A[3]B[3]


Magnitude Comparator• Compute B-A and look at sign

• B-A = B + ~A + 1

• For unsigned numbers, carry out is sign bit

A0

B0

A1

B1

A2

B2

A3

B3

A = BZ

C

A B≤

N A B≥


Shifters

• Logical Shift:

– Shifts number left or right and fills with 0’s

• 1011 LSR 1 = 0101 1011 LSL1 = 0110

• Arithmetic Shift:

– Shifts number left or right. Rt shift sign extends

• 1011 ASR1 = 1101 1011 ASL1 = 0110

• Rotate:

– Shifts number left or right and fills with lost bits

• 1011 ROR1 = 1101 1011 ROL1 = 0111


The Binary Shifter

Ai

Ai-1

Bi

Bi-1

Right Leftnop

Bit-Slice i

One-bit shifts


Multi-bit Shifters

• Cascade one-bit shifters?

• Complex, unwieldy, slow for larger number of

shifts

• Two other types of shifters– Barrel shifter

– Logarithmic shifter


The Barrel Shifter

Sh3Sh2Sh1Sh0

Sh3

Sh2

Sh1

A3

A2

A1

A0

B3

B2

B1

B0

: Control Wire

: Data Wire

Shift by 0 to

3 bits


The Barrel Shifter

• Area dominated by wiring

• Propagation delay is theoretically constant (at most one

transmission gate), independent of shifter size, no. of

shifts

• Reality: Capacitance on buffer input α maximum shift

width


4x4 barrel shifter

BufferSh3Sh2Sh1Sh0

A3

A2

A1

A0

Widthbarrel ~ 2 pmM pm = metal/poly pitch

M = no. of shifts


Logarithmic Shifter

Sh1 Sh1 Sh2 Sh2 Sh4 Sh4

A3

A2

A1

A0

B1

B0

B2

B3

• Staged approach, e.g. 7 = 1 + 2 + 4, 5 = 1 + 0 + 4

• Shifter with maximum shift width M consists of log2M stages


0-7 bit Logarithmic Shifter

A3

A2

A1

A0

Out3

Out2

Out1

Out0


Funnel Shifter

• A funnel shifter can do all six types of shifts

• Selects N-bit field Y from 2N-bit input

– Shift by k bits (0 ≤ k < N)

B C

offsetoffset + N-1

0N-12N-1

Y


Funnel Shifter Operation

• Computing N-k requires an adder


Funnel Shifter Design 1• N N-input multiplexers

– Use 1-of-N hot select signals for shift amount

– nMOS pass transistor design (Vt drops!)k[1:0]

s0

s1

s2

s3

Y3

Y2

Y1

Y0

Z0

Z1

Z2

Z3

Z4

Z5

Z6

left Inverters & Decoder


Funnel Shifter Design 2

• Log N stages of 2-input muxes

– No select decoding needed

Y3

Y2

Y1

Y0

Z0

Z1

Z2

Z3

Z4

Z5

Z6

k0

k1

left

arithmetic circuits-2 2004 - Duke...

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