Application Note JEDEC e MMCTM Ver4.41α,Ver.4.5 … · 37 Remark on the potential bug of Linux...

©2014 TOSHIBA CORPORATION CONFIDENTIAL of 120

M1PCA00-0008

Application Note JEDEC e-MMCTM

Ver4.41α,Ver.4.5 and V5.0

Memory Division

TOSHIBA Semiconductor & Storage products Company

e-MMCTM

is a trademark and a product category for a class of embedded memory

products built to the joint JEDEC/MultiMediaCard Association (MMCA) MMC

Standard specification.

(Jan., 2014 Rev 1.73)


M1PCA00-0008

Disclaimer

The information contained herein is presented only as a guide for the

application of TOSHIBA products. No responsibility is assumed by TOSHIBA

for any infringements of patents or other rights of third parties which may

result from its use. No license is granted by implication or otherwise under any

patent or patent rights of TOSHIBA or others.

The information in this document is provided "as is", with no warranties.

This document is provided for informational purpose only.

The information in this document is preliminary and is subject to change at any

time, without prior notice.


M1PCA00-0008

About this document

This document is intended to provide information for the use of TOSHIBA’s e-MMCTM

.

The information given in this document will help the user to understand how to use it

based upon the JEDEC e-MMCTM

standard.


M1PCA00-0008

1 Introduction ........................................................................................................................................10

1.1 OVERVIEW .......................................................................................................................................10 1.2 DEFINITIONS AND ACRONYMS .........................................................................................................10

2 JEDEC e-MMCTM

Standard .............................................................................................................11

2.1 WHAT VERSION ARE THE TOSHIBA’S E-MMCTM

DEVICES COMPLIANT TO?.................................11 2.2 THE DIFFERENCES BETWEEN V4.41Α,V4.5 AND V5.0 ......................................................................11

3 e-MMCTM

System Architecture ........................................................................................................13

3.1 COMPOSITION OF AN E-MMCTM

SYSTEM .........................................................................................13 3.2 BLOCK DIAGRAM OF THE E-MMC

TM SYSTEM ..................................................................................14

3.3 PIN CONNECTION OF THE BGA PACKAGE .........................................................................................15 3.4 NC PINS AND RFU TREATMENT ......................................................................................................20 3.5 RECOMMENDED WIRING: HOST BUS ................................................................................................21 3.6 RECOMMENDED WIRING : VDDI......................................................................................................22 3.7 RECOMMENDED WIRING: RST_N ....................................................................................................22 3.8 DIFFERENCES IN THE PIN ASSIGNMENT OF THE JEDEC VERSIONS ...................................................22

4 Additional Partitions Configuration (V4.41α or later) ...................................................................23

4.1 INITIAL PARTITION ARCHITECTURE .................................................................................................23 4.2 ADDITIONAL PARTITIONS CONFIGURATION .....................................................................................24 4.3 AN EXAMPLE OF PARTITION ARCHITECTURE ...................................................................................28 4.4 POINTS TO CONSIDER .......................................................................................................................29

5 Boot Process for e-MMCTM

(V4.41α or later) ..................................................................................31

5.1 SELECT BOOT PARTITION .................................................................................................................31 5.2 SELECT BOOT ACKNOWLEDGEMENT................................................................................................31 5.3 ENABLE HARDWARE RESET OPERATION..........................................................................................31 5.4 BOOT OPERATION ............................................................................................................................32 5.5 ALTERNATIVE BOOT OPERATION .....................................................................................................33

6 Auto Sleep Optimization ...................................................................................................................34

6.1 AUTO SLEEP FUNCTION ....................................................................................................................34 6.2 AUTO SLEEP SPECIFICATION COMPARISON .......................................................................................34 6.3 AUTO-BKOPS AND AUTO SLEEP .....................................................................................................35 6.4 POINT TO NOTICE REGARDING AUTO SLEEP .....................................................................................36 6.5 FURTHER REDUCE CURRENT CONSUMPTION .....................................................................................36

7 Secure Erase Operation (V4.41α or later) .......................................................................................38

8 Production State Awareness (V5.0) ..................................................................................................39

8.1 PRODUCTION STATE AWARENESS RELATED REGISTER FIELDS .........................................................40 8.2 RECOMMENDED SOLDERING PROCEDURE ........................................................................................42

9 Field Firmware Update (FFU) (V5.0) ...............................................................................................43

9.1 FFU RELATED REGISTER FIELDS .......................................................................................................43 9.2 FIELD FIRMWARE UPDATE SEQUENCE .............................................................................................45

10 Hardware reset (V4.41α or later) .....................................................................................................46

10.1 DEFINITION IN JEDEC STANDARD ...................................................................................................46 10.2 INITIALIZATION RECOMMENDATION ................................................................................................47

11 High Priority Interrupt (HPI) (V4.41α or later) .............................................................................48

HPI COMMANDS ...............................................................................................................................48 11.1 48 11.2 INTERRUPTIBLE COMMANDS ............................................................................................................48 11.3 HPI RELATED REGISTER FIELDS .......................................................................................................49 11.4 HPI PRE-PROCESS.............................................................................................................................50 11.5 HPI PROCESS ....................................................................................................................................51


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11.6 HPI POST-PROCESS ...........................................................................................................................52 12 Background Operation (V4.41α or later) .........................................................................................53

12.1 BACKGROUND OPERATION RELATED REGISTER FIELDS ....................................................................53 12.2 BACKGROUND OPERATION PRE-PROCESS .........................................................................................55 12.3 START & STOP BACKGROUND OPERATION .......................................................................................56

13 Combination of HPI and Background operation (V4.41α or later) ...............................................57

13.1 THE HPI PROCESSING FLOW SPECIFIED BY JEDEC ..........................................................................57 13.2 HPI TIMING AND POST-PROCESS .......................................................................................................58 13.3 HPI & BACKGROUND OPERATION SEQUENCE ..................................................................................59

14 Write Reliability (V4.41α or later) ...................................................................................................60

14.1 WRITE RELIABILITY RELATED REGISTER FIELDS ..............................................................................60 14.2 WRITE RELIABILITY SETTING ...........................................................................................................60

15 Enhanced Reliable Write (V4.41α or later) .....................................................................................61

15.1 RELIABLE WRITE RELATED COMMAND ............................................................................................63 15.2 RELIABLE WRITE RELATED REGISTER FIELDS ..................................................................................63 15.3 RELIABLE WRITE SECTOR COUNT ...................................................................................................63 15.4 ENHANCED RELIABLE WRITE ..........................................................................................................64

16 HS200 (SDR 200MHz) (V4.41α or later) ..........................................................................................65

16.1 HS200 RELATED REGISTER FIELDS ...................................................................................................65 16.2 HS200 TIMING MODE SELECTION .....................................................................................................66 16.3 HS200 RELATED COMMAND .............................................................................................................67

17 HS400 (DDR 200MHz) (V5.0) ...........................................................................................................68

17.1 HS400 RELATED REGISTER FIELDS ...................................................................................................68 17.2 HS400 TIMING MODE SELECTION .....................................................................................................69 17.3 HS400 SWITCH FUNCTION HANDLING SPECIFICATION ....................................................................70

18 Sanitize (V4.41α or later)...................................................................................................................72

18.1 SANITIZE RELATED REGISTER FIELDS ...............................................................................................72 19 Discard (V4.41α or later) ...................................................................................................................73

19.1 DISCARD RELATED COMMAND .........................................................................................................73 19.2 DISCARD RELATED REGISTER FIELDS ...............................................................................................73

20 Packed command (V4.41α or later) ..................................................................................................74

20.1 PACKED COMMAND HEADER ............................................................................................................75 20.2 PACKED RELATED COMMAND ..........................................................................................................76 20.3 PACKED INTERRUPTIBLE COMMANDS ...............................................................................................76 20.4 PACKED RELATED REGISTER FIELDS .................................................................................................77 20.5 PACKED COMMANDS ERROR HANDLING .........................................................................................78

21 Exception Events (V4.41α or later)...................................................................................................79

21.1 EXCEPTION EVENTS RELATED REGISTER FIELDS ..............................................................................79 22 Power Off notification (V4.41α or later) ..........................................................................................80

22.1 POWER OFF RELATED REGISTER FIELDS ...........................................................................................80 22.2 POWER OFF NOTIFICATION SETTING .................................................................................................81

23 Large sector size (V4.41α or later) ....................................................................................................82

23.1 LARGE SECTOR RELATED REGISTER FIELDS ......................................................................................82 23.2 DISABLING EMULATION MODE SETTING ...........................................................................................83

24 Boot Partition individual Write Protection .....................................................................................84

24.1 BOOT PARTITION WRITE PROTECTION RELATED REGISTER FIELDS ..................................................84 25 Data Tag(V4.5 or later) .....................................................................................................................85

25.1 DATA TAG RELATED COMMAND ......................................................................................................85


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25.2 DATA TAG RELATED REGISTER FIELDS .............................................................................................85 26 Dynamic Capacity(V4.5 or later) ......................................................................................................86

26.1 DYNAMIC CAPACITY RELATED COMMAND .......................................................................................86 26.2 DYNAMIC CAPACITY RELATED REGISTER FIELDS .............................................................................87

27 Context Management(V4.5 or later) ................................................................................................88

27.1 CONTEXT MANAGEMENT RELATED COMMAND ................................................................................88 27.2 CONTEXT MANAGEMENT RELATED REGISTER FIELDS ......................................................................88

28 Real Time Clock Info.(V4.5 or later) ................................................................................................89

28.1 REAL TIME CLOCK INFO RELATED COMMAND .................................................................................89 29 Device Health Report(V5.0) ..............................................................................................................89

29.1 DEVICE HEALTH REPORT RELATED COMMAND ................................................................................89 30 Secure Removal Type (V5.0) .............................................................................................................91

30.1 SECURE REMOVAL TYPE RELATED COMMAND .................................................................................91 31 Thermal Spec(V4.5 or later) .............................................................................................................92

31.1 THERMAL SPEC RELATED REGISTER FIELDS .....................................................................................92 32 Extended Partition Attribute(V4.5) ..................................................................................................93

32.1 EXTENDED PARTITION ATTRIBUTE RELATED REGISTER FIELDS .......................................................93 33 New register fields (V4.41α, V4.5 or V5.0) .......................................................................................94

33.1 EXTENDED CSD REGISTER ..............................................................................................................94 34 Unsupported register fields (V4.41α, V4.5 and V5.0) .....................................................................97

35 Remark on the value of [192]EXT_CSD_REV in EXT_CSD register ..........................................98

36 Remark on the value of [196]DEVICE_TYPE in EXT_CSD register ...........................................99

37 Remark on the potential bug of Linux e-MMC driver in data write operation (V4.41α or V4.5)

103

38 Recommended power-on sequence .................................................................................................109

39 Recommended sequence when power-down only VCC. .................................................................110

39.1 SLEEP/AWAKE RELATED COMMAND ..............................................................................................110 39.2 SLEEP/AWAKE RELATED REGISTER FIELDS.....................................................................................110 39.3 SLEEP/AWAKE SEQUENCE ..............................................................................................................111

40 Supported command set ..................................................................................................................112

40.1 BASIC COMMANDS (CLASS 0) .........................................................................................................112 40.2 READ RELATED COMMANDS (CLASS 2)..........................................................................................113 40.3 WRITE RELATED COMMANDS (CLASS 4) ........................................................................................113 40.4 ERASE RELATED COMMANDS (CLASS 5) ........................................................................................115 40.5 WRITE PROTECTION RELATED COMMANDS (CLASS 6) ...................................................................116 40.6 LOCK RELATED COMMANDS (CLASS 7) ..........................................................................................117

41 Product List ......................................................................................................................................118


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LIST OF TABLES

Table 1 : Table of Acronyms ............................................................................................ 10

Table 2 : The JEDEC Standard Comparison .................................................................... 12

Table 3 : Table of Capacitance Values ............................................................................. 14

Table 4 : Pin Assignment for 153 ball BGA package for V4.41α, V4.5 e-MMCTM

........ 16

Table 5 : Pin Assignment for 153 ball BGA package for V5.0 e-MMCTM

...................... 17


........ 18


...................... 19

Table 8 : GP_SIZE_MULT_GP0 – GP3 [154:143] of the Extended CSD ...................... 26

Table 9 : Partition Parameters ........................................................................................... 29

Table 10 : Auto Sleep Specification Comparison ............................................................. 34

Table 11: Production State Awareness related register fields .......................................... 40

Table 12: FFU related register fields ................................................................................ 43

Table 13: HPI commands.................................................................................................. 48

Table 14 : Interruptible commands ................................................................................... 48

Table 15: HPI related register fields ................................................................................. 49

Table 16: Background operation related register fields .................................................... 53

Table 17: HPI timing and post-process ............................................................................. 58

Table 18: Write Reliability related register fields............................................................. 60

Table 19: Reliable Write related command ...................................................................... 63

Table 20: Reliable Write related register fields ................................................................ 63

Table 21: Reliable Write Sector Count ............................................................................. 63

Table 22: HS200 related register fields ............................................................................ 65

Table 23: HS200 related command ................................................................................... 67

Table 24: HS400 related register fields ............................................................................ 68

Table 25: Sanitize related register fields ........................................................................... 72

Table 26: Discard related command ................................................................................. 73

Table 27: Discard related register fields ........................................................................... 73

Table 28: Packed command structure ............................................................................... 75

Table 29: Packed related command .................................................................................. 76

Table 30: CMD23 (packed) argument .............................................................................. 76

Table 31: Packed related register fields ............................................................................ 77

Table 32: Exception Events related register fields ........................................................... 79

Table 33: Power Off related register fields ....................................................................... 80

Table 34: Large sector related register fields .................................................................... 82

Table 35: Boot Partition Write Protection related register fields ..................................... 84

Table 36: Data Tag related command ............................................................................... 85

Table 37: Data Tag related register fields ......................................................................... 85

Table 38: Dynamic Capacity related command ................................................................ 86

Table 39: Dynamic Capacity related register fields .......................................................... 87

Table 40: Context Management related command ........................................................... 88

Table 41: Context Management related register fields ..................................................... 88

Table 42: Real Time Clock Info related command ........................................................... 89

Table 43: Device Health Report related command ........................................................... 89

Table 44: Secure Removal Type related command .......................................................... 91


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Table 45: Thermal Spec related register fields ................................................................. 92

Table 46: Extended Partition Attribute related register fields .......................................... 93

Table 47: New register fields in Extended CSD Register (V4.41α, V4.5 or V5.0) .......... 94

Table 48: Nonsupport register fields ................................................................................. 97

Table 49: EXT_CSD_REV [192] ..................................................................................... 98

Table 50: DEVICE_TYPE [196] ...................................................................................... 99

Table 51: Bus mode setting by Linux Kernel 3.0-3.9,3.0 and [196]DEVCE_TYPE ..... 100

Table 52: Power Supply Voltage and tPRU ................................................................... 109

Table 53: Sleep/Awake related command ...................................................................... 110

Table 54: Sleep/Awake related register fields ................................................................ 110

Table 55: Basic Commands (class 0) .............................................................................. 112

Table 56: Read Related Commands (class 2) ................................................................. 113

Table 57: Write Related Commands (class 4) ................................................................ 113

Table 58: Erase Related Commands (class 5)................................................................. 115

Table 59: Write protection Related Commands (class 6) ............................................... 116

Table 60: Lock Related Commands (class 7) ................................................................. 117

Table 61: TOSHIBA e-MMCTM

Product List ................................................................ 118

LIST OF FIGURES

Figure 1 : Composition of an e-MMCTM

system .............................................................. 14

Figure 2 : Block Diagram of V4.41α, V4.5 e-MMCTM

.................................................... 14

Figure 3 : Block Diagram of V5.0 e-MMCTM

.................................................................. 15

Figure 4 : Pin connection of BGA package 1 (153 balls) for V4.41α, V4.5 e-MMCTM

... 16

Figure 5 : Pin connection of BGA package 1 (153 balls) for V5.0 e-MMCTM

................. 17


... 18


................. 19

Figure 8 : Ver5.0 backward compatibility ........................................................................ 20

Figure 9 : Recommended Wiring for 19nm and A19nm e-MMCTM

to Host.................... 21

Figure 10: Recommended Wiring for 19nm and A19nm e-MMCTM

for VDDi pin ......... 22

Figure 11: Initial Memory Area Partitions........................................................................ 24

Figure 12: Flow Chart of Additional Partitions Configuration ......................................... 25

Figure 13: An Example of Partition Architecture ............................................................. 28

Figure 14: Boot Operation Process (V4.41α or later) ....................................................... 32

Figure 15: Alternative Boot Operation Process (V4.41α or later) .................................... 33

Figure 16: Auto Sleep Process .......................................................................................... 34

Figure 17: Cache On with Auto-BKOPS request exists ................................................... 35

Figure 18: Cache On without Auto-BKOPS request ........................................................ 35

Figure 19: Cache OFF ....................................................................................................... 36

Figure 20: Awake Process ................................................................................................ 37

Figure 21: Normal Erase Case .......................................................................................... 38

Figure 22: Secure Erase .................................................................................................... 38

Figure 23: Recommended Soldering Procedure ............................................................... 42

Figure 24: Field Firmware Update Procedure .................................................................. 45

Figure 25: Hardware reset operation - JEDEC standard - ................................................ 46


M1PCA00-0008

Figure 26: Hardware reset operation – Recommendation ................................................ 47

Figure 27: HPI pre-process ............................................................................................... 50

Figure 28: HPI process...................................................................................................... 51

Figure 29: HPI post-process.............................................................................................. 52

Figure 30: Background operation pre-process .................................................................. 55

Figure 31: Start & Stop Background operation ................................................................ 56

Figure 32: HPI & Background operation sequence .......................................................... 59

Figure 33: Write Reliability setting .................................................................................. 61

Figure 34: Enhanced Reliable Write ................................................................................. 64

Figure 35: HS200 selection flow diagram ........................................................................ 66

Figure 36: HS400 selection flow diagram ........................................................................ 69

Figure 37: HS400 Switch function specification for HS_TIMING .................................. 70

Figure 38: HS400 Switch function specification for BUS_WIDTH ................................ 71

Figure 39: Packed write command sequence .................................................................... 74

Figure 40: Packed read command sequence ..................................................................... 74

Figure 41: Determining the error during a packed command sequence ........................... 78

Figure 42: Power Off notification setting sequence for V4.5 and V5.0 ........................... 81

Figure 43: Large sector size setting sequence................................................................... 83

Figure 44: Power up sequence ........................................................................................ 109

Figure 45: Sleep/Awake sequence .................................................................................. 111


M1PCA00-0008

1 Introduction

1.1 Overview

TOSHIBA’s e-MMCTM

, which stands for embedded Multi Media Card, is one

of the embedded memory solutions which use non volatile NAND flash memory

devices for data storage and communication. It consists of NAND flash memory

devices and a controller in single Ball Grid Array (BGA) package with the Multi

Media Card interface. The applications of the e-MMCTM

cover a wide range of

mobile devices such as mobile phones, digital video cameras, and PNDs, as well

as other devices which need embedded memory devices inside. Features of the

e-MMCTM

are low cost, high performance, and low power consumption. Since it

has a specifically designed controller, it can be easily integrated into application

systems which have a MMC/HS-MMC interface.

TOSHIBA’s latest e-MMCTM

is based upon JEDEC e-MMCTM

standard version

5.0 (V5.0)

1.2 Definitions and Acronyms

Table 1 : Table of Acronyms

Acronyms Definition

e-MMC embedded Multi Media Card

HS-MMC High Speed Multi Media Card

BGA Ball Grid Array

SDR Single Data Rate

DDR Dual Data Rate

RPMB Replay Protected Memory Block

ECC Error Correction Code

CSD Card Specific Data register

EXT_CSD Extended Card Specific Data register

CMD Command line or Multi Media Card bus command

PND Portable Navigation Device or Personal Navigation Device

HPI High Priority Interrupt

BKOPS Background Operations


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2 JEDEC e-MMCTM

Standard

2.1 What Version are the TOSHIBA’s e-MMCTM

Devices Compliant To?

TOSHIBA’s e-MMCTM

devices are based upon the JEDEC e-MMCTM

standard.

Those developed using the 19nm process (19nm products) are based upon

V4.41α ,V4.5. Those developed using A19nm process (A19nm products) are

based upon V5.0.

2.2 The Differences between V4.41α,V4.5 and V5.0

The JEDEC e-MMCTM

standards have backward compatibility. Therefore, it is

possible to operate a V4.41α compliant device on a V4.4 or V4.41 compliant

system. Several functions such as HS200, Sanitize, Discard, Packed command,

Power off notification and Large sector size are added to V4.41α. Table 2

shows the JEDEC standard comparison between V4.41α,V4.5 and V5.0.


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Table 2 : The JEDEC Standard Comparison

JEDEC Ver.

(NAND Gen.)

V4.41α

(19nm)

V4.5

(19nm)

V5.0

(A19nm)

SDR/DDR I/F

SDR (200MHz)/

SDR (52MHz)/

DDR (52MHz)

SDR (200MHz)/

SDR (52MHz)/

DDR (52MHz)

SDR (200MHz)/

SDR (52MHz)/

DDR (52MHz)/

DDR (200MHz)

HW Reset Available Available Available

Partitioning

GP/

Enhanced User Data

GP/

Enhanced User Data

GP/

Enhanced User Data

N/A Extended Partition

Attribute Extended Partition

Attribute

Security

Erase + Sanitize

Trim + Sanitize

Secure Erase(*)

Secure TRIM Erase(*)

Erase + Sanitize

Trim + Sanitize

Secure Erase(*)


Erase + Sanitize

Trim + Sanitize

Secure Erase(*)


RPMB RPMB RPMB

High Priority

Interrupt Available Available Available

Background

Operation Available Available Available

Write Reliability Available Available Available

Enhanced Reliable

Write Available Available Available

Discard Available Available Available

Packed command Available Available Available

Data Tag N/A Available Available

Dynamic Capacity N/A Available Available

Context

Management N/A Available Available

Real Time Clock

info N/A Available Available

Thermal Spec. N/A Available Available

Boot Area

Protection Available Available Available

Power Off

Notification Available Available Available

Large Sector Size Available Available Available

e-MMCTM

Cache / 3 VDDi N/A Optional (e2-MMC) Optional (e2-MMC)

Production

State Awareness N/A N/A Available

Field

Firmware Update N/A N/A Available

Device

Health Report N/A N/A Available

Secure Removal

Type N/A N/A Available


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(*) Optional

3 e-MMCTM

System Architecture

3.1 Composition of an e-MMCTM

System

An e-MMCTM

system generally consists of a host controller, an e-MMCTM

, and

a HS-MMC driver, which is software which controls the e-MMCTM

.

1. The host controller has a host CPU and a HS-MMC interface. The e-

MMCTM

also has a HS-MMC interface.

2. The e-MMCTM

consists of raw NAND flash memory and a controller. The

controller has a HS-MMC interface which can be connected to the host

controller. It also has a NAND interface which is connected to the raw

NAND flash memory. It has several functions such as Bad Block

Management, Wear Leveling and Error Correction Code (ECC), to utilize

the raw NAND flash memory efficiently.

3. The HS-MMC driver handles operations between the host controller and the

e-MMCTM

.

4. TOSHIBA recommends that the start address is aligned to 4KB(A19/19nm

e-MMC) so that the maximum performance is derived.

Figure 1 shows the composition of an e-MMCTM

system.


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Figure 1 : Composition of an e-MMCTM

system

3.2 Block Diagram of the e-MMCTM

System

As mentioned above, the e-MMCTM

consists of raw NAND chip(s) and a

controller, which are put in a standard Ball Grid Array (BGA) package.

The following pictures show the block diagram of the e-MMCTM

. Figure 2 for

V4.41α, V4.5 and Figure 3 for and V5.0.

Specification of CREG and recommended values of CVCC, and CVCCQ in the

figures are as follows.

Table 3 : Table of Capacitance Values

Parameter Symbol Unit Min. Typ. Max. Remark

VDDi capacitor value CREG

μF 0.10 - 2.2* Except HS400

μF 1.00 - 2.2* HS400

VCC capacitor value CVCC μF - 2.2 + 0.1 -

VCCQ capacitor value CVCCQ μF - 2.2 + 0.1 -

* TOSHIBA recommends that the minimum value should be applied as the

value of CREG. CREG shall be compliant with X5R/X7R of the EIA standard or B

of the JIS standard.

Figure 2 : Block Diagram of V4.41α, V4.5 e-MMCTM

VccQ(1.8V/3.3V)

Vcc(3.3V)

MMC I/F(1.8V/3.3V)

Package

MM

C I/

O B

LO

CK

CREG

NA

ND

I/O

BLO

CK

x10

REGULATOR

CORE LOGIC

VDDi

CVCC

CVCCQ

NAND

NAND I/O

NAND

Control signal


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Figure 3 : Block Diagram of V5.0 e-MMCTM

3.3 Pin connection of the BGA package

The BGA package has 153 balls and 169 balls. The ball layout and the pins

assignment are based upon the JEDEC e-MMCTM

standard.

Figure 4, 5, 6 and 7 show the pin connections of the BGA packages. For Ver5.0

backward compatibility, please refer to Figure 8.


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Pin

Number Name

Pin

Number Name

Pin

Number Name

Pin

Number Name

A3 DAT0 C2 VDDi J10 Vcc N4 VccQ

A4 DAT1 C4 VssQ K5 RST_n N5 VssQ

A5 DAT2 C6 VccQ K8 Vss P3 VccQ

B2 DAT3 E6 Vcc K9 Vcc P4 VssQ

B3 DAT4 E7 Vss M4 VccQ P5 VccQ

B4 DAT5 F5 Vcc M5 CMD P6 VssQ

B5 DAT6 G5 Vss M6 CLK B6 DAT7 H10 Vss N2 VssQ


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Pin

Number Name

Pin

Number Name

Pin

Number Name

Pin

Number Name

A3 DAT0 C2 VDDi J5 Vss N4 VccQ

A4 DAT1 C4 VssQ J10 Vcc N5 VssQ

A5 DAT2 C6 VccQ K5 RST_n P3 VccQ

A6 Vss E6 Vcc K8 Vss P4 VssQ

B2 DAT3 E7 Vss K9 Vcc P5 VccQ

B3 DAT4 F5 Vcc M4 VccQ P6 VssQ

B4 DAT5 G5 Vss M5 CMD

B5 DAT6 H5 DS M6 CLK

B6 DAT7 H10 Vss N2 VssQ


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Pin

Number Name

Pin

Number Name

Pin

Number Name

Pin

Number Name

H3 DAT0 K2 VDDi T10 Vcc Y4 VccQ

H4 DAT1 K4 VssQ U5 RST_n Y5 VssQ

H5 DAT2 K6 VccQ U8 Vss AA3 VccQ

J2 DAT3 M6 Vcc U9 Vcc AA4 VssQ

J3 DAT4 M7 Vss W4 VccQ AA5 VccQ

J4 DAT5 N5 Vcc W5 CMD AA6 VssQ

J5 DAT6 P5 Vss W6 CLK J6 DAT7 R10 Vss Y2 VssQ


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Pin

Number Name

Pin

Number Name

Pin

Number Name

Pin

Number Name

H3 DAT0 K2 VDDi T5 Vss Y4 VccQ

H4 DAT1 K4 VssQ T10 Vcc Y5 VssQ

H5 DAT2 K6 VccQ U5 RST_n AA3 VccQ

H6 Vss M6 Vcc U8 Vss AA4 VssQ

J2 DAT3 M7 Vss U9 Vcc AA5 VccQ

J3 DAT4 N5 Vcc W4 VccQ AA6 VssQ

J4 DAT5 P5 Vss W5 CMD J5 DAT6 R5 DS W6 CLK J6 DAT7 R10 Vss Y2 VssQ

NC: No Connect, can be connected to ground or left floating.

RFU: Reserved for Future Use, should be left floating for future use.

VSF: Vendor Specific Function should be left floating. Toshiba may use these

for debug/test etc.


M1PCA00-0008

Figure 8 : Ver5.0 backward compatibility

(1) Another VSS pin in e-MMC should be connected to GND.

(2) Case of 19nm e-MMC of TOSHIBA, VSF4 is floating inside.

Please set state of DS-line following to the specification of the host. (3)

According to the JEDEC Standard Ver4.5, VSF4, VSF5 and RFU should be floating.

However, case of 19nm e-MMC of TOSHIBA, VSF4, VSF5 and RFU can be connected to Vss.

3.4 NC Pins and RFU Treatment

Regarding TOSHIBA’s 19nm and A19nm e-MMCTM

, the NC pins are set to Hi-

Z and basically there should be no problem even if these pins are connected to

GND or other signal line. (In case of connecting to a signal line, an increase in

capacitance has to be considered.) TOSHIBA recommends that the NC pins be

connected to GND.

For the RFU pins, TOSHIBA recommends that it shall be left floating for future

use.


M1PCA00-0008

3.5 Recommended Wiring: Host bus

Figure 9 shows the recommended wiring for the Host bus.

Figure 9 : Recommended Wiring for 19nm and A19nm e-MMCTM

to Host

*1 : Please refer to JESD84-B50, Table 179 - Capacitance, about recommended values of

resistances.

*2 : RST_n might be NC or connected to GND when it is not used. DAT4 - DAT7 should

be NC in 4 bit mode.

*3 : Please refer to next section for VDDi treatment.

*4 : DS should be left floating in case of not using HS400.

e - MMCTM

DAT0 ~ DAT7

VDDi *3 VssQ

Vcc

Vss

RST_n *2

CMD

CLK

VccQ

1.8V or 3.3V 3.3V

HOST

CLK

CMD

RST_n (or GPIO)

DAT0 ~ DAT7

NC NC or GND

R CMD *1 R DAT *1

1.8V or 3.3V 1.8V or 3.3V

2.2uF 0.1uF 2.2uF 0.1uF

1.8V or 3.3V

R RST

*1

DS R DS *1

*4


M1PCA00-0008

3.6 Recommended Wiring : VDDi

TOSHIBA recommends making the wiring traces pass between balls, especially

for communication lines to the host such as CLK, CMD, and DAT0-7. If the

wiring passes through the NC pins, the waveform quality may deteriorate since

parasitic impedance is added to the wiring.

The VDDi pin is very sensitive to the increase of impedance because it is the pin

to connect the bypass condenser for regulation of the internal regulator.

Therefore, wiring for the VDDi pin should not pass through NC pins and should

be as short as possible.

Figure10 shows the recommended wiring for the VDDi pin.

Figure 10: Recommended Wiring for 19nm and A19nm e-MMCTM

for VDDi pin

3.7 Recommended Wiring: RST_n

Specifications of the hardware reset timings are defined in the datasheet of each

product. TOSHIBA recommends that pull-up resistor RRST be connected if the

host connects RST_n line to a GPIO pin and there is the possibility that the

RST_n line floats when the host goes into a sleep state or some other mode.

TOSHIBA recommends the value for RRST be the same as RDAT and RCMD.

3.8 Differences in the Pin Assignment of the JEDEC versions

RST_n: Reset. If the hardware reset function in Ext-CSD is configured as

“Disable”, it can be treated as NC. The Ext-CSD configuration at the time of

shipping is “Disable”.

RFU: Reserved for Future Use. These pins are not planned to be used at this

time and can be treated as NC.


M1PCA00-0008

4 Additional Partitions Configuration (V4.41α or later)

TOSHIBA’s e-MMCTM

version V4.41α or later has additional partitioning

features so that users can configure the memory area of the device according to

their usage. This chapter provides information on how to configure the partitions

of the memory area of the device.

4.1 Initial Partition Architecture

At the time of shipment of the device, the memory area consists of the following

four partitions: a User Data Area Partition, two Boot Area Partitions, and a

Replay Protected Memory Block (RPMB) Area Partition.

1. User Data Area Partition

2. Boot Area Partition 1

3. Boot Area Partition 2

4. RPMB Area Partition

The User Data Area Partition is used to store users’ data. The size of the User

Data Area can be determined from the CSD register bits [73:62] (C_SIZE) when

the density of the device is up to 2GB, or from the Extended CSD register bits

[215:212] (SEC_COUNT) when the density of the device is over 2GB.

Up to 2GB devices:

User Data Area Partition size

= (C_SIZE+1) x 2(C_SIZE_MULT+2) x 2(READ_BL_LEN)

where:

C_SIZE_MULT < 8,

READ_BL_LEN < 12.

The C_SIZE_MULT is indicated in CSD register bits [49:47], and the

READ_BL_LEN is also indicated in CSD register bits [83:80], both of which

are read-only information.

Over 2GB devices:

User Data Area Partition size = 512B x SEC_COUNT

The Boot Area Partitions store important information or the program for booting.

The size of each Boot Area Partition is a multiple of 128kB; the multiple is

defined by Extended CSD register byte [226] (BOOT_SIZE_MULT), which is

read-only information.

Boot Area Partition size = 128kB x BOOT_SIZE_MULT


M1PCA00-0008

Finally, the RPMB Area Partition is provided to store secret data so as not to be

replayed by an unauthenticated person. The size of the RPMB Partition is a

multiple of 128kB; the multiple is defined by Extended CSD register byte [168]

(RPMB_SIZE_MULT), which is also read-only information.

RPMB Area Partition size = 128kB x RPMB_SIZE_MULT

Figure 11 shows a diagram of the initial memory area of the device. Please note

that the size of each area partition in Figure11 is not proportional to the actual

area size.

Figure 11: Initial Memory Area Partitions

4.2 Additional Partitions Configuration

In addition to the initial memory area partitions, up to four General Purpose

Area Partitions and an Enhanced User Data Area segment in the User Data Area

Partition can be arranged by the host according to its usage in e-MMCTM V4.41α

or later. Moreover, the host may add enhanced technological features to these

areas. These configurations can be executed by issuing CMD6 (SWITCH).

The basic procedure for partitions configuration by the host is as follows:


M1PCA00-0008

1. Confirm if the device supports the partitioning feature.

2. Confirm if the device supports the enhanced technological features.

3. Configure sizes and attributes of the General Purpose Area Partitions.

4. Configure start address, size, and attributes of the Enhanced User Data

Area.

5. Notify the device that the configuration is completed.

6. Execute a power cycle.

Figure 12 shows a flow chart of the additional partitions configuration.

Figure 12: Flow Chart of Additional Partitions Configuration

The following are explanations of the steps shown above.


M1PCA00-0008

4.2.1 Confirmation of Supporting the Partitioning Feature

Before starting the configuration of the additional partitions, the host is

recommended to confirm if the device supports the partitioning feature. If Bit 0

(PARTITIONING_EN) of PARTITIONING_SUPPORT field [160] in the

Properties segment of Extended CSD register is 0x1, the device supports the

partitioning feature, and the host can proceed to the next step. Otherwise, the

device may not support the partitioning feature and the additional partitions may

not be configured.

4.2.2 Confirmation of Supporting the Enhanced Technological Features

If the host wants to add the enhanced technological features to the additional

partitions, their capability had better to be confirmed previously. If Bit 1

(ENH_ATTRIBUTE_EN) of the PARTITIONING_SUPPORT field [160] is

0x1, the device supports the enhanced technological features, and the host can

add them to the additional partitions. Otherwise, they do not have the enhanced

technological features, though the General Purpose Area Partitions still can be

configured by the host.

4.2.3 Configuration of the General Purpose Area Partitions

The size of the General Purpose Area Partitions can be configured as a multiple

of the High Capacity Write Protect Group size, whose coefficient is defined by

GP_SIZE_MULT_GP0 – GP3 [154:143] of the Extended CSD register,

respectively.

General Purpose Area Partition X size

= High Capacity Write Protect Group size x (GP_SIZE_MULT_X_2 x 216

+ GP_SIZE_MULT_X_1 x 28 + GP_SIZE_MULT_X_0 x 2

0)

where

High Capacity Write Protect Group size

= (512kB x HC_WP_GRP_SIZE x HC_ERASE_GRP_SIZE),

Bit 0 of ERASE_GROUP_DEF [175] = 0x1,

GP_SIZE_MULT_X_Y is a byte of the GP_SIZE_MULT,

X is a number of the General Purpose Area to be configured,

Y is a factor of the formula shown above.

Each GP_SIZE_MULT_X_Y is shown in shown below.

Table 8 : GP_SIZE_MULT_GP0 – GP3 [154:143] of the Extended CSD

216 28 20

General Purpose Area 1 GP_SIZE_MULT_1_2[145] GP_SIZE_MULT_1_1[144] GP_SIZE_MULT_1_0[143]





M1PCA00-0008

Additionally, the enhanced attribute can be configured for each General Purpose

Area Partition by setting Bit 1 - 4 (ENH_1 – ENH_4) of

PARTITIONS_ATTRIBUTE [156] of the Extended CSD register to 0x1.

General Purpose Area Partition 1:

Bit 1 (ENH_1) = 0x0: Default

Bit 1 (ENH_1) = 0x1: set enhanced attribute










4.2.4 Configuration of the Enhanced User Data Area

The start address of the Enhanced User Data Area segment in the User Data

Area Partition can be defined by ENH_START_ADDR [139:136] in the Modes

segment of the Extended CSD register. The address should be aligned with the

Write Protect Group and LSBs below the write protect group size in the

configured value will be ignored. The address space of the Enhanced User Data

Area will be continuous with the rest of the User Data Area Partition.

Second, the size of the Enhanced User Data Area can be defined by

ENH_SIZE_MULT [142:140] in the Modes segment of the Extended CSD

register in terms of High Capacity Write Protect Groups as follows:

Enhanced User Data Area size

= High Capacity Write Protect Group size x (ENH_SIZE_MULT_2 x 216

+

ENH_SIZE_MULT_1 x 28 + ENH_SIZE_MULT_0 x 2

0)

where:



Bit 0 of ERASE_GROUP_DEF [175] = 0x1.

Finally, the enhanced attribute can be configured for the Enhanced User Data

Area by setting Bit 0 (ENH_USR) of PARTITIONS_ATTRIBUTE [156] of the

Extended CSD register to 0x1.


M1PCA00-0008

4.2.5 Notification of the Completion of the Configuration

After all configurations are completed, in order to notify the device of the

completion of the configuration, Bit 0 of

PARTITIONING_SETTING_COMPLETED of the Extended CSD register

must be set to 0x1 by the host. If this bit remains 0x0, which is the default, the

former configuration set by the host may be reset after the next power cycle.

Actually, this register is prepared to prevent trouble in case of a sudden power

loss during the configuration, so that the host can properly start the

configuration again afterward.

The host can confirm if the configuration parameters are correctly set by issuing

CMD13.

4.2.6 Execution of a Power Cycle

Even after the completion of the configuration by the host, the setting values

will not be reflected in the device immediately. The device can configure itself

according to the values in the Extended CSD register set by the host only after a

power cycle.

The host can check the User Data Area size containing the Enhanced User Data

Area size by referring to C_SIZE or SEC_COUNT in the same manner as

described in section 2.

4.3 An Example of Partition Architecture

Figure 13 shows an example of the partition architecture after partition

configuration by the host. Please note that the size of each partition in Figure 13

is not proportional to the actual area size.

Figure 13: An Example of Partition Architecture


M1PCA00-0008

4.4 Points to Consider

- Before configuring partition parameters

The granularity of the General Purpose Partitions and of the Enhanced User

Data Area is in units of the High Capacity Write Protect Group Sizes. When the

partition parameters are configured, ERASE_GROUP_ DEF bit in the Extended

CSD shall be set to indicate that the High Capacity Erase Group Sizes and High

Capacity Write Protect Group Sizes are to be used. If the partition parameters

are sent to a device by CMD6 before setting ERASE_GROUP_DEF bit, the

slave shows SWITCH_ERROR. Table 9 shows the partition parameters.

Table 9 : Partition Parameters

Register Position Cell Type

EXT_CSD [167] WR_REL_SET R/W

EXT_CSD [156] PARTITIONS_ATTRIBUTE R/W

EXT_CSD [155] PARTITIONS_SETTING_COMPLETED R/W

EXT_CSD [154:143] GP_SIZE_MULT R/W

EXT_CSD [142:140] ENH_SIZE_MULT R/W

EXT_CSD [139:136] ENH_START_ADDR R/W

R/W: One time programmable and Readable (multiple times)

- Sizes and Attributes are One Time Programmable

The sizes and attributes of the General Purpose Area Partitions and the

Enhanced User Data Area can be configured by the host only once during the

lifetime of the device and are referred to as One Time Programmable (OTP).

- Previously Stored Data May Be Erased

If there is previously stored data in the memory area, it may be erased after the

partitions configuration by the host.

- Device Initialization Time May Extend

The partitions configuration may extend the following initialization time.

Especially in the first power cycle after the configuration, it will take a

considerable time for the internal controller to implement the new configuration

set by the host.

- Command Restrictions

Commands which can be issued by the host to each partition are:

General Purpose Area Partition - Command classes 0, 2, 4, 5 and 6.

Enhanced User Data Area – Same as the User Data Area partition


M1PCA00-0008

- Max Enhanced Area Size

The maximum area size that can be configured as an enhanced area by the host

is defined by MAX_ENH_SIZE_MULT [159:157] in the Modes segment of the

Extended CSD register in terms of High Capacity Write Protect Groups as

follows:

Max Enhanced Area size

= High Capacity Write Protect Group size x (MAX_ENH_SIZE_MULT_2 x 216

+ MAX_ENH_SIZE_MULT_1 x 28 + MAX_ENH_SIZE_MULT_0 x 2

0)

≧

4

1i

size) i)Partition( Area Purpose General (Enhanced

+ Enhanced User Data Area size

where:



Bit 0 of ERASE_GROUP_DEF [175] = 0x1.


M1PCA00-0008

5 Boot Process for e-MMCTM

(V4.41α or later)

5.1 Select Boot Partition

The host can choose the partition from which boot data is read out by

configuring BOOT_PARTITION_ENABLE, bits [5:3] in the extended CSD

register [179]. The default value of the register is 0x0, which means the device is

not boot enabled.

BOOT_PARTITION_ENABLE: Bits [5:3] of PARTITION_CONFIG [179]

0x0: Device not enabled for boot (default)

0x1: Boot Area Partition 1 enabled for boot

0x2: Boot Area Partition 2 enabled for boot

0x3 – 0x6: Reserved

0x7: User area enabled for boot

5.2 Select Boot Acknowledgement

The host can also choose to a receive boot acknowledge signal from the device

by configuring BOOT_ACK, bit [6] in the extended CSD register [179].

BOOT_ACK: Bit [6] of PARTITION_CONFIG [179]

0x0: No boot acknowledge sent (default)

0x1: Boot acknowledge sent during boot operation

If BOOT_ACK is set to 0x1, the device will send the boot acknowledge pattern

“010” to the host within 50ms after the CMD line goes LOW.

5.3 Enable Hardware Reset Operation

Before executing the hardware reset operation, the host may need to configure

RESET_n_FUNCTION [162] in the extended CSD register to make the

hardware reset function valid. The default value of the RESET_n_FUNCTION

is 0x0 (RST_n signal is temporarily disabled).

RESET_n_FUNCTION = 0x0: temporarily disabled (default)

RESET_n_FUNCTION = 0x1: permanently enabled

RESET_n_FUNCTION = 0x2: permanently disabled

Please note that the RESET_n_ FUNCTION is one time programmable (OTP)

for the lifetime of the device.


M1PCA00-0008

5.4 Boot Operation

The boot process will begin if the CMD line is kept LOW for more than 74

clocks after power on or hardware (H/W) reset operation or issuing CMD0 with

argument 0xF0F0F0F0. Then, the device recognizes that the boot mode is

started and begins to prepare boot data. The device will start to send the boot

data to the host within one second after the CMD line goes LOW. The host

should keep the CMD line LOW until it receives all the boot data from the

device. Figure 14 shows the boot operation process.

Figure 14: Boot Operation Process (V4.41α or later)

Power OnH/W Reset

Device Host

CMD0 with

argument

0xF0F0F0F0

CMD line = LOW

For more than 74clocks

Recognize boot mode

Send boot data to host

Keep CMD line = LOW

Boot data

Receive boot data

from device

Ready to accept CMD1 Send CMD1

End of boot operation

CMD1

“010”Send boot

acknowledge to host

Boot operation

Power OnH/W Reset

Device Host

CMD0 with

argument

0xF0F0F0F0

CMD line = LOW

For more than 74clocks

Recognize boot mode


Keep CMD line = LOW

Boot data

Receive boot data

from device



CMD1

“010”Send boot

acknowledge to host

Boot operation


M1PCA00-0008

5.5 Alternative Boot Operation

Alternatively, the boot process can be started by issuing CMD0 with argument

0xFFFFFFFA, after 74 clock cycles from power on or the H/W reset operation

or issuing CMD0 with argument 0xF0F0F0F0. Then, the device recognizes that

the boot mode is started and begins to prepare boot data. The device will start to

send the boot data to the host within one second after issuing CMD0 with

argument 0xFFFFFFFA. The host should keep the CMD line LOW until it

receives all the boot data from the device.

Figure 15: Alternative Boot Operation Process (V4.41α or later)

Power OnH/W Reset

Device Host

CMD0 with

argument

0xF0F0F0F0

more than 74clocks

Recognize boot mode


Keep CMD line = LOW

Boot data

Receive boot data

from device



CMD1

Send CMD0 with

argument 0xFFFFFFA

Boot operation

“010”Send boot

acknowledge to host

Power OnH/W Reset

Device Host

CMD0 with

argument

0xF0F0F0F0

more than 74clocks

Recognize boot mode


Keep CMD line = LOW

Boot data

Receive boot data

from device



CMD1

Send CMD0 with

argument 0xFFFFFFA

Boot operation

“010”Send boot

acknowledge to host


M1PCA00-0008

6 Auto Sleep Optimization

6.1 Auto Sleep function

Auto Sleep is a function which makes the e-MMCTM

automatically enter into the

low power consumption mode (Auto Sleep mode) when there is no command

for a certain period. The period until the e-MMCTM

shifts into the Auto Sleep

mode since the last command occurred is defined as auto sleep shift time (TA).

6.2 Auto Sleep specification comparison

Figure 16 shows a general diagram of the Auto Sleep process. Definitions of the

symbols are as follows:

TA: the Auto Sleep shift time: time until the device enters the Auto Sleep mode

since the last command

TC: awaking time: time which the device takes to wake up from the Auto Sleep

mode

Table 10 shows the Auto Sleep specification comparison between product types.

Figure 16: Auto Sleep Process

Table 10 : Auto Sleep Specification Comparison

Product type Auto Sleep shift time (TA) Awake time (TC)

V4.41α(19nm) 100msec 1.3ms

V4.5(19nm) 100msec 1.3ms

V5.0(A19nm) 10msec 1.3ms

Awake W/R Standby Awake W/R Standby

TA TC

Time

Power On On On On On On On On OnCLK On On On On OFF On On On On

Auto Sleep

Curr

ent


M1PCA00-0008

6.3 Auto-BKOPS and Auto Sleep

Auto-BKOPS is valid only if Cache ON and Auto-BKOPS request exists. Auto-

BKOPS will be carried out in Transfer State. Data in cache will be flushed to

NAND automatically before goes into Auto Sleep. Auto-BKOPS request is a

flag that controlled by e-MMC controller internally. Please refer figures below

for details.

Case 1: Cache ON with Auto-BKOPS request exists

Below three items will be executed after 10ms from ready.

System Write, Auto Flush (equivalent value for one interleave), Garbage

Collection (Data amount processed by the Garbage Collection is one physical

block). Device goes into auto sleep mode after “10ms + Auto-BKOPS process

time + 10ms”.

Figure 17: Cache On with Auto-BKOPS request exists

Case 2: Cache ON and without Auto-BKOPS request

Auto-BKOPS will not executed due to request does not exist. After busy is

released, device goes into Auto Sleep after 10ms.

Figure 18: Cache On without Auto-BKOPS request


M1PCA00-0008

Case 3: Cache OFF

Auto-BKOPS will not be executed in all the cases due to Cache OFF. Device

goes into Auto Sleep after 10ms from ready.

Figure 19: Cache OFF

6.4 Point to Notice regarding Auto Sleep

In case the device enters the Auto Sleep mode frequently, performance of the

device may decline, especially for Single Block Read.

6.5 Further reduce current consumption

If the host can stop CLK, the current consumption is reduced more. Host can

stop CLK at standby or Auto Sleep without any side effect.

TOSHIBA recommends the following awake procedure. Host shall supply the

CLK stable before issuing the Command.

Figure 20 shows the TOSHIBA’s requirements and recommendations.


M1PCA00-0008

Figure 20: Awake Process


M1PCA00-0008

7 Secure Erase Operation (V4.41α or later)

TOSHIBA’s e-MMCTM

V4.41α or later (V4.5 – obsolete) has the Secure Erase

function in addition to the normal Erase function in order to securely erase data.

When the normal Erase command e data in the target erase block will be erased.

However, copies of the data of the target erase block may still exist in the

original data block, which is different from the target erase block. On the other

hand, when the Secure Erase command is executed, not only is the data of the

target block erased, but also any corresponding data copies will also be erased.

Therefore, the data of the target erase block will be totally erased from any

physical NAND memory cells in the device.

The Secure Erase function allows the device to perform high security operations.

However, please note that once the Secure Erase command is executed, it will

be impossible to recover the original data.

Figure 21: Normal Erase Case Figure 22: Secure Erase

Block A Block B

Secure Erase

Block ACopy

Block B

Block A Block B

Erase

Block ACopy

Block BBlock ACopy

Block B

1.Copy Block A to Block B

2.Erase Block B


2.Secure Erase Block B

The data in

the Block A

may remain.

The data in

the Block A

will be also

erased.

Block A Block B

Secure Erase

Block A Block B

Secure Erase

Block ACopy

Block BBlock ACopy

Block B

Block A Block B

Erase

Block A Block B

Erase

Block ACopy

Block BBlock ACopy

Block B


2.Erase Block B


2.Secure Erase Block B

The data in

the Block A

may remain.

The data in

the Block A

will be also

erased.


M1PCA00-0008

8 Production State Awareness (V5.0)

TOSHIBA’s e-MMCTM

V5.0 has the product state awareness function that

informs e-MMC if it is before or after soldering. Production State Awareness

feature have to be used when loading data before soldering.

Pre loading data size (PRE_LOADING_DATA_SIZE [25:22]) has to be set to

the same sector size as the actual pre-loading data size.

Pre loading data size = PRE_LOADING_DATA_SIZE x Sector Size

Pre-loading data size should be multiple of 4KB and the pre-loading data should

be written by multiple of 4KB chunk size, aligned 4KB address. This is because

the valid data size will be treated as 4KB when host writes data less than 4KB.

Pre-loading data size is limited to MAX_PRE_LOADING_DATA_SIZE[21-18]

regardless of using Production State Awareness function.

MAX_PRE_LOADING_DATA_SIZE[21-18] value will change when host sets

Enhanced User area Partition.

If the host continues to write data in Normal state (after it wrote

PRE_LOADING_DATA_SIZE amount of data) and before soldering, the pre-

loading data might be corrupted after soldering.

If a power cycle is occurred during the data transfer, the amount of data written

to device is not clear. Therefore in this case, host should erase the entire pre-

loaded data and set again PRE_LOADING_DATA_SIZE[25:22],

PRODUCTION_STATE_AWARENESS[133], and

PRODUCT_STATE_AWARENESS_ENABLEMENT[17].


M1PCA00-0008

8.1 Production State Awareness related register fields

Table 11: Production State Awareness related register fields

Register Position Cell Type Explanation Default

Value

EXT_CSD

[133]

PRODUCTION_STATE_AWARENESS

R/W/E

0x00: This value

represents a state in

which the device is the

field and the device

uses regular operations.

0x01: This value


which the device is in

production prior

soldering and before the

host loaded content to

the device. The host sets

the device to this state

for loading the content

to the device.

0x02: This value


which the device is in

production and the host

completed to load the

content to the device.

The host sets the device

to this state after content

was loaded and just

before soldering. Once

transferred to this state

the host should not write

content to the device.

0x03: This value should

be set by the host if auto

pre-soldering data is

desired. If the data is

transferred as much as

PRE_LOADING_DAT

A_SIZE, then the device

state is changed back to

normal state by changing

the value of

PRODUCTION_STAT

A_AWARENESS to

0x0 (Normal)

automatically.

0x00


M1PCA00-0008

EXT_CSD

[218]

PRODUCTION_STATE_AWARENESS_TI

MEOUT

R

The maximum timeout

for the SWITCH

command (CMD6) when

setting a value to the

PRODUCTION_STATE

_AWARENESS.

0x0A

EXT_CSD [25-22] PRE_LOADING_DATA_SIZE R/W/E_P

This field is used to set

the size of the contents

to be loaded on to the

device during pre-

loading.

0x007

58000

EXT_CSD [21-18]

MAX_PRE_LOADING_DATA_SIZE R

The maximum data size

that can be loaded to the

device. This value shall

be set by the device

vendor.

0x007

58000

EXT_CSD

[17]

PRODUCT_STATE_AWARENESS_ENABL

EMENT

R &

R/W/E

[bit 0:3]CAPABILITIES

0x0: Manual mode is

supported

0x1: Auto mode is

supported

[bit 5:4]ENABLEMENT

[bit:5] Mode

0x0: Manual mode is

enabled.

0x1: Auto mode is

enabled.

[bit:4] Production State

Awareness enable

0x0: Production State

Awareness is disabled.

0x1: Production State

Awareness is enabled.

Bit 4 could be set to ‘1’

only once

0x03

R: Read only.

R/W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any

CMD0 reset and readable.

©2014 TOSHIBA CORPORATION CONFIDENTIAL Page 40 of 116

M1PCA00-0008

8.2 Recommended Soldering Procedure

Figure 23: Recommended Soldering Procedure


M1PCA00-0008

9 Field Firmware Update (FFU) (V5.0)

Field Firmware Updates (FFU) enables features enhancement in the field. Using

this mechanism the host downloads a new version of the firmware to the

e-MMC device and following a successful download, instructs the e-MMC

device to install the new downloaded firmware into the device.

Toshiba will support only MODE_OPERATION_CODES.

9.1 FFU related register fields

Table 12: FFU related register fields

Register Position Cell

Type Explanation

Default

Value

EXT_CSD [493] SUPPORTED_MODES R

[bit:0] FFU

0x0: FFU is not supported

0x1: FFU is supported.

[bit:1] VSM (Vendor Specific Mode)

0x0: VSM is not supported

0x1 : VSM is supported

0x01

EXT_CSD [30]MODE_CONFIG R/W/E_P

0x00: Normal mode (default)

0x01: FFU mode

0x10: Vendor Specific Mode

Others: Reserved

0x00

EXT_CSD [29]MODE_OPERATION_CODES W/E_P

0x00: Reserved

0x01: FFU_INSTALL

0x02: FFU_ABORT

Others: Reserved

0x00

EXT_CSD [492] FFU_FEATURES R

[bit:0]

SUPPORTED_MODE_OPERATION_CODES

0x0: Does not support

MODE_OPERATION_CODES field

0x1: Support MODE_OPERATION_CODES

field

0x00

EXT_CSD [169] FW_CONFIG R/W

[bit:0] UPDATE_DISABLE

0x0: FW updates enabled.

0x1: FW updates disabled permanently

0x00

EXT_CSD [490:487] FFU_ARG R

Using this field the device reports to the host

which value the host should set as an argument

for the read and write commands in FFU mode.

0xFFF

FFFFF


M1PCA00-0008

EXT_CSD

[491]

OPERATION_CODES_TIMEOUT

R

Indicates the maximum timeout for the

SWITCH command (CMD6) when setting a

value to the MODE_OPERATION_CODES

field.

0x00

EXT_CSD [26]FFU_STATUS R

Using this field the device reports the status of

the FFU process.

0x00: Success

0x01- 0xF: Reserved

0x10: General error

0x11: Firmware install error

0x12: Error in downloading firmware

Others: Reserved

0x00

EXT_CSD

[305-:302]

NUMBER_OF_FW_SECTORS

_CORRECTLY_PROGRAMMED

R

Using this field the device reports the number

of sectors, from the firmware bundles, which

were programmed correctly into the device.

The value is in terms of 512 Bytes or in

multiple of eight 512Bytes sectors (4KBytes)

depending on the value of the

DATA_SECTOR_SIZE field.

0x00

EXT_CSD [261:254] FIRMWARE_VERSION R

This field provides the device firmware version

0xXX


M1PCA00-0008

9.2 Field Firmware Update Sequence

Figure 24: Field Firmware Update Procedure


M1PCA00-0008

10 Hardware reset (V4.41α or later)

TOSHIBA’s e-MMCTM

V4.41α or later has the hardware reset function that

moves the device from any state to Pre-idle state by controlling the RST_n pin.

10.1 Definition in JEDEC standard

Figure 25 shows the hardware reset operation from the JEDEC specification.

Figure 25: Hardware reset operation - JEDEC standard -

The JEDEC standard specifies that the host shall wait tRSCA (min 200us) and

supply 74 clocks between asserting the RST_n (Rising Edge) and issuing the

initialize command.

But it’s unclear when the host should supply clocks during the hardware reset

operation and which command should be issued for the next initiation.


M1PCA00-0008

10.2 Initialization Recommendation

TOSHIBA recommends the following initialization procedure and the period of

supplied clocks relevant to the hardware reset operation in addition to the

JEDEC standard.

Figure 26 shows the TOSHIBA’s requirements and recommendations.

Figure 26: Hardware reset operation – Recommendation

CLK

RST_n

CMD

CLK

RST_n

CMD

tRSTH

Min 1us

Min 10 cycles of clock are required between asserting RST_n (Rising edge) and putting it low.

Min 10 clocks

tRSTH

tRSCA

Min 74 cycles of clock are required before issuing CMD1, CMD0 with argument 0xFFFFFFA

or boot process by keeping CMD line low.

Host can issue CMD1, CMD0 with

argument 0xFFFFFFA or boot

process by keeping CMD line low.

tRSCA

Min 200us

Min 74 clocks


M1PCA00-0008

11 High Priority Interrupt (HPI) (V4.41α or later)

The HPI command (CMD12 or CMD 13 according to V4.41α) can interrupt the

Program/Erase operation during the prg-state in order to perform high priority

read processing.

TOSHIBA’s e-MMCTM

uses CMD13 as the HPI command. Refer to the bit in

EXT_CSD[503] HPI_FEATURES.

11.1 HPI commands

Table 13: HPI commands

11.2 Interruptible commands

Table 14 : Interruptible commands

CMD

Index Name

Is

interruptible?

CMD24 WRITE_BLOCK Yes

CMD25 WRITE_MULTIPLE_BLOCK Yes

CMD38 ERASE Yes

CMD6 SWITCH, byte BKOPS_START,

any value

Yes

CMD6 SWITCH, byte

SANITIZE_START, any value

Yes

CMD6 SWITCH, byte

POWER_OFF_NOTIFICATION,

value POWER_OFF_LONG

or SLEEP_NOTIFICATION

Yes

CMD6 SWITCH, byte

POWER_OFF_NOTIFICATION,

other values

No

CMD6 CACHE_CTRL when used for

turning the cache OFF

Yes

CMD6 FLUSH_CACHE Yes

CMD6 SWITCH, other bytes, any value No

All others No

CMD Index Abbreviation Restrictions

CMD12 STOP_TRANSMISSION -With setting arg[bit:31:16] RCA and arg[bit:0]HPI flag.

-Enable only prg-state. CMD13 SEND_STATUS


M1PCA00-0008

11.3 HPI related register fields

Table 15: HPI related register fields


Value

EXT_CSD [503]HPI_FEATURES R

[bit:0] HPI_SUPPORT

0x0: HPI mechanism not

supported (default)

0x1: HPI mechanism supported

[bit:1]HPI_IMPLEMENTATION

0x0: HPI mechanism

implementation based on CMD13

0x1: HPI mechanism

implementation based on CMD12

0x01

EXT_CSD [161]HPI_MGMT R/W/E_P

[bit:0] HPI_EN

0x0: HPI mechanism not

activated by the host (default)

0x1: HPI mechanism activated by

the host

0x00

EXT_CSD [198]OUT_OF_INTERRUPT_TIME R

Defines the maximum time

between the end bit of

CMD12/13, arg[bit:0]=1 to the

DAT0 release by the device.

0x0A

EXT_CSD [245:242]

CORRECTLY_PRG_SECTORS_NUM R

This field indicates how many

512B sectors were successfully

programmed by the last

WRITE_MULTIPLE_BLOCK

command (CMD25)

0x00

R: Read only.

R/W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0 reset

and readable.


M1PCA00-0008

11.4 HPI pre-process

The host shall check the relevant information about the HPI mechanism and

enable it by setting the HPI_EN bit in the HPI_MGMT field (EXT_CSD byte

[161]) before it may be used.

Figure 27: HPI pre-process

Enable HPI function

Check availability of HPI

End

Start

HPI pre-process

Read EXT_CSD

EXT_CSD[503]HPI_FEATURES [bit:0]HPI_SUPPORT == 1?

Find which CMD host should use, CMD12 or CMD13, for HPI from EXT_CSD[503]HPI_FEATURES[bit:1]HPI_IMPLEMENTATION

Find HPI busy time from EXT_CSD[198]OUT_OF_INTERRUPT_TIME

Yes

No

Enable HPI function by updating EXT_CSD[161]HPI_MGMT[bit:0]HPI_EN to 1


M1PCA00-0008

11.5 HPI process

HPI shall only be executed during prg-state.

Figure 28: HPI process

There is two ways of HPI processing, depending on the state of the device.

1. CMD6, CMD38 : As the device is in prg-state, host can issue HPI command.

2. CMD24, CMD25 : If the host has finished all data transfer, it can issue the

HPI command. On the other hand, if the host has not finished all data transfer, it

can issue the HPI command after setting device into prg-state from rcv-state by

CMD12.

Set eMMC into prg.state

End

Start

HPI process

Which CMD is interrupted?

CMD24 CMD25

Issue HPI command with CMD13 (arg[bit:0]HPI flag = 1)

CMD6 CMD38

Not sending last sector yet ?

No？

Yes

？？

CMD12 with arg[bit:0]HPI flag = 0

eMMC de-assert busy(DAT0 = Low) within [198]OUT_OF_INTERRUPT_TIME


M1PCA00-0008

11.6 HPI post-process

The host may use the information CORRECTLY_PRG_SECTORS_NUM field

(EXT_CSD bytes [245:242]) when interrupting a WRITE_MULTIPLE_BLOCK

command (CMD25). The device updates this field with the number of 512B

sectors successfully written to the device. The host may skip the correctly

programmed sectors and continue writing only the rest of the data that wasn't yet

programmed.

Figure 29: HPI post-process

Start HPI post-process

Interrupted CMD?

Check EXT_CSD[245:242] CORRECTLY_PRG_SECTORS_NUM

And calculate unfinished write size

Issue CMD24/38/6 once again by the same condition

as issued before HPI.

End

Issue CMD25 with only unfinished write data

CMD25 Others


M1PCA00-0008

12 Background Operation (V4.41α or later)

In order to reduce latencies during time critical operations like read and write,

the host can control the maintenance operations by using background operation.

The e-MMCTM

will stay busy (DAT0=Low) until no more background

processing is needed.

12.1 Background operation related register fields

Table 16: Background operation related register fields


Type Explanation

Default

Value

EXT_CSD [502] BKOPS_SUPPORT R

[bit 0]SUPPORTED

0x0 : Background operations are

not supported.

The fields BKOPS_STATUS,

BKOPS_EN,BKOPS_START and

Device Status bit

URGENT_BKOPS are not

supported.

0x1 : Background operations are

supported.

The fields BKOPS_STATUS,

BKOPS_EN,BKOPS_START and

Device Status bit

URGENT_BKOPS are supported.

0x01

EXT_CSD [163] BKOPS_EN R/W

[bit 0]ENABLE

0x0 : Host does not support

background operations handling

and is not expected to write to

BKOPS_START field.

0x1 : Host is indicating that it shall

periodically write to

BKOPS_START field to manually

start background operations.

0x00

EXT_CSD [246] BKOPS_STATUS R

[bit 1:0] OUTSTANDING

0x0 : No operations required

0x1 : Operations outstanding (non

critical)

0x2 : Operations outstanding

(performance being impacted)

0x3 : Operations outstanding

(critical)

0x00


M1PCA00-0008

EXT_CSD [164] BKOPS_START W/E_P

Writing any value to this field shall

manually start background

operations. Device shall stay busy

till no more background operations

are needed.

0x00

EXT_CSD

[54]

EXCEPTION_EVENTS_STATUS

for V4.41α or later

R

[bit:0]URGENT_BKOPS

If set, the device needs to perform

background operations urgently.

Host can check EXT_CSD field

BKOPS_STATUS for the detailed

level.

0x00

Device

status

[bit:6] URGENT_BKOPS

-

"0" = not urgent

"1" = urgent (BKOPS_STATUS is

level 2 or 3)

-

Device

status

[bit:6] EXCEPTION_EVENT

for V4.41α or later -

"0" = no event

"1" = an exception event has

occurred

If set, one of the exception bits in

field EXCEPTION_EVENTS_

STATUS was set to indicate some

exception has occurred. Host

should check that field to discover

which exception has occurred to

understand what further actions are

needed in order to clear this bit.

-

R: Read only.

R/W: One time programmable and readable.

W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0 reset

and not readable.


M1PCA00-0008

12.2 Background operation pre-process

The host shall check the relevant information about the Background operation

and enable it by setting the ENABLE bit in the BKOPS_EN field (EXT_CSD

byte [163]) before it may be used.

Figure 30: Background operation pre-process

Check availability of background operation

Enable background operation function

End

Start

BKOPS pre-process

EXT_CSD[502] BKOPS_SUPPORT == 1?

Yes

No

Enable Background operation function by updating EXT_CSD[163]BKOPS_EN[bit:0]ENABLE to 1

Background operation is not supported

Read EXT_CSD

Note that for backward compatibility reasons in case of V4.41α, if BKOPS_SUPPORT bit [0] is set, then the urgent background operations event ([bit:0]URGENT_BKOPS in EXT_CSD[54] EXCEPTION_EVENTS_STATUS) is always enabled and cannot be disabled. All other enable bits start disabled after power up until set by host.


M1PCA00-0008

12.3 Start & Stop Background operation

Figure 31: Start & Stop Background operation

No

End

Start

BKOPS process

Device status[bit:6] EXCEPTION_EVENT==

1 ?

Yes

No

Read EXT_CSD

Find detail level of background operations urgency from EXT_CSD[246] BKOPS_STATUS

Start background operation by update EXT_CSD[164] BKOPS_START to 1

Busy signal is asserted (Dat0=low) * eMMC is processing Background operation with busy signal(Dat0=low)

Does host issue HPI command ?

Yes

Busy signal is de-asserted (Dat0=High)

There are two ways to finish Background operation. 1. Host may abort Background operation by issuing HPI command. 2. Host won't access the device and waits until BKOPS

completely finished inside the device.

In case of V4.41α, [bit:0]URGENT_BKOPS in EXT_CSD[54]EXCEPTION_EVENTS_STATUS is also set if device requires BKOPS.

[bit:0]URGENT_BKOPS in EXT_CSD[54]EXCEPTION

_EVENTS_STATUS == 1 ?

Yes

Background operation terminated & EXT_CSD[246] BKOPS_STATUS is updated with appropriate value

No

Does eMMC finish background

operation internally?

Yes

No

Background operation correctly finished internally & both EXT_CSD[246] BKOPS_STATUS and Device status[bit:6]EXCEPTION_EVENT was updated to “0” (No operations required)


M1PCA00-0008

13 Combination of HPI and Background operation (V4.41α or

later)

13.1 The HPI processing flow specified by JEDEC

The DAT0 line will be kept low as long as the device is busy and in the

Programming State. It means the e-MMCTM

is performing internal processing.

The e-MMCTM

will release the busy when the host interrupts write processing

using a HPI command.

In this case, the e-MMCTM

reports its background operation status in bits [1:0]

of BKOPS_STATUS (EXT_CSD byte [246]).

If the host runs the background operation when background operation status is

required, the e-MMCTM

will finish the internal processing and clear the

background operation status.

As a result, the host can prevent a long busy from happening at the time of later

Write processing.


M1PCA00-0008

13.2 HPI timing and post-process

Table 17: HPI timing and post-process

Interruptible

CMD

Condition Processing state

( means Interrupt timing)

Interrupt

CMD

How many sectors

did eMMCTM

correctly program

before HPI ?

HPI post

process

CMD24 - during data transfer

CMD12

(rcv->prg)

&

HPI command

0 Write again

- during busy

HPI command Unknown (0 or 1) Write again

CMD25 Open-ended

multi block

write

during data transfer

CMD12

(rcv->prg)

&

HPI command

EXT_CSD [245:242]

CORRECTLY_PRG

_SECTORS_NUM

Write only

unfinished

part

Pre-defined

multi block

write

with block

count =1


CMD12

(rcv->prg)

&

HPI command

during busy

HPI command

Pre-defined

multi block

write

with block

count >1


CMD12

(rcv->prg)

&

HPI command

during busy

HPI command

CMD38 - during busy

HPI command Unknown Erase again

CMD6 Device is

processing

background

operation

during busy

HPI command Background

operation

again if

needed


M1PCA00-0008

13.3 HPI & Background operation sequence

Figure 32: HPI & Background operation sequence

Processing interruptible CMD(24/25/38/6)

HPI pre-process

Refer to section 11.4

End

Have CMD process

finished ?

Yes

No

HPI pre-process

Start

Is there high priority processing request ?

Yes

No

HPI process

Refer to section 11.5 HPI Operation

High priority operation

High priority Read etc. Processing

High priority request

Background operation

Refer to section 12.3

Start & Stop Background Operation

HPI post-process

Refer to section 11.6 HPI post-process


M1PCA00-0008

14 Write Reliability (V4.41α or later)

This is a function that can avoid the collateral damage between Lower Page data

and Upper Page data when the Upper Page data being programmed is affected

by sudden power loss.

The host can set this feature for each partition. (User Data Area Partition &

General Purpose Area partition)

Write Reliability functionality is enabled in the default state.

14.1 Write Reliability related register fields

Table 18: Write Reliability related register fields


Value

EXT_CSD [167] WR_REL_SET R/W

[bit:4] WR_DATA_REL_4




[bit:0] WR_DATA_REL_USR

0x0: In each partition, the

write operation has been

optimized for performance and

existing data in the partition

could be at risk if a power

failure occurs.

0x1: In each partition, the

device protects previously

written data if power failure

occurs during a write

operation.

0x1F

EXT_CSD [166] WR_REL_PARAM R

[bit:0] HS_CTRL_REL

0x0: All the WR_DATA_REL

parameters in the

WR_REL_SET register are

read only bits.

0x1: All the WR_DATA_REL

parameters in the

WR_REL_SET registers are

R/W.

0x05

R: Read only.


14.2 Write Reliability setting

The host can set this feature only once.


M1PCA00-0008

The host cannot set it if EXT_CSD [166] WR_REL_PARAM is zero.

Figure 33: Write Reliability setting

15 Enhanced Reliable Write (V4.41α or later)

This function which keeps the old data associated with a logical address

Check cell type of EXT_CSD[167]WR_REL_SET

Enable write reliability function

End

Start Write Reliability

setting

EXT_CSD [166] WR_REL_PARAM

[bit:0] HS_CTRL_REL == 1?

Yes

No

Enable Write Reliability to each partition by updating EXT_CSD[167] WR_REL_SET[bit:4:0]

WR_DATA_REL_xxx * to 1 * xxx : 4/3/2/1/USR

EXT_CSD [167] WR_REL_SET is not writable. Host cannot control Write Reliability function.

Read EXT_CSD

Set 0x01 to Ext_CSD [175] ERASE_GROUP_DEF

Set 0x01 to Ext_CSD [155] PARTITIONS_SETTING_COMPLETED

Power cycle


M1PCA00-0008

unchanged until the new data written to same logical address has been

successfully programmed when the host does a multiple block write with a pre-

defined block count and enables Reliable Write (CMD23 arg[bit:31]=1).

This is to ensure that the target address updated by the reliable write transaction

never contains undefined data.

The data will remain valid even if a sudden power loss occurs during the

programming.

There are two versions of reliable write.

1. Legacy implementation

Support a maximum of two different sizes of reliable write transactions,

512B and the Reliable Write Sector Count parameter in EXT_CSD

(REL_WR_SEC_C) multiplied by 512B.

2. Enhanced implementation

There is no limit on the size of reliable write transactions.

The block size defined by SET_BLOCKLEN(CMD16) is ignored and all

blocks are 512 B in length.

The Enhanced Reliable Write feature is optional in the JEDEC standard.

Remark:

When the host enables the Reliable Write function, it degrades the sequential

write performance, and increases the number of cycles of Write/Erase access to

the NAND cells.

Both Reliable Write and Write Reliability have a similar effect against an

unexpected power loss during programming and it’s easier for the host to

implement the Write Reliability function.

Therefore, TOSHIBA recommends using the Write Reliability function rather

than Reliable Write.


M1PCA00-0008

15.1 Reliable Write related command

Table 19: Reliable Write related command

CMD Index Abbreviation Explanation

CMD23 SET_BLOCK_COUNT With set arg [bit:31] Reliable Write Request

15.2 Reliable Write related register fields

Table 20: Reliable Write related register fields


Value

EXT_CSD [222] REL_WR_SEC_C R

Reliable Write Sector Count.

The reliable write feature

requires mandatory sector

count 1 (512B) support.

If HPI_SUPPORT =1 and

EN_REL_WR=0 then the

REL_WR_SEC_C register

value must be 1.

0x10

0x01(V5.0)

EXT_CSD [166] WR_REL_PARAM R

[bit:2] EN_REL_WR

0x0: The device supports the

previous definition of reliable

write.

0x1: The device supports the

enhanced definition of reliable

write

0x05

R: Read only.

15.3 Reliable Write Sector Count

Host will find the unit of Reliable Write by combination of the following values.

Table 21: Reliable Write Sector Count

EN_REL_WR

(EXT_CSD[166])

HPI_SUPPORT

(EXT_CSD[503])

REL_WR_SEC_C

(EXT_CSD [222])

0 0 It indicates Reliable Write Sector Count for legacy implementation.

Host should set this size or 512B on CMD23 for Reliable Write.

0 1 The value must be 1.

Device support legacy implementation.

1 1 This value has no meaning.

Device support Enhanced implementation.


M1PCA00-0008

15.4 Enhanced Reliable Write

The host shall read EN_REL_WR field in EXT_CSD and confirm whether the

device supports Enhanced Reliable Write or not.

The host can execute an ‘Enhanced Reliable Write’ if the device supports it.

However, if not, the host can execute ‘Reliable Write’.

Figure 34: Enhanced Reliable Write

End

Start Enhanced Reliable

Write setting

EXT_CSD [166] WR_REL_PARAM [bit:2]

EN_REL_WR == 1?

Yes, eMMC support Enhanced Reliable write

No, eMMC support only Legacy implementation

CMD23 SET_BLOCK_COUNT *1

with arg[bit:31] Reliable Write Request flag =

1

Read EXT_CSD

CMD25 WRITE_MULTIPLE_BLOCK *2

*1: There is no limit on the size. When the length of the write operation is set to “0,” the

operation is executed as a basic, open-ended, multiple-block-write case, even when the

reliable write request is active.

*2: The block size defined by SET_BLOCKLEN(CMD16) is ignored and all blocks are

512 B in length. Reliable write transactions must be sector aligned, if a reliable write is not

sector aligned the error bit 19 will be set and the transaction will not complete.


M1PCA00-0008

16 HS200 (SDR 200MHz) (V4.41α or later)

HS200 is a high speed interface timing mode up to 200MB/s @200MHz. It is

single data rate bus, 4 or 8-bits, and is valid only at Vccq = 1.8V. HS200 is not

supported during BOOT operation.

16.1 HS200 related register fields

Table 22: HS200 related register fields


Type Explanation

Default

Value

EXT_CSD [196]DEVICE_TYPE R

Added two new fields for HS200.

[bit:5] HS200 SDR@200MHz - 1.2V I/O [bit:4] HS200 SDR@200MHz - 1.8V I/O

0x0 : Not supported 0x1 : Supported

0x57

EXT_CSD [197]DRIVER_STRENGTH R

[bit:0] Type 0 [bit:1] Type 1 [bit:2] Type 2 [bit:3] Type 3

Indicates the I/O driver strength types that are supported by a device.


0x1F

EXT_CSD [185]HS_TIMING R/W/E_P

Select bus type by setting this field.

[bit:3:0] Timing Interface

0x0 : Selecting backwards compatibility interface timing 0x1 : High Speed 0x2 : HS200 0x3 : HS400

[bit:7:4] Selected Driver Strength

0x0 : Default Driver Type

0x1 : x1.5

0x2 : x0.75

0x3 : x0.5

0x4 :x1.2

0x00

R: Read only.


and readable.


M1PCA00-0008

16.2 HS200 timing mode selection

After the host initializes the device, it must verify that the device supports the

HS200 mode by reading the DEVICE_TYPE field in the Extended CSD register.

Then it may enable the HS200 timing mode in the device, before changing the

clock frequency to a frequency higher than 52MHz.

After power-on or software reset (CMD0), the interface timing of the device is

set to the default “Backward Compatible Timing”. Device shall select HS200

timing mode if desired and perform the tuning process if needed.

Figure 35 shows the process to switch to HS200.

Figure 35: HS200 selection flow diagram

End

Read EXT_CSD

EXT_CSD [196] DEVICE_TYPE [bit:4] == 1 ?

Find the supported device Driver Strengths from EXT_CSD [197] DRIVER_STRENGTH if needed.

Enable HS200 mode and switch the driver strength by updating EXT_CSD [185] HS_TIMING

Busy signal is asserted (Dat0 = low)

Busy signal is de-asserted (Dat0 = High)

Issue CMD13 SEND_STATUS using the HS200 timing.

If host could receive R1 response with Trans State indication and No Error, the device is set to HS200 timing and the Driver Strength is set to the selected settings.

Host can set the frequency to <= 200MHz

Start

Yes

No


M1PCA00-0008

16.3 HS200 related command

The host may optimize the bus sampling timing when switching to the HS200

mode.

The new command CMD21 is used for sending the tuning block.

The device transmits 128 clocks of data, 64 bytes in 4 bit mode, or 128 bytes in

8 bit mode, with a known data pattern to the host which uses it to find the

optimal sampling point for the data lines.

Table 23: HS200 related command


CMD21 SEND_TUNING_ BLOCK 128 clocks of tuning pattern (64 bytes in 4 bit mode or 128 bytes in 8 bit mode) is sent for HS200 optimal sampling point detection

CMD21 is valid only in HS200 mode and only when the device is unlocked.

In any other state, CMD21 is treated as an illegal command.

Since the data block following CMD21 is fixed, CMD16 is not required to precede CMD21.


M1PCA00-0008

17 HS400 (DDR 200MHz) (V5.0)

HS400 is a high speed interface timing mode up to 400MB/s @DDR200MHz.

It is dual data rate bus, 8-bits, and is valid only at Vccq = 1.8V. HS400 is not

supported during BOOT operation.

17.1 HS400 related register fields

Table 24: HS400 related register fields


Value

EXT_CSD [196]DEVICE_TYPE R Added two new fields for HS400.

[bit:7] HS400 DDR@200MHz - 1.2V I/O [bit:6] HS400 DDR@200MHz - 1.8V I/O


0x57

EXT_CSD [197]DRIVER_STRENGTH R [bit:0] Type 0 [bit:1] Type 1 [bit:2] Type 2 [bit:3] Type 3 [bit:4] Type 4

Indicates the I/O driver strength types that are supported by a device.


0x1F

EXT_CSD [185]HS_TIMING R/W/E_P Select bus type by setting this field.

[bit:3:0] Timing Interface

0x0 : Selecting backwards compatibility interface timing 0x1 : High Speed 0x2 : HS200 0x3 : HS400

[bit:7:4] Selected Driver Strength

0x0 : Default Driver Type

0x1 : x1.5

0x2 : x0.75

0x3 : x0.5

0x4: x1.2

0x00

R: Read only.


and readable.


M1PCA00-0008

17.2 HS400 timing mode selection

After the host initializes the device, it must verify that the device supports the

HS400 mode by reading the DEVICE_TYPE field in the Extended CSD register.

Then it may enable the HS400 timing mode in the device, before changing the

clock frequency to a frequency higher than 52MHz.

After power-on or software reset (CMD0), the interface timing of the device is

set to the default “Backward Compatible Timing”. Device shall select HS400

timing mode if desired and perform the tuning process if needed.

Figure 36 shows the process to switch to HS400.

Figure 36: HS400 selection flow diagram

End

Read EXT_CSD

EXT_CSD [196] DEVICE_TYPE [bit:6] == 1?

Find the supported device Driver Strengths from EXT_CSD [197] DRIVER_STRENGTH if needed.

Enable HS400 mode and switch the driver strength by updating EXT_CSD [185] HS_TIMING

Set HS_TIMING [185] with [CMD 6 03B94300] in EXTCSD, Timing Interface changed to HS400

Start

Yes

No

Set HS_TIMING [185] with [CMD 6 03B94200] in EXTCSD, Timing Interface changed to HS200 mode

Set BUS_WIDTH [183] = 2 in EXTCSD, 8 bit Bus SDR

Tuning CMD line delay in HS200 mode

Host bus mode is switched to bus width 8bit, bus frequency 200MHz and initialization of bus delay timing


M1PCA00-0008

17.3 HS400 Switch Function Handling Specification

Switch error will be generated if HS_TIMING[185] or BUS_WIDTH[183] is

not set properly. Kindly refer figure below for the details.

In case of HS_TIMING[185] Setting:

Examples: For V4.41α, Ver.4.5 devices that don’t support HS400 feature, switch

error (SW_ERR) will be generated if switch HS(DDR) mode to HS200 mode.

Figure 37: HS400 Switch function specification for HS_TIMING


M1PCA00-0008

In case of BUS_WIDTH[183] Setting:

Examples: For V4.41α, Ver.4.5 devices that don’t support HS400 feature, switch

error (SW_ERR) will be generated if switch HS200 mode to DDR4/8b mode.

Figure 38: HS400 Switch function specification for BUS_WIDTH


M1PCA00-0008

18 Sanitize (V4.41α or later)

This function requires the device to physically remove data from all unmapped

user address space.

A Sanitize operation is initiated by writing a value to the extended CSD[165]

SANITIZE_START. While the device is performing the sanitize operation, the

busy line is asserted. The device will continue the sanitize operation, with busy

asserted, until one of the following events occurs:

Sanitize operation is complete.

An HPI is used to abort the operation.

A power failure.

A hardware reset.

After the sanitize operation is completed, no data should exist in the unmapped

host address space.

18.1 Sanitize related register fields

Table 25: Sanitize related register fields


Type Explanation

Default

Value

EXT_CSD [165] SANITIZE_START W/E_P

Writing any value to this field shall manually start a sanitize operation. Device shall stay busy until sanitize is complete.

0x00


and not readable.


M1PCA00-0008

19 Discard (V4.41α or later)

This function allows the host to identify data that is no longer required so that

the device can erase the data if necessary during background erase events. The

contents of a write block where the discard function has been applied shall be

‘don’t care’.

The DISCARD function timeout is calculated based on the TRIM_MULT factor

(EXT_CSD byte [232]).

19.1 Discard related command

Table 26: Discard related command


CMD35 ERASE_GROUP_START Sets the address of the first erase group within a

range to be selected for erase

CMD36 ERASE_GROUP_END Sets the address of the last erase group within a

continuous range to be selected for erase

CMD38 ERASE

Erases all previously selected write blocks.

Argument bit 0 and bit 1 set to one and the remainder

of the arguments set to zero means discard operation.

19.2 Discard related register fields

Table 27: Discard related register fields


Value

EXT_CSD [232] TRIM_MULT R

This register is used to

calculate the timeout value for

the TRIM and DISCARD

operation inside a logical

erase group.

0x01

Device

status [bit:13] ERASE_RESET -

“0” = cleared

“1” = set -

R: Read only.


M1PCA00-0008

20 Packed command (V4.41α or later)

Read and write commands can be packed into groups of commands (either all

read or all write) that transfer the data for all commands in the group in one

transfer on the bus to reduce overhead.

The maximum number of read or write commands that can be packed in a single

packed command is reported by the device in MAX_PACKED_READS and

MAX_PACKED_WRITES fields in EXT_CSD respectively.

Figure 39 and Figure 40 show an example of the packed write/read command

sequence.

Figure 39: Packed write command sequence

Figure 40: Packed read command sequence

CMD CMD23

Packed command

header DAT

Packed Write CMD w/ PACKED flag

Arg:First write address

RES CMD25 RES

DAT 512byte

CMD CMD23

Packed command

header DAT

Packed Write CMD w/ PACKED flag

Arg:First read address

RES CMD25 RES

DAT 512byte

Arg:Clock count w/ PACKED flag

CMD23 RES

Arg:First read address

CMD18 RES


M1PCA00-0008

20.1 Packed command header

Table 28 shows the format of the packed command header.

Table 28: Packed command structure

Entry index Offset (Bytes) Name Length(Bytes)

-

+0 VERSION*1

1

+1 R/W*2

1

+2 NUM_ENTRIES (=N)*3

1

+3 Padding to 8B 5

1 +8 CMD23_ARG_1

*4 4

+12 CMDxx_ARG_1*5

4

2 +16 CMD23_ARG_2

*4 4

+20 CMDxx_ARG_2*5

4

3 +24 CMD23_ARG_3

*4 4

+28 CMDxx_ARG_3*5

4

...

N +8N CMD23_ARG_N

*4 4

+8N+4 CMDxx_ARG_N*5

4

- +8N+8 Padding till block ends

*1 Version of structure – a byte to indicate version for future compatibility; shall be set to 0x01.

*2 R/W flag – 0x01 for packed read, 0x02 for packed write.

*3 Number of entries in the table.

*4 Argument of CMD23 of the individual command (4 bytes), formatted as in CMD23, including both the

‘count’ field and the various flags fields (high bits), with the ‘packed’ bit always ‘0’. (except for the

‘packed’ bit, all other CMD23 argument bits are still allowed in the header)

*5 Argument of CMD18 or CMD25 (4 bytes) – the address read/written by the individual command.


M1PCA00-0008

20.2 Packed related command

Table 29: Packed related command


CMD23 SET_BLOCK_COUNT

Defines the number of blocks (read/write) for the following packed write command or for the header of the following packed read command.

For packed write commands, the number of blocks should include the total number of blocks all packed commands plus one for the header block.

For packed read commands, the number of blocks should equal one as only the header is sent inside the following CMD25. After that, a separate normal read command is sent to get the packed data.

For example, following argument for CMD23 is used in the packet command

sequence.

Table 30: CMD23 (packed) argument

Bit Bit 31 Bit 30 Bit 29:16 Bit 15:0

Format set to 0 ‘1’ PACKED flag set to 0 number of blocks

First packed write command

sequence 0 1 0

the sum of all block counts

of the individual writes

plus one

First packed read command

sequence 0 1 0

1 for packed command

header

First packed read command

sequence

(CMD23 here is optional – open-

ended reading is allowed)

0 1 0 the sum of all block counts

of the individual reads

20.3 Packed interruptible commands

Host can send only CMD13 SEND_STATUS or CMD12

STOP_TRANSMISSION during the packed command sequence.


M1PCA00-0008

20.4 Packed related register fields

Table 31: Packed related register fields


Type Explanation

Default

Value

EXT_CSD [501]MAX_PACKED_READS R The maximum number of commands that can be packed inside a packed read command.

0x3F

EXT_CSD [500]MAX_PACKED_WRITES R The maximum numbers of commands that can be packed inside a packed write command.

0x3F

EXT_CSD [56]EXCEPTION_EVENTS_CTRL R/W/E_P

[bit:3]PACKED_EVENT_EN

Each bit enables the use of the relevant exception event bit, allowing it to raise the EXCEPTION_EVENT bit in Device Status.

0x00

EXT_CSD [54]

EXCEPTION_EVENTS_STATUS R

[bit:3]PACKED_FAILURE

If set, the last packed command has failed. Host may check EXT_CSD field PACKED_COMMAND_STATUS for the detailed cause.

0x00

EXT_CSD [36]PACKED_COMMAND_STATUS R

[bit:1]Indexed error

If the error is a result of one of the individual commands inside the packed command, its index is reported in PACKED_FAILURE_INDEX [35] and ‘Indexed Error’ bit (bit 1) is set as well.

[bit:0]Error

In case any error occurs during a packed command, the ‘Error’ bit (bit 0) shall be set.

0x00

EXT_CSD [35]PACKED_FAILURE_INDEX R

If the ‘Indexed Error’ bit (bit 1) in PACKED_COMMAND_STATUS is set, this field specifies the index in the header of the failed command.

0x00

Device

status [bit:6]EXCEPTION_EVENT -

If set, one of the exception bits in field EXCEPTION_EVENTS_STATUS was set to indicate some exception has occurred. Host should check that field to discover which exception has occurred to understand what further actions are needed in order to clear this bit.

-

R: Read only.


and readable.


M1PCA00-0008

20.5 Packed Commands Error Handling

If one of the individual commands causes a failure, the following individual

commands within the same packed command are not executed.

The host can use the EXCEPTION_EVENT bit in R1 response in order to find

the index in the header of the failed command.

The following chart shows an example of how the host can determine the error.

Figure 41: Determining the error during a packed command sequence

End

Start

Device Status [bit:6] EXCEPTION_EVENT in R1 response

= = 1 ?

Yes

Enables the use of the packed event by setting 0x08 to EXT_CSD [56] EXCEPTION_EVENTS_CTRL if needed.

Execute a packed command and some error happens.

Read EXT_CSD

[bit:3]PACKED_FAILURE in EXT_CSD [54] EXCEPTION_

EVENTS_STATUS == 1?

Yes

[bit:0]Error and [bit:1]Indexed Error in EXT_CSD

[36]PACKED_COMMAND_STATUS == 1?

Yes

No

Host can check EXT_CSD[245:242]CORRECTLY_PRG_ SECTORS_NUM and calculate unfinished write size if needed.

No

No

Host can find the index in the header of the failed command by checking [35]PACKED_FAILURE_INDEX.

Device Status [bit:19]ERROR is also set if [bit:6]EXCEPTION_EVENT is set.


M1PCA00-0008

21 Exception Events (V4.41α or later)

The exception events allows the device to report some exceptions quickly to the

host by setting the EXCEPTION_EVENT bit in Device Status in R1 response.

21.1 Exception Events related register fields

Table 32: Exception Events related register fields


Type Explanation

Default

Value

Device

status [bit:6]EXCEPTION_EVENT -

If set, one of the exception bits in field EXCEPTION_EVENTS_ STATUS was set to indicate some exception has occurred. Host should check that field to discover which exception has occurred to understand what further actions are needed in order to clear this bit.

-

EXT_CSD [56:57]EXCEPTION_EVENTS_CTRL R/W/E_P

[bit:3]PACKED_EVENT_EN [bit:2]SYSPOOL_EVENT_EN [bit:1]DYNCAP_EVENT_EN

Each bit enables the use of the relevant exception event bit, allowing it to raise the EXCEPTION_EVENT bit in Device Status.

TOSHIBA V4.41α device support only [bit:3]

0x00

EXT_CSD [54:55]

EXCEPTION_EVENTS_STATUS R

[bit:3]PACKED_FAILURE

If set, the last packed command has failed. Host may check EXT_CSD field PACKED_COMMAND_STATUS for the detailed cause.

[bit:2]SYSPOOL_EXHAUSTED

If set, system resources pool has no more available resources and some data needs to be untagged before other data can be tagged

[bit:1]DYNCAP_NEEDED

If set, device needs some capacity to be released.

[bit:0]URGENT_BKOPS

If set, the device needs to perform background operations urgently. Host can check EXT_CSD field BKOPS_STATUS for the detailed level.

TOSHIBA V4.41α device support only [bit:3] and [bit:0]

0x00

R: Read only.


and readable.


M1PCA00-0008

22 Power Off notification (V4.41α or later)

The host should notify the device before it powers the device off. This function

allows the device to prepare itself for being powered off.

22.1 Power Off related register fields

Table 33: Power Off related register fields


Type Explanation

Default

Value

EXT_CSD [34]POWER_OFF_NOTIFICATION R/W/E_P

0x00: NO_POWER_NOTIFICATION

Power off notification is not supported by host, device shall not assume any notification

0x01: POWERED_ON

Host shall notify before powering off the device, and keep power supplies alive and active until then

0x02: POWER_OFF_SHORT

Host is going to power off the device, The device shall respond within GENERIC_CMD_6_TIME.

0x03: POWER_OFF_LONG

Host is going to power off the device The device shall respond within POWER_OFF_LONG_TIME.

0x04: SLEEP_NOTIFICATION

Host is going to put the device in Sleep Mode. The device shall respond within SLEEP_NOTIFICATION_TIME.

0x00

EXT_CSD [248]GENERIC_CMD6_TIME R

The default maximum timeout for a SWITCH command (CMD6) unless a specific timeout is defined when accessing a specific field. Time is expressed in units of 10-milliseconds.

0x05

EXT_CSD [247]POWER_OFF_LONG_TIME R

The maximum timeout for the SWITCH command (CMD6) when notifying the device that power is about to be turned off by writing POWER_OFF_LONG to POWER_OFF_NOTIFICATION[34] byte. Time is expressed in units of 10-milliseconds.

0x32

EXT_CSD [216]SLEEP_NOTIFICATION_TIME(*)

R

The maximum timeout for the SWITCH command (CMD6) when notifying the device that it is about to be move to sleep state. Time is expressed in units of 10-milliseconds.

0x10


M1PCA00-0008

R: Read only.


and readable.

(*) Available for V5.0 only

22.2 Power Off notification setting

Figure 42: Power Off notification setting sequence for V4.5 and V5.0


M1PCA00-0008

23 Large sector size (V4.41α or later)

TOSHIBA’s e-MMCTM

V4.41α and later supports large 4KB sectors.

For backward compatibility, the devices shall work in emulation mode when

shipped. In emulation mode, the device emulates 512B operations internally.

The emulation mode may be disabled by the host. Once emulation mode is

disabled, the sector size is set permanently to the native sector size.

23.1 Large sector related register fields

Table 34: Large sector related register fields


Type Explanation

Default

Value

EXT_CSD [63]NATIVE_SECTOR_SIZE R

This field indicates the native size of sectors supported by the device:

0x00: Native sector size is 512B 0x01: Native sector size is 4KB 0x02-0xFF: Reserved

0x01

EXT_CSD [62]USE_NATIVE_SECTOR R/W

This field controls if a sector size of 512B is emulated on a native sector size other than 512B:

0x00: Device is emulating a 512B sector size or uses a native 512B sector size

0x01: Device is using a larger than 512B native sector size

0x02-0xFF: Reserved

0x00

EXT_CSD [61]DATA_SECTOR_SIZE R

This field indicates the current sector size that can be accessed or addressed:

0x00: Data sector size is 512B 0x01: Data sector size is 4KB 0x02-0xFF: Reserved

0x00

EXT_CSD [60]INI_TIMEOUT_EMU R

This register indicates the maximum initialization timeout during the first power up after successful disabling of the 512B emulation mode.

0x0A

R: Read only.



M1PCA00-0008

23.2 Disabling emulation mode setting

Figure 43: Large sector size setting sequence

End

Read EXT_CSD

EXT_CSD [63] NATIVE_SECTOR_SIZE == 1 ?

Disable emulation mode by setting 0x01 to EXT_CSD [62]USE_NATIVE_SECTOR

Execute a power cycle and initialize by using CMD1 initialization timeout for CMD1 is then defined by the

[60]INI_TIMEOUT_EMU.

Start

Yes, device support large sector size

No

Disable emulation mode?

Yes, use large sector size

No

Host can check the device now works in large sector mode by [61]DATA_SECTOR_SIZE is 0x01.

Read EXT_CSD

A large sector device shall not support partial access and shall not support reliable write mode EN_REL_WR=0. Any valid commands issued after USE_NATIVE_SECTOR is set to 0x01 but before a power cycle takes place will be normally executed. After a successful disabling of the emulation mode, the content of the User Data Area is undefined.

Power cycle


M1PCA00-0008

24 Boot Partition individual Write Protection

TOSHIBA’s e-MMCTM

V4.41α and later supports two levels of write

protection: Permanent write protection or power-on write protection.

This protection can be applied to each boot area individually or to both regions

with V4.41α and later devices.

24.1 Boot Partition Write Protection related register fields

Table 35: Boot Partition Write Protection related register fields


Value

EXT_CSD [174] BOOT_WP_STATUS R

This byte allows the host to read the current protection status of the boot sectors.

[bit:3:2] B_AREA_2_WP

0x00:Boot Area 2 is not protected 0x01:Boot Area 2 is Power on protected 0x10:Boot Area 2 is Permanently Protected 0x11:Reserved

[bit:1:0] B_AREA_1_WP

0x00:Boot Area 1 is not protected 0x01:Boot Area 1 is Power on protected 0x10:Boot Area 1 is Permanently Protected 0x11:Reserved

0x00

EXT_CSD [173]BOOT_WP R/W &

R/W/C_P

This byte allows the host to apply permanent or power-on write protection to the boot area.

Bit[7]: B_SEC_WP_SEL

Bit[6]: B_PWR_WP_DIS

Bit[4]: B_PERM_WP_DIS

Bit[3]: B_PERM_WP_SEC_SEL

Bit[2]: B_PERM_WP_EN

Bit[1]: B_PWR_WP_SEC_SEL

Bit[0]: B_PWR_WP_EN

Please see JEDEC Standard for detail.

0x00


M1PCA00-0008

25 Data Tag(V4.5 or later)

Tag size is more than 0.1% of User Area Size, e-MMC will report with

EXCEPTION_EVENT bit in Device Status in R1 response & SYSPOOL

EXHAUSTED=1(EXT_CSD[54])

25.1 Data Tag related command

Table 36: Data Tag related command



With set arg [bit:29] Data Tag Request

Tag and Context ID cannot be used together in the

same command, if one is used the other must be set

to zero.

25.2 Data Tag related register fields

Table 37: Data Tag related register fields


Value

EXT_CSD [499]

SYSTEM_DATA_TAG_SUPPORT R

This field indicates if the Data

Tag mechanism features are

supported.

0x01

EXT_CSD [498] TAG_UNIT_SIZE R

This field is used by the host

to calculate the size of a Tag

Unit in Bytes.

0x03

EXT_CSD [497] TAG_RES_SIZE R

This field is defined to inform

the host about the maximum

quantity of resources in bytes

allocated by the device to

allocate system data by the

tagging mechanism:

0x00

R: Read only.


M1PCA00-0008

26 Dynamic Capacity(V4.5 or later)

The device keeps an indication DYNCAP_NEEDED in EXT_CSD byte [58] to

notify the host how many WP-Groups host should release.

26.1 Dynamic Capacity related command

Table 38: Dynamic Capacity related command


CLASS_6_CTRL=0x00 CLASS_6_CTRL=0x01

CMD28 SET_WRITE_PROT

If the Device has write protection

features, this command sets the

write protection bit of the

addressed group. The properties

of write protection are coded in

the Device specific data

(WP_GRP_SIZE or

HC_WP_GRP_SIZE).

This command releases

the specified addressed

group.

CMD29 CLR_WRITE_PROT

If the Device provides write

protection features, this

command clears the write

protection bit of the addressed

group.

This command is

ignored.

CMD30 SEND_WRITE_PROT

If the Device provides write

protection features, this

command asks the Device to

send the status of the write

protection bits.1

This command asks the

device to send the status

of released groups. A bit

‘0’ means the specific

group is valid and

accessible, a bit ‘1’

means the specific group

was released and it

cannot be used.2

CMD31 SEND_WRITE_PROT_TYPE

This command sends the type of

write protection that is set for the

different write protection

groups3.

This command returns a

fixed pattern of 64-bit

zeros in its payload.

NOTE 1. 32 write protection bits (representing 32 write protect groups starting at the specified address)

followed by 16 CRC bits are transferred in a payload format via the data lines. The last (least significant) bit

of the protection bits corresponds to the first addressed group. If the addresses of the last groups are outside

the valid range, then the corresponding write protection bits shall be set to zero.

NOTE 2. 32 released status bits (representing 32 write protect groups starting at the specified address)

followed by 16 CRC bits are transferred in a payload format via the data lines. The last (least significant) bit

of the released bits corresponds to the first addressed group. If the addresses of the last groups are outside the

valid range, then the corresponding released bits shall be set to zero.


followed by 16 CRC bits are transferred in a payload format via the data lines. Each set of two protection bits

shows the type of protection set for each of the write protection groups. The definition of the different bit

settings are shown below. The last (least significant) two bits of the protection bits correspond to the first

addressed group. If the addresses of the last groups are outside the valid range, then the corresponding write

protection bits shall be set to zero.

“00” Write protection group not protected

“01” Write protection group is protected by temporary write protection

“10” Write protection group is protected by power-on write protection

“11” Write protection group is protected by permanent write protection


M1PCA00-0008

26.2 Dynamic Capacity related register fields

Table 39: Dynamic Capacity related register fields


Value

EXT_CSD [59] CLASS_6_CTRL R/W/E_P

This field controls the usage of

class 6 command set (CMD28,

CMD29, CMD30 and

CMD31). By setting this field

to 0x00, class 6 command set

is used for WP. By setting this

field to 0x1, class 6 command

set is used to manipulate the

dynamic capacity

functionality. Setting any

other value (0x02-0xFF) is

forbidden.

0x00

EXT_CSD [58] DYNCAP_NEEDED R

This field is a read only field

through which the device

indicates to the host the

amount of WP-Groups that the

device requests to be released

from the user area address

space.

0x00

R: Read only.


M1PCA00-0008

27 Context Management(V4.5 or later)

By sending CMD6, host can set the Context_ID(EXT_CSD byte [51:37])

Host send Context write when bit[1:0] of CONTEXT_CONFIG is [10], Device

return ERROR in Device_Status[19]

Host send Context read when bit[1:0] of CONTEXT_CONFIG is [01], Device

return ERROR in Device_Status[19]

Host reopen same Context_ID, Device return SWITCH_ERROR in

Device_Status[7]

27.1 Context Management related command

Table 40: Context Management related command



[bit:28:25] is context id

The context ID is an identifier (0 to 15) that

associates the read/write command with the specific

context.

27.2 Context Management related register fields

Table 41: Context Management related register fields


Value

EXT_CSD [496] CONTEXT_CAPABILITIES R

This field describes the

capabilities of context

management.

0x7F

EXT_CSD [51:37] CONTEXT_CONFIG R/W/E_P

CONTEXT_CONF is an array

of 15 bytes, each controlling

the configuration of the

relevant ID, starting with ID

#1. Context ID #0 is reserved

for context-less operation and

has no configuration register.

0x00

R: Read only.


M1PCA00-0008

28 Real Time Clock Info.(V4.5 or later)

Providing real time clock information to the device may be useful for internal

maintenance operations.

28.1 Real Time Clock Info related command

Table 42: Real Time Clock Info related command


CMD49 SET_TIME Sets the real time clock according to the RTC

information in the 512B data block.

29 Device Health Report(V5.0)

Providing device health report may be useful for internal maintenance

operations.

29.1 Device Health Report related command

Table 43: Device Health Report related command


Value

EXT_CSD [254:261] FIRMWARE_VERSION R Provides the device firmware

version 0xXX

EXT_CSD [262:263] DEVICE_VERSION R Provides the device version 0xXX

EXT_CSD [264] OPTIMAL_TRIM_SIZE R

Provides the minimum

optimal (for the device) erase

unit size (for the different

partitions).

0x01

EXT_CSD [265] OPTIMAL_WRITE_SIZE R


optimal (for the device) write

unit size for the different

partitions.

Depends

on the

device

EXT_CSD [266] OPTIMAL_READ_SIZE R


optimal (for the device) trim

unit size for the different

partitions..

Depends

on the

device

EXT_CSD [267]PRE_EOL_INFO R

Provides indication about

device life time reflected by

average reserved blocks.

0x01

EXT_CSD [268] DEVICE_LIFE_TIME_EST_TYP_A

R

Provides an estimated

indication about the device

life time which is reflected by

the averaged wear out of

memory of Type A relative to

its maximum estimated

device life time. 1

0x01


M1PCA00-0008

EXT_CSD [269] DEVICE_LIFE_TIME_EST_TYP_B

R

Provides an estimated

indication about the device

life time which is reflected by

the averaged wear out of

memory of Type B relative to

its maximum estimated

device life time. 2

0x00

EXT_CSD [270:301] VENDOR_PROPRIETARY

_HEALTH_REPORT R

Reserved for vendor

proprietary health report. 0x00

R: Read only.

NOTE 1. Type A refers to Default area

NOTE 2. Type B refers to Enhanced area


M1PCA00-0008

30 Secure Removal Type (V5.0)

Indicates that how information is removed from the physical memory during a

Purge operation. It can be set once during system integration by host.

30.1 Secure Removal Type related command

Table 44: Secure Removal Type related command


Value

EXT_CSD [16] SECURE_REMOVAL_TYPE R/W & R

[bit3:0] Supported Secure

Removal Type

[Bit:0] Information removed

by an erase of the physical

memory


by an overwriting the

addressed locations with a

character followed by an erase


by an overwriting the

addressed locations with a

character, its complement,

then a random character


using a vendor defined.

[bit5:4] Configure Secure

Removal Type

0x0: Information removed by

an erase of the physical

memory

0x1: information removed by

an overwriting the addressed

locations with a character

followed by an erase

0x2: information removed by

an overwriting the addressed

locations with a character, its

complement, then a random

character

0x3: information removed

using a vendor defined

0x09


M1PCA00-0008

31 Thermal Spec(V4.5 or later)

e•MMC device may condition their maximum performance to cases in which

host conforms to the Tcase control temperature tables as given in Annex A.10 In

that case host that wish to utilize the maximum performance and conforms to the

given Case temperature (Tc) tables shall set the TCASE_SUPPORT bits

accordingly:

TCASE_SUPPORT = 0x01 : Table 204 in Annex A.10 is supported. Heat relief

through Case only is assumed.

TCASE_SUPPORT = 0x10 : Table 204 in Annex A.10 is supported. Heat relief

through Case & PCB/Balls is assumed.

If TCASE_SUPPORT bit is =“0x00” the above mentioned device may limit the

maximum available performance.

31.1 Thermal Spec related register fields

Table 45: Thermal Spec related register fields


Value

EXT_CSD [132] TCASE_SUPPORT W/E_P 0x00

R: Read only.


M1PCA00-0008

32 Extended Partition Attribute(V4.5)

Each General Purpose Partition can have a different extended partition attribute.

The list of attribute types includes:

• Default – no extended attribute is set

• System code – a partition that is rarely updated and contains important system

files (e.g. containing the executable files of the host operating system)

• Non-Persistent – a partition that is used for temporary information (e.g. swap

file to extend the host virtual memory space)

Using the extended attribute, the device can optimize the mixture of storage

media characteristics to better suit the intended uses per partition.

A single partition cannot have both enhanced and extended attributes set for it.

32.1 Extended Partition Attribute related register fields

Table 46: Extended Partition Attribute related register fields


Value

EXT_CSD [494] EXT_SUPPORT R

This field describes the

extended partitions attribute

support.

0x03

EXT_CSD [160] PARTITIONING_SUPPORT R This register defines supported

partition features. 0x07

EXT_CSD [53:52]

EXT_PARTITIONS_ATTRIBUTE R/W Host can switch this field 0x00

R: Read only.


M1PCA00-0008

33 New register fields (V4.41α, V4.5 or V5.0)

The following are the JEDEC V4.41α, V4.5 or V5.0 new register fields. Refer to

JESD84-B50 for details.

33.1 Extended CSD Register

Table 47: New register fields in Extended CSD Register (V4.41α, V4.5 or V5.0)

Name Field Size

(Bytes)

Cell

Type slice

Default Value

V4.41α V4.5 V5.0

Extended Security

Commands Error EXT_SECURITY_ERR 1 R [505]

Nonsupp

ort

Nonsupp

ort 0x00

Max packed read commands MAX_PACKED_READS 1 R [501] 0x3F 0x3F 0x3F

Max packed write commands MAX_PACKED_WRITES 1 R [500] 0x3F 0x3F 0x3F

Data Tag Support DATA_TAG_SUPPORT 1 R [499] 0x00 0x01 0x01

Tag Unit Size TAG_UNIT_SIZE 1 R [498] 0x00 0x03 0x03

Tag Resource Size TAG_RES_SIZE 1 R [497] 0x00 0x00 0x00

Context management

capabilities CONTEXT_CAPABILITIES 1 R [496] 0x00 0x7F 0x7F

Large Unit size LARGE_UNIT_SIZE_M1 1 R [495] 0x00 0x00 0x00

Extended partitions attribute

support EXT_SUPPORT 1 R [494] 0x00 0x03 0x03

Supported modes SUPPORTED_MODES 1 R [493] Nonsupp

ort

Nonsupp

ort 0x01

FFU features FFU_FEATURES 1 R [492] Nonsupp

ort

Nonsupp

ort 0x00

Operation codes timeout OPERATION_CODES_TIMEOU

T

1 R [491] Nonsupp

ort

Nonsupp

ort 0x00

FFU Argument FFU_ARG 4 R [490:

487]

Nonsupp

ort

Nonsupp

ort All’F’

Number of FW sectors

correctly programmed

NUMBER_OF_FW_SECTORS_C

ORRECTLY_PROGRAMMED

4 R [305:

302]

Nonsupp

ort

Nonsupp

ort All’0’

Vendor proprietary health

report

VENDOR_PROPRIETARY_HEA

LTH_REPORT

32 R [301:

270]

Nonsupp

ort

Nonsupp

ort All‘0’

Device life time estimation

type B

DEVICE_LIFE_TIME_EST_TYP

_B

1 R [269] Nonsupp

ort

Nonsupp

ort 0x00

Device life time estimation

type A

DEVICE_LIFE_TIME_EST_TYP

_A

1 R [268] Nonsupp

ort

Nonsupp

ort 0x01

Pre EOL information PRE_EOL_INFO 1 R [267] Nonsupp

ort

Nonsupp

ort 0x01

Optimal read size OPTIMAL_READ_SIZE 1 R [266] Nonsupp

ort

Nonsupp

ort

Depend

on the

device

Optimal write size OPTIMAL_WRITE_SIZE 1 R [265] Nonsupp

ort

Nonsupp

ort

Depend

on the

device

Optimal trim unit size OPTIMAL_TRIM_UNIT_SIZE 1 R [264] Nonsupp

ort

Nonsupp

ort 0x01

Device version DEVICE_VERSION 2 R [263:

262]

Nonsupp

ort

Nonsupp

ort 0xXX

Firmware version FIRMWARE_VERSION 8 R [261:

254] Nonsupp

ort

Nonsupp

ort

Depend

on the

device


M1PCA00-0008

Power class for 200MHz,

DDR at VCC= 3.6V PWR_CL_DDR_200_360 1 R [253]

Nonsupp

ort

Nonsupp

ort

Depend

on the

device

Cache size CACHE_SIZE 4 R [252:

249] All’0’ All’0’

0x00001

000

Generic CMD6 timeout GENERIC_CMD6_TIME 1 R [248] 0x05 0x05 0x05

Power off notification (long)

timeout POWER_OFF_LONG_TIME 1 R [247] 0x32 0x32 0x32

Power class for 200MHz @

3.6V PWR_CL_200_360 1 R [237]

Depend

on the

device

Depend

on the

device

Depend

on the

device

Power class for 200MHz @

1.95V PWR_CL_200_195 1 R [236]

Depend

on the

device

Depend

on the

device

Depend

on the

device

Secure Erase Multiplier(*1)

SEC_ERASE_MULT 1 R [230]

Depend

on the

device

Depend

on the

device

Depend

on the

device

Secure TRIM Multiplier(*1)

SEC_TRIM_MULT 1 R [229]

Depend

on the

device

Depend

on the

device

Depend

on the

device

Production state awareness

timeout

PRODUCTION_STATE_AWAR

ENESS_TIMEOUT

1 R [218] Nonsupp

ort

Nonsupp

ort 0x0A

Sleep Notification Timout1

SLEEP_NOTIFICATION_TI

ME

1 R [216] Nonsupp

ort

Nonsupp

ort 0x10

I/O Driver Strength DRIVER_STRENGTH 1 R [197] 0x0F 0x0F 0x1F

Boot write protection status

registers B OOT_WP_STATUS 1 R [174] 0x00 0x00 0x00

Start Sanitize operation SANITIZE_START 1 W/E_P [165] 0x00 0x00 0x00

Production state awareness PRODUCTION_STATE_AWAR

ENESS

1 R/W/E [133] Nonsupp

ort

Nonsupp

ort 0x00

Package Case Temperature is

controlled TCASE_SUPPORT 1 W/E_P [132] 0x00 0x00 0x00

Periodic Wake-up PERIODIC_WAKEUP 1 R/W/E [131] 0x00 0x00 0x00

Program CID/CSD in DDR

mode support

PROGRAM_CID_CSD_DDR_SU

PPORT 1 R [130] 0x01 0x01 0x01

Vendor Specific Fields VENDOR_SPECIFIC_FIELD 64 TBD [127:

64] TBD TBD TBD

Native sector size NATIVE_SECTOR_SIZE 1 R [63] 0x01 0x01 0x01

Sector size emulation USE_NATIVE_SECTOR 1 R/W [62] 0x00 0x00 0x00

Sector size DATA_SECTOR_SIZE 1 R [61] 0x00 0x00 0x00

1st initialization after

disabling sector size

emulation

INI_TIMEOUT_EMU 1 R [60] 0x0A 0x0A 0x0A

Class 6 commands control CLASS_6_CTRL 1 R/W/

E_P [59] 0x00 0x00 0x00

Number of addressed group

to be Released DYNCAP_NEEDED 1 R [58] 0x00 0x00 0x00

Exception events control EXCEPTION_EVENTS_CTRL 2 R/W/

E_P [57:56] All’0’ All’0’ All’0’

Exception events status EXCEPTION_EVENTS_STATU

S 2 R [55:54] All’0’ All’0’ All’0’

Extended partitions attribute EXT_PARTITIONS_ATTRIBUT

E 2 R/W [53:52] 0x00 0x00 0x00


M1PCA00-0008

Context configuration CONTEXT_CONF 15 R/W/

E_P [51:37] All’0’ All’0’ All’0’

Packed command status PACKED_COMMAND_STATUS 1 R [36] 0x00 0x00 0x00

Packed command failure

index PACKED_FAILURE_INDEX 1 R [35] 0x00 0x00 0x00

Power Off Notification POWER_OFF_NOTIFICATION 1 R/W/

E_P [34] 0x00 0x00 0x00

Control to turn the Cache

ON/OFF CACHE_CTRL 1

R/W/

E_P [33] 0x00 0x00 0x00

Flushing of the cache FLUSH_CACHE 1 W/E_P [32] 0x00 0x00 0x00

Mode config MODE_CONFIG 1 R/W/E_

P [30] Nonsupp

ort

Nonsupp

ort 0x00

FFU status FFU_STATUS 1 R [26]

Nonsupp

ort

Nonsupp

ort 0x00

Pre loading data size PRE_LOADING_DATA_SIZE 4 R/W/E_

P [25:22] Nonsupp

ort

Nonsupp

ort

0x00758

000

Max pre loading data size MAX_PRE_LOADING_DATA_

SIZE

4 R [21:18] Nonsupp

ort

Nonsupp

ort

0x00758

000

Product state awareness

enablement PRODUCT_STATE_

AWARENESS_ENABLEMENT

1 R/W/E & R

[17] Nonsupp

ort

Nonsupp

ort 0x03

Secure Removal Type SECURE_REMOVAL_TYPE 1 R/W & R

[16] Nonsupp

ort

Nonsupp

ort 0x09

(*1) These functions are obsolete in JEDEC V4.5. TOSHIBA e-MMCTM

V4.41 and V4.41α supports them.


M1PCA00-0008

34 Unsupported register fields (V4.41α, V4.5 and V5.0)

TOSHIBA’s e-MMCTM

V4.41α, V4.5 and V5.0 does not support the following

functions defined in JEDEC V5.0. Table 48 shows the related register fields and

behavior when the host accesses it.

Table 48: Nonsupport register fields

Register Position Cell Type behavior Default

Value V4.41α V4.5 V5.0

EXT_CSD

[127:64]

VENDOR_SPECIFIC_

FIELD

<vendor

specific>

Please don’t access to these fields without TOSHIBA recommendation.

<vendor

specific>

Nonsupport Nonsupport Support

EXT_CSD [187] POWER_CLASS R/W/E_P

Some products don’t support it

and the device doesn’t return

any error if the host accesses it.

0x00

Nonsupport Nonsupport Nonsupport

EXT_CSD [132] TCASE_SUPPORT W/E_P

Host can access these fields according to the cell types without any error, but each function is disabled.

0x00 Nonsupport Nonsupport Nonsupport

EXT_CSD [131] PERIODIC_WAKEUP

R/W/E 0x00 Nonsupport Nonsupport Nonsupport

EXT_CSD [59] CLASS_6_CTRL R/W/E_P 0x00 Nonsupport Support Support

EXT_CSD

[53:52]

EXT_PARTITIONS_ATT

RIBUTE

R/W 0x00


EXT_CSD [51:37] CONTEXT_CONF

R/W/E_P 0x00 Nonsupport Support Support

EXT_CSD [33] CACHE_CTRL R/W/E_P 0x00 Nonsupport Nonsupport Support

EXT_CSD [32] FLUSH_CACHE W/E_P 0x00 Nonsupport Nonsupport Support

EXT_CSD [29]MODE_OPERATION

_CODES W/E_P Device will return switch error. 0x00




and readable.

R/W/E: Multiple writable with value kept after power failure, H/W reset assertion and any CMD0 reset and

readable.


and not readable.

R/W/C_P: Writable after value cleared by power failure and HW/reset assertion (the value is not cleared by

CMD0 reset) and readable.


M1PCA00-0008

35 Remark on the value of [192]EXT_CSD_REV in EXT_CSD

register

Table 49: EXT_CSD_REV [192]

JEDEC Specified Default Value

Value Extended CSD Revision 19nm V4.41α 19nm V4.5 A19nm V5.0

(0x06) (0x06) (0x07)

255-8 Reserved

7 Revision 1.7 (for MMC v5.0) ✓

6 Revision 1.6 (for MMC v4.5) ✓ ✓

5 Revision 1.5 (for MMC v4.41)

4 Revision 1.4 (Obsolete)





Linux kernel might check if the value of EXT_CSD[192]EXT_CSD_REV is

suitable for the kernel itself or not and return the initialize error when the device

indicates JEDEC/MMCA V5.0 or later because the old kernel version does not

support V5.0.

In case of V4.41α and V4.5 device, EXT_CSD[192]EXT_CSD_REV indicates

0x06 that means V4.5.

If the Host could not initialize the V4.41α or V4.5 device, Host should modify

the treatment of EXT_CSD[192]EXT_CSD_REV to accept V4.5 or use Linux

kernel release 3.1 or later that can initialize V4.41α or V4.5 device.


M1PCA00-0008

36 Remark on the value of [196]DEVICE_TYPE in EXT_CSD

register

Table 50: DEVICE_TYPE [196]

JEDEC Specified Default Value

Bit

slice Device Type

19nm V4.41α 19nm V4.5 A19nm V5.0

(0x17) (0x17) (0x57)

7 HS400 Dual Data Rate e•MMC @ 200MHz – 1.2V I/O 0 0 0

6 HS400 Dual Data Rate e•MMC @ 200MHz – 1.8V I/O 0 0 1

5 HS200 Single Data Rate e•MMC @ 200 MHz - 1.2V I/O 0 0 0

4 HS200 Single Data Rate e•MMC @ 200 MHz - 1.8V I/O 1 1 1

3 High-Speed Dual Data Rate e•MMC @ 52MHz - 1.2V I/O 0 0 0

2 High-Speed Dual Data Rate e•MMC @ 52MHz - 1.8V or 3V I/O 1 1 1

1 High-Speed e•MMC @ 52MHz - at rated device voltage(s) 1 1 1

0 High-Speed e•MMC @ 26MHz - at rated device voltage(s) 1 1 1

TOSHIBA’s e-MMCTM

V4.41α and V4.5 support HS200 under condition of

only 1.8V IO.

TOSHIBA’s e-MMCTM

V5.0 support HS400 under condition of only 1.8V IO.

Linux kernel might be check EXT_CSD[196]DEVCE_TYPE in order to

configure Host I/F itself.

But some host could not set Bus mode correctly because it fail to decode this

field.

Table 51 shows the bus setting that determined from the combination of

EXT_CSD[196]DEVICE_TYPE and Linux kernel version.

e.g., Linux e-MMCTM

driver configure TOSHIBA’s e-MMCTM

V4.41α or V4.5

into SDR52 or SDR200 mode if Host’s H/W doesn’t support HS200 with Linux

kernel 3.3.

It doesn’t comply with standards because High speed interface timing mode

doesn’t support over 52MHz CLK.


M1PCA00-0008

Table 51: Bus mode setting by Linux Kernel 3.0-3.9,3.0 and [196]DEVCE_TYPE

Linux Kernel

ver.

Supported Bus

by HOST

Supported Bus

by e-MMC (EXT_CSD[196]DEVICE_TYPE) The result of Bus setting Ideal Bus setting

Bus

Mode Voltage HEX

Bit decode

Bit

5

Bit

4

Bit

3

Bit

2

Bit

1

Bit

0 Speed Voltage Speed Voltage

3.0～3.2

HS200 doesn't

supported

HS200

DDR52

SDR52

1.8V

3.3V

1.2V

0x3F 1 1 1 1 1 1 DDR52 1.8V/3.3V *1 DDR52 1.2V

0x1F 0 1 1 1 1 1 DDR52 1.8V/3.3V *1 DDR52 1.2V

0x17 0 1 0 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

0x0F 0 0 1 1 1 1 DDR52 1.8V/3.3V *1 DDR52 1.2V

0x07 0 0 0 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

1.8V

3.3V

0x3F 1 1 1 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

0x1F 0 1 1 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

0x17 0 1 0 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

0x0F 0 0 1 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

0x07 0 0 0 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

DDR52

SDR52

1.8V

3.3V

1.2V

0x3F 1 1 1 1 1 1 DDR52 1.8V/3.3V *1 DDR52 1.2V

0x1F 0 1 1 1 1 1 DDR52 1.8V/3.3V *1 DDR52 1.2V

0x17 0 1 0 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

0x0F 0 0 1 1 1 1 DDR52 1.8V/3.3V *1 DDR52 1.2V

0x07 0 0 0 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

1.8V

3.3V

0x3F 1 1 1 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

0x1F 0 1 1 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

0x17 0 1 0 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

0x0F 0 0 1 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

0x07 0 0 0 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

3.3～

HS200

supported

HS200

DDR52

SDR52

1.8V

3.3V

1.2V

0x3F 1 1 1 1 1 1 HS200 1.2V HS200 1.2V

0x1F 0 1 1 1 1 1 HS200 1.8V HS200 1.8V

0x17 0 1 0 1 1 1 HS200 1.8V HS200 1.8V

0x0F 0 0 1 1 1 1 DDR52 1.8V/3.3V *1 DDR52 1.2V

0x07 0 0 0 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

1.8V

3.3V

0x3F 1 1 1 1 1 1 HS200 1.8V HS200 1.8V

0x1F 0 1 1 1 1 1 HS200 1.8V HS200 1.8V

0x17 0 1 0 1 1 1 HS200 1.8V HS200 1.8V

0x0F 0 0 1 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

0x07 0 0 0 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

DDR52M

SDR52M

1.8V

3.3V

1.2V

0x3F 1 1 1 1 1 1 SDR52 *2 1.8V/3.3V *1 DDR52 1.2V

0x1F 0 1 1 1 1 1 SDR52 *2 1.8V/3.3V *1 DDR52 1.2V

0x17 0 1 0 1 1 1 SDR52 *2 1.8V/3.3V DDR52 1.8V/3.3V

0x0F 0 0 1 1 1 1 DDR52 1.8V/3.3V *1 DDR52 1.2V

0x07 0 0 0 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

1.8V

3.3V

0x3F 1 1 1 1 1 1 SDR52 *2 1.8V/3.3V DDR52 1.8V/3.3V

0x1F 0 1 1 1 1 1 SDR52 *2 1.8V/3.3V DDR52 1.8V/3.3V

0x17 0 1 0 1 1 1 SDR52 *2 1.8V/3.3V DDR52 1.8V/3.3V

0x0F 0 0 1 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

0x07 0 0 0 1 1 1 DDR52 1.8V/3.3V DDR52 1.8V/3.3V

*1 : Host system set bus mode with 1.8V or 3.3V instead of 1.2V.

*2 : Host system set bus mode with SDR52 instead of DDR52.

*HS400 mode is not supported by the Linux Kernel 3.0-3.9.


M1PCA00-0008

Following is an example how the host correct the Linux MMC driver source

code.

Motif Kernel : Kernel.org, version 3.3 (URL:https://www.kernel.org/)

Target C file : drivers/mmc/core/mmc.c

Bold/Italic character : Proposed amendment

Function : mmc_read_ext_csd()

If e-MMCTM

supported DDR52 mode, set “EXT_CSD_CARD_TYPE_SDR_

ALL_DDR_52” into “card->ext_csd.card_type”.

static int mmc_read_ext_csd(struct mmc_card *card, u8 *ext_csd) { switch (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_MASK) { …. card->ext_csd.card_type = EXT_CSD_CARD_TYPE_SDR_200;

card->ext_csd.card_type |= (ext_csd[EXT_CSD_CARD_TYPE]& /* Added */ EXT_CSD_CARD_TYPE_SDR_ALL_DDR_52); /* Added */

…. card->ext_csd.card_type = EXT_CSD_CARD_TYPE_SDR_1_2V;

card->ext_csd.card_type |= (ext_csd[EXT_CSD_CARD_TYPE]& /* Added */ EXT_CSD_CARD_TYPE_SDR_ALL_DDR_52); /* Added */

…. card->ext_csd.card_type = EXT_CSD_CARD_TYPE_SDR_1_2V;

card->ext_csd.card_type |= (ext_csd[EXT_CSD_CARD_TYPE]& /* Added */ EXT_CSD_CARD_TYPE_SDR_ALL_DDR_52); /* Added */ …. }

https://www.kernel.org/


M1PCA00-0008

Function : mmc_init_card()

If Host doesn’t support HS200 mode, set fixed value “52000000” into “card-

>ext_csd.hs_max_dtr”.

Function : mmc_init_card()

If Host support HS200 mode, added the condition “host->f_max > 104000000”.

static int mmc_init_card(struct mmc_host *host, u32 ocr, struct mmc_card *oldcard) { …. /* * Activate high speed (if supported) */ if (card->ext_csd.hs_max_dtr != 0) { …. if (err) { …. } else { if (card->ext_csd.hs_max_dtr > 52000000 && host->caps2 & MMC_CAP2_HS200) { …. } else {

if (card->ext_csd.hs_max_dtr > 52000000) { /* Added */ card->ext_csd.hs_max_dtr = 52000000; /* Added */ } /* Added */ …. }

static int mmc_init_card(struct mmc_host *host, u32 ocr, struct mmc_card *oldcard) { …. /* * Activate high speed (if supported) */ if (card->ext_csd.hs_max_dtr != 0) { err = 0; if (card->ext_csd.hs_max_dtr > 52000000 &&

host->f_max > 104000000 && /* Added */ host->caps2 & MMC_CAP2_HS200) …. if (err) { …. } else { if (card->ext_csd.hs_max_dtr > 52000000 &&

host->f_max > 104000000 && /* Added */ host->caps2 & MMC_CAP2_HS200) { …. }


M1PCA00-0008

37 Remark on the potential bug of Linux e-MMC driver in data

write operation (V4.41α or V4.5)

The e-MMC device might report an error (as examples, write protect violation,

out of range, address misalignment, internal error) in block write operation. A

host driver shall handle these kinds of error by checking the response of CMD

12 and CMD 13.

However current error handling of Linux MMC driver is not adequate for block

write operation. A host might pass over an error in block write operation.

In this chapter, it explains this program failure scenario and shows a workaround.

The following figures are program failure scenario and show the points of retry

write operation.

If an internal program failure occurred, Toshiba e-MMC informs “General Error” in

CMD12/CMD13 response. A host shall check the response and retry write

operation when the device returns this kind of error.

Toshiba strongly recommend adding error handling code which checks device

status and retries write operation if the data write operation fails.


M1PCA00-0008

The following flows show the implementation of avoidance write failure.

Case A & B & C: Open-ended Multiple block write

Case D: Single block write / Multiple block write with pre-defined


M1PCA00-0008

The following code is an example (Bold line) of retry function in e-MMC

driver based on the kernel ver.3.0.69 in https://www.kernel.org/.

(drivers\mmc\block.c) This is a just sample. So after applying this sample into

your e-MMC driver, please evaluate e-MMC driver on your system.

static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *req) { struct mmc_blk_data *md = mq->data; struct mmc_card *card = md->queue.card; struct mmc_blk_request brq; int ret = 1, disable_multi = 0; int data_err_retry = 0, gen_err = 0;

/* ADDED */ /* * Reliable writes are used to implement Forced Unit Access and * REQ_META accesses, and are supported only on MMCs. */ bool do_rel_wr = ((req->cmd_flags & REQ_FUA) || (req->cmd_flags & REQ_META)) && (rq_data_dir(req) == WRITE) && (md->flags & MMC_BLK_REL_WR); do { struct mmc_command cmd = {0}; u32 readcmd, writecmd, status = 0; memset(&brq, 0, sizeof(struct mmc_blk_request)); brq.mrq.cmd = &brq.cmd; brq.mrq.data = &brq.data; brq.cmd.arg = blk_rq_pos(req); if (!mmc_card_blockaddr(card)) brq.cmd.arg <<= 9; brq.cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC; brq.data.blksz = 512; brq.stop.opcode = MMC_STOP_TRANSMISSION; brq.stop.arg = 0; brq.stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC; brq.data.blocks = blk_rq_sectors(req); /* * The block layer doesn't support all sector count * restrictions, so we need to be prepared for too big * requests. */ if (brq.data.blocks > card->host->max_blk_count) brq.data.blocks = card->host->max_blk_count; /* * After a read error, we redo the request one sector at a time * in order to accurately determine which sectors can be read * successfully. */ if (disable_multi && brq.data.blocks > 1) brq.data.blocks = 1; if (brq.data.blocks > 1 || do_rel_wr) { /* SPI multiblock writes terminate using a special * token, not a STOP_TRANSMISSION request. */ if (!mmc_host_is_spi(card->host) || rq_data_dir(req) == READ) brq.mrq.stop = &brq.stop; readcmd = MMC_READ_MULTIPLE_BLOCK; writecmd = MMC_WRITE_MULTIPLE_BLOCK; } else { brq.mrq.stop = NULL; readcmd = MMC_READ_SINGLE_BLOCK; writecmd = MMC_WRITE_BLOCK; } if (rq_data_dir(req) == READ) { brq.cmd.opcode = readcmd; brq.data.flags |= MMC_DATA_READ; } else { brq.cmd.opcode = writecmd; brq.data.flags |= MMC_DATA_WRITE; }

https://www.kernel.org/


M1PCA00-0008

if (do_rel_wr) mmc_apply_rel_rw(&brq, card, req); /* * Pre-defined multi-block transfers are preferable to * open ended-ones (and necessary for reliable writes). * However, it is not sufficient to just send CMD23, * and avoid the final CMD12, as on an error condition * CMD12 (stop) needs to be sent anyway. This, coupled * with Auto-CMD23 enhancements provided by some * hosts, means that the complexity of dealing * with this is best left to the host. If CMD23 is * supported by card and host, we'll fill sbc in and let * the host deal with handling it correctly. This means * that for hosts that don't expose MMC_CAP_CMD23, no * change of behavior will be observed. * * N.B: Some MMC cards experience perf degradation. * We'll avoid using CMD23-bounded multiblock writes for * these, while retaining features like reliable writes. */ if ((md->flags & MMC_BLK_CMD23) && mmc_op_multi(brq.cmd.opcode) && (do_rel_wr || !(card->quirks & MMC_QUIRK_BLK_NO_CMD23))) { brq.sbc.opcode = MMC_SET_BLOCK_COUNT; brq.sbc.arg = brq.data.blocks | (do_rel_wr ? (1 << 31) : 0); brq.sbc.flags = MMC_RSP_R1 | MMC_CMD_AC; brq.mrq.sbc = &brq.sbc; } mmc_set_data_timeout(&brq.data, card); brq.data.sg = mq->sg; brq.data.sg_len = mmc_queue_map_sg(mq); /* * Adjust the sg list so it is the same size as the * request. */ if (brq.data.blocks != blk_rq_sectors(req)) { int i, data_size = brq.data.blocks << 9; struct scatterlist *sg; for_each_sg(brq.data.sg, sg, brq.data.sg_len, i) { data_size -= sg->length; if (data_size <= 0) { sg->length += data_size; i++; break; } } brq.data.sg_len = i; } mmc_queue_bounce_pre(mq); mmc_wait_for_req(card->host, &brq.mrq); mmc_queue_bounce_post(mq); /* * Check for errors here, but don't jump to cmd_err * until later as we need to wait for the card to leave * programming mode even when things go wrong. */ if (brq.sbc.error || brq.cmd.error || brq.data.error || brq.stop.error) { if (brq.data.blocks > 1 && rq_data_dir(req) == READ) { /* Redo read one sector at a time */ printk(KERN_WARNING "%s: retrying using single " "block read\n", req->rq_disk->disk_name); disable_multi = 1; continue; } status = get_card_status(card, req); }


M1PCA00-0008

if (brq.sbc.error) { printk(KERN_ERR "%s: error %d sending SET_BLOCK_COUNT " "command, response %#x, card status %#x\n", req->rq_disk->disk_name, brq.sbc.error, brq.sbc.resp[0], status); } if (brq.cmd.error) { printk(KERN_ERR "%s: error %d sending read/write " "command, response %#x, card status %#x\n", req->rq_disk->disk_name, brq.cmd.error, brq.cmd.resp[0], status); } if (brq.data.error) { if (brq.data.error == -ETIMEDOUT && brq.mrq.stop) /* 'Stop' response contains card status */ status = brq.mrq.stop->resp[0]; printk(KERN_ERR "%s: error %d transferring data," " sector %u, nr %u, card status %#x\n", req->rq_disk->disk_name, brq.data.error, (unsigned)blk_rq_pos(req), (unsigned)blk_rq_sectors(req), status); } if (brq.stop.error) { printk(KERN_ERR "%s: error %d sending stop command, " "response %#x, card status %#x\n", req->rq_disk->disk_name, brq.stop.error, brq.stop.resp[0], status); } if (!mmc_host_is_spi(card->host) && rq_data_dir(req) != READ) { /* Check stop command (CMD12) response */ /* ADDED */ if (brq.mrq.stop && (brq.mrq.stop->resp[0] & R1_ERROR)) { /* ADDED */ if ( data_err_retry++ < 5 ) /* ADDED */ continue; /* ADDED */ goto cmd_abort; /* ADDED */ } /* ADDED */ do { int err; cmd.opcode = MMC_SEND_STATUS; cmd.arg = card->rca << 16; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; err = mmc_wait_for_cmd(card->host, &cmd, 5); if (err) { printk(KERN_ERR "%s: error %d requesting status\n", req->rq_disk->disk_name, err); goto cmd_err; } if(cmd.resp[0] & R1_ERROR) /* ADDED */ gen_err = 1; /* ADDED */ /* * Some cards mishandle the status bits, * so make sure to check both the busy * indication and the card state. */ } while (!(cmd.resp[0] & R1_READY_FOR_DATA) || (R1_CURRENT_STATE(cmd.resp[0]) == 7)); /* if error occur, retry operation executes */ /* ADDED */ if(gen_err) { /* ADDED */ gen_err=0; /* ADDED */ if (data_err_retry++ < 5) /* ADDED */ continue; /* ADDED */ goto cmd_abort; /* ADDED */ } /* ADDED */


M1PCA00-0008

In this sample, if you issue CMD12, you have to check the status of response

of CMD12 before you issue CMD13. And please confirm your host driver sets

the response of CMD 12 to “brq.mrq.stop->resp”.

#if 0 if (cmd.resp[0] & ~0x00000900) printk(KERN_ERR "%s: status = %08x\n", req->rq_disk->disk_name, cmd.resp[0]); if (mmc_decode_status(cmd.resp)) goto cmd_err; #endif } if (brq.cmd.error || brq.stop.error || brq.data.error) { if (rq_data_dir(req) == READ) { /* * After an error, we redo I/O one sector at a * time, so we only reach here after trying to * read a single sector. */ spin_lock_irq(&md->lock); ret = __blk_end_request(req, -EIO, brq.data.blksz); spin_unlock_irq(&md->lock); continue; } goto cmd_err; } /* * A block was successfully transferred. */ spin_lock_irq(&md->lock); ret = __blk_end_request(req, 0, brq.data.bytes_xfered); spin_unlock_irq(&md->lock); } while (ret); return 1; cmd_err: /* * If this is an SD card and we're writing, we can first * mark the known good sectors as ok. * * If the card is not SD, we can still ok written sectors * as reported by the controller (which might be less than * the real number of written sectors, but never more). */ if (mmc_card_sd(card)) { u32 blocks; blocks = mmc_sd_num_wr_blocks(card); if (blocks != (u32)-1) { spin_lock_irq(&md->lock); ret = __blk_end_request(req, 0, blocks << 9); spin_unlock_irq(&md->lock); } } else { spin_lock_irq(&md->lock); ret = __blk_end_request(req, 0, brq.data.bytes_xfered); spin_unlock_irq(&md->lock); } cmd_abort; /* ADDED */ spin_lock_irq(&md->lock); while (ret) ret = __blk_end_request(req, -EIO, blk_rq_cur_bytes(req)); spin_unlock_irq(&md->lock); return 0; }


M1PCA00-0008

38 Recommended power-on sequence

TOSHIBA 19nm and A19nm e-MMC Ver.4.41α or later defined the minimum of

tPRUH / tPRUL specification in order to avoid the rush-current into by-pass

capacitance in systems side during Power-on.

Table 52: Power Supply Voltage and tPRU

Parameter Symbol Test Conditions Min Max Unit

Supply voltage 1 VCC 2.7 3.6

Supply voltage 2 VccQ 1.7 1.95

2.7 3.6

Supply power-up for 3.3V tPRUH 5 μs 35 ms

Supply power-up for 1.8V tPRUL 5 μs 25 ms

Figure 44: Power up sequence

0.5V

VccQ

min

VccQ

max

Vcc

min

Vcc

max

Vcc

Power up time

tPRUH V

ccq Power up time

tPRUL V

ccq Powe up time

tPRUL

time

Supply voltage


M1PCA00-0008

39 Recommended sequence when power-down only VCC.

TOSHIBA recommends that Host issue CMD5(Sleep) before switched off only

Vcc power supply in order to minimize the power consumption of the memory device.

Host can wake-up the device by issuing CMD5(Awake).

39.1 Sleep/Awake related command

Table 53: Sleep/Awake related command


CMD5 SLEEP_AWAKE

Toggles the card between Sleep state and Standby state.

Sleep command: The bit 15 as set to 1

Awake command: The bit 15 as set to 0

39.2 Sleep/Awake related register fields

Table 54: Sleep/Awake related register fields


Type Explanation

Default

Value

EXT_CSD [217] S_A_TIMEOUT. R

This register defines the max timeout value for state transitions from Standby state (stby) to Sleep state(slp) and from Sleep state (slp) to Standby state (stby).

Depend

on the

device

EXT_CSD [220] S_C_VCC R This register define the max VCC current consumption during the Sleep state (slp).

Depend

on the

device

EXT_CSD [219] S_C_VCCQ R This register define the max VCCQ current consumption during the Sleep state (slp).

Depend

on the

device

R: Read only.


M1PCA00-0008

39.3 Sleep/Awake sequence

Figure 45 shows the CMD sequence of Sleep/Awake and Vcc power-down

sequence.

Figure 45: Sleep/Awake sequence

CLK

Vcc

CMD CMD7

CMD5

RES CMD5

RES CMD7

(SELECT) RES

(DESELECT) (SLEEP) (AWAKE)

DAT0

Transfer State Stand-by State Sleep State Stand-by State


M1PCA00-0008

40 Supported command set

40.1 Basic Commands (class 0)

Table 55: Basic Commands (class 0)

CMD Index Argument Abbreviations Command Descriptions

CMD0

[31:0] 00000000 GO_IDLE_STATE Resets the Device to idle state

[31:0] F0F0F0F0 GO_PRE_IDLE_ST

ATE Resets the Device to pre-idle state

[31:0] FFFFFFFA BOOT_INITIATIO

N Initiate alternative boot operation

CMD1

[31:0] OCR

without

busy

SEND_OP_COND

Asks the Device, in idle state, to send its

Operating Conditions Register contents in the

response on the CMD line.

CMD2 [31:0] stuff bits ALL_SEND_CID Asks the Device to send its CID number on the

CMD line.

CMD3 [31:16] RCA

[15:0] stuff bits

SET_RELATIVE_

ADDR Assigns relative address to the Device

CMD4 [31:16] DSR

[15:0] stuff bits SET_DSR Not support DSR Register

CMD5

[31:16] RCA

[15] Sleep/Awake

[14:0] stuff bits

SLEEP_AWAKE Toggles the Device between Sleep state and

Standby state.

CMD6

[31:26] Set to 0

[25:24] Access

[23:16] Index

[15:8] Value

[7:3] Set to 0

[2:0] Cmd Set

SWITCH Switches the mode of operation of the selected

Device or modifies the EXT_CSD registers.

CMD7 [31:16] RCA

[15:0] stuff bits

SELECT/DESELEC

T_CARD

Command toggles a device between the

standby and transfer states or between the

programming and disconnect states. In both

cases the Device is selected by its own relative

address and gets deselected by any other

address; address 0 deselects the Device.

CMD8 [31:0] stuff bits SEND_EXT_CSD The Device sends its EXT_CSD register as a

block of data.

CMD9 [31:16] RCA

[15:0] stuff bits SEND_CSD

Addressed Device sends its Device-specific

data

(CSD) on the CMD line.

CMD10 [31:16] RCA

[15:0] stuff bits SEND_CID

Addressed Device sends its Device

identification

(CID) on CMD the line.

CMD12

[31:16] RCA

[15:1] stuff bits

[0] HPI

STOP_

TRANSMISSION

Forces the Device to stop transmission.

If HPI flag is set the device shall interrupt its

internal operations in a well-defined timing.

CMD13

[31:16] RCA

[15:1] stuff bits

[0] HPI

SEND_STATUS

Addressed Device sends its status register.

If HPI flag is set the device shall interrupt its

internal operations in a well-defined timing.

CMD14 [31:0] stuff bits BUSTEST_R A host reads the reversed bus testing data

pattern from a Device.

CMD15 [31:16] RCA

[15:0] stuff bits

GO_INACTIVE_

STATE Sets the Device to inactive state

CMD19 [31:0] stuff bits BUSTEST_W Not support Bus Test


M1PCA00-0008

40.2 Read Related Commands (class 2)

Table 56: Read Related Commands (class 2)


CMD16 [31:0] block length SET_BLOCKLEN

Sets the block length (in bytes) for all

following block commands (read and write).

Default block length is specified in the CSD.

CMD17 [31:0] data

address1

READ_SINGLE_

BLOCK

Reads a block of the size selected by the

SET_BLOCKLEN command.2

CMD18 [31:0] data

address1

READ_MULTIPLE

_BLOCK

Continuously transfers data blocks from

Device to host until interrupted by a stop

command, or the requested number of data

blocks is transmitted. If sent as part of a packed

read command, the argument shall contain the

first read data address in the pack (address of

first individual read command inside the pack).

CMD21 [31:0] stuff bits SEND_TUNING_B

LOCK

128 clocks of tuning pattern (64 bytes in 4 bit

mode or 128 bytes in 8 bit mode) are sent for

HS200 optimal sampling point detection.

NOTE 1. Data address for media =<2GB is a 32bit byte address and data address for media > 2GB is a

32bit sector (512B) address.

NOTE 2. The transferred data must not cross a physical block boundary, unless

READ_BLK_MISALIGN is set in the CSD register.

40.3 Write Related Commands (class 4)

Table 57: Write Related Commands (class 4)


CMD23

(default)

[31] Reliable Write

Request

[30] ‘0’ non-

packed

[29] tag request4

[28:25] context ID4

[24] forced

programming4

[23:16] set to 0

[15:0] number of

blocks

SET_BLOCK_COU

NT

Non-packed command version

Defines the number of blocks (read/write) and

the reliable write parameter (write) for a block

read or write command.

May contain a tag request or a context ID. Tag

and Context ID cannot be used together in the

same command, if one is used the other must

be set to zero.

The context ID is an identifier (0 to 15) that

associates the read/write command with the

specific context.

When bit 24 is set to 1, forced programming

enabled, data shall be forcefully programmed

to non-volatile storage instead of volatile cache

while cache is turned ON.


M1PCA00-0008

CMD23

(packed)

[31] set to 0

[30] ‘1’ packed

[29:16] set to 0

[15:0] number of

blocks

SET_BLOCK_COU

NT

Packed command version

Defines the number of blocks (read/write) for

the following packed write command or for the

header of the following packed read command.

For packed write commands, the number of

blocks should include the total number of

blocks all packed commands plus one for the

header block.

For packed read commands, the number of

blocks should equal one as only the header is

sent inside the following CMD25. After that, a

separate normal read command is sent to get

the packed data.

CMD24 [31:0] data

address1

WRITE_BLOCK Writes a block of the size selected by the

SET_BLOCKLEN command.2

CMD25 [31:0] data

address1

WRITE_MULTIPL

E_BLOCK

Continuously writes blocks of data until a

STOP_TRANSMISSION follows or the

requested number of block received.

If sent as a packed command (either packed

write, or the header of packed read) the

argument shall contain the first read/write data

address in the pack (address of first individual

command inside the pack).

CMD26 [31:0] stuff bits PROGRAM_CID

Programming of the Device identification

register. This command shall be issued only

once. The Device contains hardware to prevent

this operation after the first programming.

Normally this command is reserved for the

manufacturer.

CMD27 [31:0] stuff bits PROGRAM_CSD Programming of the programmable bits of the

CSD.

CMD493 [31:0] stuff bits SET_TIME

Sets the real time clock according to the RTC

information in the 512B data block.



NOTE 2. The transferred data must not cross a physical block boundary unless

WRITE_BLK_MISALIGN is set in the CSD.

NOTE 3. TOSHIBA’s e-MMCTM

V4.41α,V4.5 and V5.0 doesn’t support CMD49. The device shall return

R1 response with no error and there is no functional operation if the host issues CMD49.

NOTE 4. TOSHIBA’s e-MMCTM

V4.41α doesn’t support data tag, context ID and forced programming in

JEDEC V4.5. CMD23 argument bit[29:24] are ignored.

TOSHIBA’s e-MMCTM

V4.5 and later support data tag. Tag size is more than 0.1% of User Area Size, e-

MMC will report with EXCEPTION_EVENT bit in Device Status in R1 response & SYSPOOL

EXHAUSTED=1(EXT_CSD[54])


M1PCA00-0008

40.4 Erase Related Commands (class 5)

Table 58: Erase Related Commands (class 5)


CMD35 [31:0] data

address1,2

ERASE_GROUP_S

TART

Sets the address of the first erase group

within a range to be selected for erase

CMD36 [31:0] data

address1,2

ERASE_GROUP_E

ND

Sets the address of the last erase group

within a continuous range to be

selected for erase

CMD38

[31] Secure

request4

[30:16] set to 0

[15] Force Garbage Collect request

4

[14:2] set to 0

[1] Discard Enable

[0] Identify Write

Blocks for Erase

(or TRIM Enable)

ERASE

Erases all previously selected write blocks

according to argument bits3

When all argument bits are zero CMD38 will

perform an erase on erase group(s).

When Bit 0 = 1 and Bit 1=0 then CMD38 will

perform a TRIM on the sector(s).

When Bit 0 =1 and Bit 1=1 then CMD38 will perform a DISCARD on the sector(s)

To maintain backward compatibility the device

must not report an error if bits 31 and 15 are

set. The device behavior when these are set is

undefined.

All other argument settings should trigger an

ERROR.



NOTE 2. The Device will ignore all LSB’s below the Erase Group size, effectively rounding the address

down to the Erase Group boundary.

NOTE 3. Table 11 on page 55 in JESD84-B50 give a description of the argument bits and a list of

supported argument combinations.

NOTE 4. Argument bit 15 is an optional feature that is only supported if SEC_GB_CL_EN

(EXT_CSD[231] bit 4) is set. Argument bit 31 is an optional feature that is only supported if

SEC_ER_EN (EXT_CSD[231] bit 0) is set


M1PCA00-0008

40.5 Write protection Related Commands (class 6)

Table 59: Write protection Related Commands (class 6)


CMD28 [31:0] data

address1

SET_WRITE_PRO

T

If CLASS_6_CTRL=0x00:

If the device has write protection features, this

command sets the write protection bit of the

addressed group. The properties of write

protection are coded in the device specific data

(WP_GRP_SIZE or HC_WP_GRP_SIZE).


This command releases the specified addressed

group.

CMD29 [31:0] data

address1

CLR_WRITE_PRO

T


If the device provides write protection features,

this command clears the write protection bit of

the addressed group.


This command is ignored.

CMD30 [31:0] write protect

data address

SEND_WRITE_PR

OT


If the device provides write protection features,

this command asks the device to send the status

of the write protection bits.2


This command asks the device to send the

status of released groups. A bit ‘0’ means the

specific group is valid and accessible, a bit ‘1’

means the specific group was released and it

cannot be used.3

CMD31 [31:0] write protect

data address

SEND_WRITE_PR

OT_TYPE


This command sends the type of write

protection that is set for the different write

protection groups.4


This command returns a fixed pattern of 64-bit

zeros in its payload.


M1PCA00-0008




followed by 16 CRC bits are transferred in a payload format via the data lines. The last (least significant)

bit of the protection bits corresponds to the first addressed group. If the addresses of the last groups are

outside the valid range, then the corresponding write protection bits shall be set to zero.

NOTE 3. 32 released status bits (representing 32 write protect groups starting at the specified address)

followed by 16 CRC bits are transferred in a payload format via the data lines. The last (least significant)

bit of the released bits corresponds to the first addressed group. If the addresses of the last groups are

outside the valid range, then the corresponding released bits shall be set to zero.


followed by 16 CRC bits are transferred in a payload format via the data lines. Each set of two protection

bits shows the type of protection set for each of the write protection groups. The definition of the different

bit settings are shown below. The last (least significant) two bits of the protection bits correspond to the

first addressed group. If the addresses of the last groups are outside the valid range, then the

corresponding write protection bits shall be set to zero.

“00” Write protection group not protected

“01” Write protection group is protected by temporary write protection

“10” Write protection group is protected by power-on write protection

“11” Write protection group is protected by permanent write protection

40.6 Lock Related Commands (class 7)

Table 60: Lock Related Commands (class 7)


CMD42 [31:0] stuff bits. LOCK_UNLOCK

Used to set/reset the password or lock/unlock

the Device. The size of the data block is set by

the SET_BLOCK_LEN command.


M1PCA00-0008

41 Product List

Table 61: TOSHIBA e-MMCTM

Product List

Product Number Density Package Size JEDEC Version Process

THGBM5G9B8JBAIE 64GB 12x16x1.2mm

V4.41α 19nm

THGBM5G8B4JBAIM 32GB 12x16x1.0mm

THGBM5G7B2JBAIM 16GB 12x16x1.0mm

THGBM5G9A8JBAIG 64GB 11.5x13x1.2mm

THGBM5G8A4JBAIM 32GB 12x16x1.0mm

THGBM5G8A4JBAIR 32GB 11.5x13x1.0mm

THGBM5G7A2JBAIM 16GB 12x16x1.0mm




THGBMAG9B8JBAIE 64GB 12x16x1.2mm

V4.5 19nm

THGBMAG8B4JBAIM 32GB 12x16x1.0mm

THGBMAG7B2JBAIM 16GB 12x16x1.0mm

THGBMAG9A8JBA4G 64GB 11.5x13x1.2mm

THGBMAG8A4JBA4R 32GB 11.5x13x1.0mm

THGBMAG7A2JBAIR 16GB 11.5x13x1.0mm


THGBMAG6A2JBAIT 8GB 10x11x0.8mm


THGBMAG5A1JBAIT 4GB 10x11x0.8mm

THGBM7G9T8JBAIG 64GB 11.5x13x1.2mm

THGBM7G8T4JBAIR 32GB 11.5x13x1.0mm

THGBMBT0DBKBAIU 128GB 11.5x13x1.5 mm

V5.0 A19nm

THGBMBG9D8KBAIG 64GB 11.5x13x1.2 mm

THGBMBG8D4KBAIR 32GB 11.5x13x1.0 mm

THGBMBG7D2KBAIL 16GB 11.5x13x0.8 mm

THGBMBG6D1KBAIL 8GB 11.5x13x0.8 mm


M1PCA00-0008

References

JEDEC Solid State Technology Association (2011),

JEDEC STANDARD “EMBEDDED MULTI-MEDIA CARD (e•MMC), ELECTRICAL

STANDARD (5.0 Device), JESD84-B50

JEDEC STANDARD “EMBEDDED MULTI-MEDIA CARD (e•MMC), ELECTRICAL

STANDARD (4.5 Device), JESD84-B45


JEDEC STANDARD “Embedded MultiMediaCard(e•MMC) e•MMC/Card Product

Standard, High Capacity, including Reliable Write, Boot, Sleep Modes, Dual Data Rate,

Multiple Partitions Supports, Security Enhancement, Background Operation and High

Priority Interrupt (MMCA, 4.4.1) , JESD84-A441 ”


JEDEC STANDARD “Embedded MultiMediaCard(e-MMC) Mechanical Standard, with

Optional Reset Signal, JESD84-C44”

Document Revision History

Rev0.1 Mar 18th, 2010 Released as tentative revision.

Rev0.2 Mar 30th, 2011 Added JEDEC V4.41 descriptions.

Rev1.0 Apr. 7th, 2011 Released as the first revision for the V4.41.

Rev1.1 May. 20th, 2011 Update the Awake time (TC) of v4.4 and v4.41 product on Table 10

Added the 2GB product with 24nm process Added the hardware reset operation as a section 8.

Rev1.2 Mar 2nd

, 2012 Added 19nm products and JEDEC V4.41α descriptions.

Rev1.3 Mar 30th, 2012 Update V4.41α function on table 2.

Added the instructions of Boot Partition Write Protection in section 21 Added the Remark on the value of EXT_CSD [192]EXT_CSD_REV.

Rev1.4 Jul 12th, 2012 Update the Awake time (TC) of v4.41α product on Table 10

Added the Remark on the value of [192]EXT_CSD_REV in EXT_CSD register as a section 24. Added the Remark on the value of [196]DEVICE_TYPE in EXT_CSD register as a section 25. Added the power on sequence and Recommended sequence when power-down only VCC as a section 26, 27.

Rev1.5 Jan 21th, 2013 Added 19nm products and JEDEC V4.5 descriptions.

Update the Auto Sleep function.

Rev1.6 Mar 5th, 2013 Update the contents of Composition of an e-MMC System.

Rev1.61 Apr 8th, 2013 Added 3 Remark on the potential bug of Linux e-MMC driver in data

write operation Update the contents of Composition of an e-MMC

System as a section33.

Rev1.62 Apr 18th, 2013 Revised figure and code of section 33.

Rev1.7 Aug 26th, 2013 Added A19nm products and JEDEC V5.0 descriptions.

Rev1.71 Oct 7th, 2013 Revised figure and table based on JEDEC V5.0 official released

Version

Rev. 1.72 Dec 9th, 2013 Revised figure 46. (Deleted the capacitor of DS terminal)

Rev. 1.73 Jan 22nd

, 2014 Added definition for device life time estimation type A & B

Added driver strength register setting in HS400 timing mode selection


M1PCA00-0008

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customers use the Product, create designs including the Product, or incorporate the Product into their own applications,

customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including

without limitation, this document, the specifications, the data sheets and application notes for Product and the

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Application Note JEDEC e MMCTM Ver4.41α,Ver.4.5 … · 37 Remark on the potential bug of Linux...

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