A GSM / GPS Receiver With a Bandpass Sigma-DeltaAnalog to Digital Converter

T. Müller*, K. Boehm*, T. Hentschel*** Daimler-Chrysler Research Ulm, FT2/HM, Wilhelm-Runge-Str. 11, 89081 Ulm, Germany

e-mail: thomas.mu.mueller@DaimlerChrysler.com** Dresden University of Technology, Endowed Chair for Mobile Communications Systems

Abstract – In traffic telematic systems (route guidance, fleetmanagement etc.) vehicle-side terminals are required for thequasi-simultaneous reception of cellular phone (GSM) andsatellite navigation (GPS). A conventional approach uses twocomplete receivers for these two tasks. We describe a cost-saving solution for a combined receiver which relies on theTDM structure of the GSM signal. Our solution is based on anbandpass-sigma-delta ADC for IF digitizing

I. INTRODUCTION

The increasing traffic density causes problems which can bepartially solved by means of modern communication systems:Route guidance, collision notification, emergency call, stolenvehicle tracking, roadside assistance, fleet- and trafficmanagement as well as road pricing are tasks of traffictelematics. In traffic telematic systems vehicle-side terminalsare required for the quasi-simultaneous reception of cellularphone(GSM) and satellite navigation(GPS). A conventionalapproach uses two complete separate receivers for these twotasks. In order to reduce the complexity of the total set-up andtherefore achieve a reduction in volume, power and cost wepropose a solution with a combined receiver which relies on theTDM structure of the GSM signal.

II. SYSTEM ARCHITECTURE

The GPS and the GSM signals can be processed in the samesignal processing chain from the antennas down to thebaseband. This is possible due to the time division multiplexstructure of the GSM signal. The GSM needs 3/8 of theavailable time slots which leaves an approximately 50% dutycycle for GPS.The set-up is depicted in the schematic of Fig. 1: The signalsfrom the antennas (GPS=1.575GHz, GSM=.935-.960GHz) arebandpass-filtered in order to suppress strong out of band signalswhich could otherwise give rise to intermodulation or blockingin the preamplifier. After the preamps variable attenuators (upto 20 dB) can be activated by the system control. Two SAW-Filters help to suppress the image frequencies. A SPDT-switchserves for the time-duplexing of the two signals. The signals aremixed down to an IF of 43.875 MHz. The application of animage rejection mixer was impossible due to the largebandwidth (935MHz-1575MHz). Two separate local oscillators(LO) are switched alternately to the mixer (MotorolaMC13143). An improved version may be later on realized witha single, rapid settling (< 200 µs) LO. The mixer is followed bya SAW-filter (Siemens X6959M) with a bandwidth of 2MHz inorder to reduce intermodulation products in the variable gain

amplifier and to prevent aliasing in the ADC. For mobileapplications power consumption is a critical issue.

LO

BP

BP BP

Σ∆Mod.

Dec

imat

ion

GSM-base-band proc.Siemens

GPS-base-band proc.Plessey

system-control display, keyboard

0,1,0,-1

1,0,-1,0

BP BP

Fig. 1: System Arcchitecture of GSM/GPS receiver

For IF-digitizing the bandpass-Σ∆-ADC has the potential oflower power consumption compared with other ADCs [4], [5],[6], [7]. The choice of the IF is a compromise between therequirements on the ADC (low IF wanted) and the image-rejection filter (high IF wanted).We use subsampling in order to relax the requirements on theADC and the digital filters. However, the requirement on theaperture jitter of the ADC is increased by the square of thesubsampling ratio in the case of subsampling [9]. Furthermoreone has to consider that the noise in the baseband is increaseddue to aliasing. Therefore we use a moderate subsampling ratio:fif / fs =43.875 MHz / 19.5 MHz = 9/4. Due to the prefilteringwith an bandwidth of 2 MHz an instantaneous dynamic range of70 dB is sufficient for the ADC. The GSM specs require a(noninstantaneous) dynamic range of total 110 dB. Thedifference of 40 dB is supplied by the variable gain amplifierand the attenuators in the RF-part.In a first implementation (proof of concept) only the GPSbaseband processing is realized with a PC-based evaluationboard (12-channel receiver) from Plessey. From this board theRF-frontend is bypassed and the decimator output is connecteddirectly to the correlator chip GP 2021 on this board. The PC isused for control of the correlator, calculation of the coordinates,control of the VCO and the variable gain amplifier and othersystem control tasks.

III. THE Σ∆-MODULATOR

Because only one IF-filter of 2 MHz (BW) is used for thecombined reception of both standards (GPS, GSM), themodulator has to digitize the 200 kHz GSM-band with a SNRof 70 dB in the presence of strong interferers in the adjacentchannels. The maximum signal swing at the input is 400 mV ata fIF = 43.875 MHz and fS = 19.5 MHz. Fig. 2 shows the blockdiagram of the modulator architecture. It is an eighth order fourstage 2-2-2-2 cascade with a fourth order noise shaping functionand 1 bit quantizers in each stage. The modulator output Y(z) inthe Z-domain is described ideally after digital cancellation as:

Y(z) = z-8 X(z) + (1+z-2)4 Q(z)

where X(z) is the Z-transform of the signal and Q(z) thequantization error of the last stage.

The cascaded structure was chosen because of the absence ofstability problems and less internal gain which is necessary tomaximize the ratio between signal swing and supply voltageand to reduce the power consumption thereby. The internal gainincreases at higher orders and therefore the input signal swingmust be reduced to keep distortion low.

z-6 1+z-2

z-4 (1+z-2)2

z-2 (1+z-2)4

z-0 (1+z-2)6

Comp.-1/(1+z2)

DAC

+Track& Hold

Comp.-1/(1+z2)

DAC

+

Comp.-1/(1+z2)

DAC

+

Comp.-1/(1+z2)

DAC

+

+4 bit

In

Out

Fig. 2: Block diagram of the cascaded 8th order bandpass Σ∆ modulator

A. MeasurementsA typical output spectrum of the complete modulator with aclock frequency of 19.5 MHz, is shown in Fig. 3. Themodulator has been tested with several frequencies to separateeffects of dc errors and incomplete settling. The first stage alonegives a 37.5 dB SNR in a 200kHz bandwidth, 3 dB lower thanthe expected value, when clocked at the nominal 19.5 MHz.The input was a single tone with 200 mV amplitude at 43.875MHz.

The main performance parameters of the complete circuit aresummarized in Table 1

Table 1: Summary of Measured PerformanceSupply 5V, 180mW analog, 109mWdig.Clock Frequency 19.5 MHzInput signal Vpp= 0.4 Vpp @ 43.875 MHzSignal Bandwidth / OSR 200 kHz / 48.75SNR 37.5 dB (B=200 kHz )Active area 1.4 mm2 (dig) + 3.2 mm2 (anal.)Technology 0.8µm BiCMOS

Fig. 3: Measured output spectrum of the prototype

Although the prototype shows a high stability, themeasurements manifest that the quantization error of the firststage is not correctly decreased by the next stage. As a resultthe noise floor is higher than expected. The cascadedarchitecture is sensitive to component mismatches.

B. Intermodulation Measurements

The noise-shaping and the intermodulation characteristics of theΣ∆-converter behave different compared with analog parts likeamplifiers. Fig. 4 shows that the signal to noise ratio reaches itsmaximum at an input level of about –2dBm. The differentialinput of the modulator itself has a high-impedance with aparallel capacity of about 1.5pF but for measurement purposes ashunt of 100Ω has been connected parallel to the symmetricinput.The specifications of GSM prescribe the immunity of thereceiver against interferers. In our system concept therequirements are fulfilled by the combination of the IF filtersand intermodulation characteristics of the Σ∆-converter.

-10

-5

0

5

10

15

20

25

30

35

40

-50 -40 -30 -20 -10 0 10

input power [dBm]

Fig. 4: Measured signal to noise ratio in relationship to the input power

Fig. 5 shows the measured power of the output bitstream andthe harmonic products depending on the input power. The twolines about 22dB below the signal are intermodulation productsof the sampling frequency and the input signal. They limit the

maximum in-channel SNR of the converter. The otherintermodulation products stay about 40dB below the two input-tones. We assume that the internal non-linear behaviour ofthe Σ∆-modulator is the reason for the 3rd order intermodulationproducts.By adding a sine-dither with an amplitude of -10dBm outsidethe used spectrum the intermodulation performance improvessignificantly (see Fig. 6).

50

60

70

80

90

100

110

120

-50 -40 -30 -20 -10 0 10

input power [dBm]

f2-f1

f1

2f1+fs/4

3f1

f2

2f2+fs/4

f1+f2+fs/4

2f1+f2

f1+f2

2f1

fs/4+f2

fs/4+f1

f1-f2

Fig. 5 : Intermodulation products depending on the input power

60

70

80

90

100

110

120

130

-50 -40 -30 -20 -10 0 10

input power [dBm]

f1

2f1

2f2

3f1

3f2

2f2+f1

2f2-f1

Fig. 6: Intermodulation products under the presence of an7,75MHz/-10dBm sine-dither

C. Correction of the Non-Ideal Loop-Filters

One problem in the chip-design has been a slight aberration ofthe center frequency of the loop filter so that the notch of thenoise transfer function lies at a frequency of about 5MHz andnot (as wanted) exactly at fs/4 = 4.875MHz. The result is thatthe digital filters of each modulator (compare with Fig. 2) don’tmatch the loop filters and the correction network will not workcorrectly.Our Σ∆-modulator has separate outputs of each comparator fortest purposes. These data have been used for further processingin MATLAB . The digital filters have been changed from(1+z-2)x to

x

s

m zzf

f

+

− −− 212cos21 π

where fm is the new center frequency of the notch in the noisetransfer function. This leads to an optimised noise shaping atthe new center frequency. By doing this also the nonlinearanomaly improves for low input.

Another error source could be different gains of the cascades,but post processed data corrections showed that these constantsmatch very well.

D. Clockgeneration

With increasing IF-frequency the requirements on the clock-generation according to jitter also increase dramatically. Therequirements on the clock source in IF sampling systems (notethat there is a difference to wide band sampling) can becalculated by the formula

B

f

fds

232

12

0

1 ≤∆ στ

where f0 is the center frequency of the input signal, fs is thesampling frequency, B is the bandwidth of one channel and ddenotes the required dynamic range of the conversion.The clock for all parts of the system is derived by a mother-clock of 234MHz. This clock is generated by an integratedVCO whose reference is a 13MHz TCXO. The mother clock isdivided through 6 (decimation), 8 (GPS correlator), and 12 (Σ∆Modulator). All the clock generation circuit and also the inputof the ADC are realized in differential ECL technology.The clock jitter [8] is better than 25ps (limit of ourmeasurement utilities) and the spectrum of the jitter is white sothat it can be assumed that no narrow-band interferers disturbthe clock.

IV. THE DIGITAL FRONT-END (DFE)

A. General

The digital front-end is the very part of the receiverimmediately following the RF front-end and the AD converter.Its functionality consists of channelization and sample-rateadaptation. Thus the digital front-end is a piece of hardware fordigital signal processing performing front-end tasks which wereformerly realized on analog hardware. Fig. 7 shows the blockdiagram of the digital frontend.

4

Digital

Sigma-Delta

Modulator

GSM-SP

Correlator

GPSand -format

Adaptation

Wordlength

GPS-Branch

GSM-Branch

RF Front-End

1 0 -1 0 1 0 -1 0

Sigma-Delta ADC

Mixed Signal ASIC

GSM Channelization

DigitalPGC

I-Q Baseband

Power Detector

Dig. Down-Conv. Digital Up-Conversion

Fig. 7: Digital Front-End of the GSM-GPS receiver

B. ChannelizationChannelization is the task of channel selection, comprisingdown-conversion of the signal to base-band and channelfiltering. If the intermediate frequency (IF) which the signal isbeing digitized at is equal to

fn

fIF S=4

, n = 1 3 5, , ,... (n = 9 in our case)

the digital signal can be down-converted to base-band bymultiplying it with the sequences [0 1 0 -1] and [1 0 -1 0]representing the cosine and sine at a quarter of the sample rate.The channel filtering at base-band should suppress adjacentchannel interferers and thereby select the channel-of-interest. Incase of highly oversampled signals (if the channel-of-interestoccupies only a fraction of the total signal bandwidth) multi-rate filtering is a promising approach for implementing thechannel selection most efficiently.The necessity of sample rate adaptation arises when the ADconverter is clocked at a different rate than the symbol- or chip-rate of the standard of current operation. This could becircumvented if the clock-rate of the AD converter was madeadaptable which, however, does not seem to be desirable in thecontext of simplification of analog hardware and shiftingfunctionalities from the analog to the digital domain of signalprocessing.The basis of sample rate adaptation is the Nyquist criterion foraliasing free signals. A rate change by an arbitrary rationalfactor L/M can be accomplished by up-sampling by L, anti-image-filtering, anti-aliasing filtering and finally down-sampling by M.An efficient method for performing the necessary filtering hasbeen proposed by Hogenauer in [3]. The described CIC-filters(cascaded-integrator-comb) are time-varying recursive FIR-filters. Conventional FIR filters are usually applied forfinalizing the adaptation process.One can realize that the structure equals the structure of thenoise-shaper allowing a combination of both resulting inreduced hardware effort due to the reduced word-length.

C. Gain ControlsIn order to compensate for fading, a programmable gain controlis employed at the input of the ADC. Its control signal isderived from the power of the input signal.The dynamic range of the signal at the output of the filter ishigher than the dynamic range the GSM base-band processorcan cope with. Therefore a second gain control is implemented.This gain control is of feed-forward type. Over a fixed time-slotthe maximum magnitude of the signal at the output of thechannelization filters is determined. Using this knowledge asignal of reduced word-length is „cut“ out of the full-word-length signal, thus reducing the dynamic range.

D. Adaptation to the Base-Band Circuits

In order to interface the chosen base-band cicuits with the DFEsome adaptation tasks have to be performed. These are mainlysample-rate-, carrier-frequency- and word-length-adaptation. Inthe GSM-branch the signal has to be Sigma-Delta modulatedwith a word-length of 1 Bit. For this reason a digital Sigma-Delta modulator of second order is employed at the output.

E. Realization of the Digital Front-EndThe first filter stage being common to both branches - the GSMand the GPS branch - is implemented together with the Sigma-Delta Modulator on a mixed-signal chip, while the remainingparts are implemented on FPGAs (XILINX XC4000 series).The estimated gate-count is given in Table 2. For an ASIC thenumber of gates will be 1.5 to 2 times lower.

Table 2: Gate-Count for FPGA part of DFE

total GSM-branch GPS-branchfilter Σ∆M rest

16 k 10 k 1 k 3 k 2 k

V. SUMMARY

We have demonstrated a new concept for a combinedGPS/GSM receiver. This concept has the potential for areduction in volume, power consumption and cost comparedwith the conventional solution.A bandpass Σ∆-ADC for digitizing an intermediatefrequency of 44MHz has been realized and tested. Thematching of the different stages of the cascaded Σ∆modulator will be improved by a redesign.A digital front-end has been realized to adapt the Σ∆-modulatoroutput to commercially available chip sets forbasebandprocessing.

VI. ACKNOWLEDGEMENT

We would like to thank Dr. J.-F. Luy (Daimler-Chrysler) forinitiating this project, helpful discussions and constantencouragement. The authors are grateful to Mr. G. Rohmer, Mr.F. Oehler, Mr. W. Sehr and Mr. S. Urquijo (all FraunhoferInstitute Erlangen) for their efforts in the design of the Σ∆-converter and for Prof. Dr. G. Fettweis for his help concerningthe digital signal processing.

VII. REFERENCES

[1] Azizi, P.M., Sorensen, H.V., van der Spiegel, J.: An Overview ofSigma-Delta Converters, IEEE Signal Processing Magazine, Jan.1996, 61-84.

[2] Candy, J.: Decimation for Sigma-Delta-Modulation, IEEE COM,Jan. 1986, 72-76.

[3] Hogenauer, E. B.: An Economical Class of Digital Filters forDecimation and Interpolation, IEEE Trans. ASSP, April 1981, 155-162.

[4] S.A. Jantzi, R. Schreier, W.M. Snelgrove, " The design of bandpassdelta-sigma ADCs" in "Delta-Sigma-Data Converters: Theory, Designand Simulation", New York, IEEE Press, 1997, ch. 9, pp. 282-308

[5] A.Hairapetian, “ An 81-MHz IF Receiver in CMOS ”, IEEE J.Solid State Circuits, Vol.31,No.12; Dec. 1996,pp. 1981-1986

[6] A.K.Ong, B.A.Wooley, “ A Two-Path Bandpass Σ∆ Modulator forDigital IF Extraction at 20 MHz “, IEEE J. Solid State Circuits, Vol.32,No.12,Dec. 1997, pp.1920-1934

[7] W.Gao, W.M.Snelgrove, “ A 950-MHz IF Second Order IntegratedLC Bandpass Delta-Sigma Modulator “ IEEE J. Solid State Circuits,Vol. 33, No. 5, May 1998, pp. 723-732

[8] Cutler, Searle: “Some Aspects of the Theory and Measurement ofFrequency Fluctuations in Frequency Standards”, Proc. of the IEEE,Feb. 1966, Vol. 54, No.2, pp. 136 – 154

[9] D.H.Shen, C.H.Hwang, B.B.Lusignan, B.A.Wooley, „A 900-MHzFront-End with Integrated Discrete_Time Filtering“, IEEE J.SolidState Circuits,Vol. 31,No. 12, Dec. 1996, pp. 1945-1953