A 7.5-W 0.08-mm2 single-ended SC delta-sigma ADC for acoustic sensor...

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONSInt. J. Circ. Theor. Appl. (2015)Published online in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.2156

A 7.5-μW 0.08-mm2 single-ended SC delta-sigma ADC for acousticsensor applications

Quanzhen Duan, Zhidong Wang and Jeongjin Roh*,†

Department of Electronics and Communication Engineering, Hanyang University, Ansan, Republic of Korea

SUMMARY

This study presents an ultra-low-power, small-size, 1-bit, single-ended, and switched-capacitor (SC) delta-sigma analog-to-digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor nodehas a delta-sigma ADC that converts the sensed signal to a digital signal for convenient data processingand emphasizes the features of small size and low-power consumption. The chip area of the delta-sigmaADC is dominated by the capacitor; therefore, a novel common-mode (CM) controlling technique with onlytransistors is proposed. This ADC achieves an extremely small size of 0.08mm2 in a 130-nm CMOS pro-cess. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in theweak inversion region to achieve high power efficiency. At 4-MHz sampling frequency and 0.7-V powersupply voltage, the delta-sigma ADC achieves a 55.8-dB signal-to-noise-plus-distortion ratio (SNDR) anda 298-fJ/step figure-of-merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5μW ofpower. Copyright © 2015 John Wiley & Sons, Ltd.

Received 30 January 2015; Revised 7 August 2015; Accepted 26 August 2015

KEY WORDS: acoustic sensor; delta-sigma analog-to-digital converter (ADC); low power; small size;weak inversion region

1. INTRODUCTION

The study of wireless sensor networks (WSNs), which consist of autonomous wireless sensor nodesthat sense and collect data for specific applications, represents a significant research area today [1].A wide range of applications require the installation of wireless sensor nodes in mobile targets orhard-to-reach areas; therefore, these nodes should be small in size [2–6]. As a result, low powerconsumption and small size become critical design criteria. Figure 1 shows a basic block diagram ofa wireless sensor node embedded with an acoustic sensor [7]. Batteries and/or embedded energyharvesting transducers are used as the power source. An ADC is used for converting sensed signalsfrom an acoustic sensor. The limited size and power consumption means that the requirement of theADC resolution is loosened, and an 8-bit ADC generally satisfies the requirement for speechrecognition and target tracking [2,8]. Successive approximation (SAR) ADC [9] with low-powerconsumption can be a good candidate for use in WSNs; however, its performance greatly dependson the accuracy of the digital-to-analog converter (DAC) and comparator, and it takes up a largearea because of the capacitors. SC delta-sigma ADCs [10–16] can also be one of the best choices inwireless sensor nodes by trading off the low power consumption, the small size, and the highresolution. Most delta-sigma ADCs adopt fully or pseudo-differential structures, so they typicallyconsume more power and require a large chip area. Thus, this study proposes a single-ended and SC

*Correspondence to: Jeongjin Roh, Department of Electronics, and Communication Engineering, Hanyang, University,Ansan 426-791, Republic of Korea.†E-mail: [email protected]

Copyright © 2015 John Wiley & Sons, Ltd.

Figure 1. Block diagram of a wireless sensor node with an acoustic sensor [7].

Q. DUAN, Z. WANG AND J. ROH

delta-sigma ADC with the advantages of ultra-low-power and small-size for wireless acoustic sensorapplications.

Power consumption is reduced using inverters [13–18] instead of conventional OTAs, to design thedelta-sigma ADCs. This is because an inverter with both PMOS- and NMOS-input transistors has agreater transconductance and a large slewing rate [13]. However, the output CM voltage of aninverter has to be controlled using additional capacitors and switches, as shown in the dashed boxin Figure 2. The capacitor CC with different configurations holds the offset voltage VOFF to ensurethat the output CM voltages have the same levels at two clock phases. As a result, the output CMvoltages are controlled. Wang [18], in particular, adopts the conventional CM technique shown inFigure 2 to control the CM voltage and proposes a cascaded inverter working in the saturationregion to achieve a high DC gain and a wide bandwidth. Table I shows a comparison betweenWang’s approach [18] and the current study. The present work achieves a high circuit simplicity,power efficiency, and size efficiency. The large number of capacitors and switches of theconventional CM technique increase the complex of the circuit and induce additional switchingnoise. Extra capacitors also significantly increase the chip area, because the area of a delta-sigmaADC is generally dominated by capacitors instead of transistors. In addition, an OTA working in

Figure 2. Conventional common-mode control [13].

Table I. Comparison between Wang’s approach [18] and the current study.

Delta-sigma ADCstructure

CM-controltechnique OTA

Circuitsimplicity

Powerefficiency

Areaefficiency

Wang [18] Single-ended,1-bit, andthird order

Conventional(additionalcapacitorsand switches)

Cascadedinverter(saturation region)

× × ×

This work Proposed Inverter (weak-inversion region)

○ ○ ○

Copyright © 2015 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2015)DOI: 10.1002/cta

A 7.5-μW 0.08-MM2 DELTA-SIGMA ADC FOR ACOUSTIC SENSOR APPLICATIONS

the saturation region limits the low-voltage design, because the threshold voltage and output swinglimit the minimum power supply voltage. This leads to difficulties in designing a delta-sigma ADCwith a low supply voltage and lower power consumption, unless more advanced processtechnologies, such as a 90-nm or 45-nm process, are used.

This study proposes a low-power, small-sized delta-sigma ADC for an acoustic sensorapplication. The delta-sigma ADC uses a 130-nm CMOS process and is implemented by a 1-bit,single-ended, third-order, and CIFF structure. An innovative CM controlling technique that usestransistors only is proposed to reduce the complexity of the circuit and obtain high-areaefficiency. The OTAs with an inverter output stage are used in the weak inversion region toachieve high-power efficiency.

2. STRUCTURE AND CIRCUIT IMPLEMENTATION

2.1. Structure of the delta-sigma ADC

Figure 3 shows the architecture of the designed SC delta-sigma ADC, which adopts a 1-bit, third-order,and CIFF structure with the input-feedforward path. This is because a 1-bit modulator has betterlinearity [19]. A third-order structure usually has fewer stability challenges compared withhigher-order modulators [11,20] and also has a better noise-shaping performance [21]. A CIFFstructure with the input-feedforward path leaves the noise only for the processed signal in the loop,which provides the advantage of a significantly small output swing for each integrator output. Thissignificantly alleviates the requirement of the OTA performance and greatly reduces the powerconsumption.

Stable operation of the delta-sigma ADC is guaranteed by ensuring that the maximum gain of thenoise transfer function [NTF(z)] over the whole frequency is lower than 1.5; the coefficients weredecided based on a MATLAB simulation [19], as shown in Figure 3. The equation, b1= 1, meansthat the input signal is directly delivered to the adder, which is called the input-feedforward path, andthis sets the signal transfer function [STF(z)] to 1 [21, 22]. As a result, based on the architectureshown in Figure 3, STF(z) and NTF(z) can be derived and expressed as follows:

STF zð Þ ¼ 1

NTF zð Þ ¼ z� 1ð Þ3z� 0:6023ð Þ z2 � 1:698zþ 0:8024ð Þ

8><>: (1)

where NTF(z) implemented by a third-order structure has the third-order noise-shapingcharacteristic. Consequently, the delta-sigma ADC can achieve a good signal-to-noise ratio

Figure 3. Diagram of a single-bit third-order delta-sigma modulator.



(SNR) [21]. Figure 4 shows that a peak SNR of 81dB with an over-sampling ratio (OSR) of 66 (the worstcase) is obtained by a MATLAB simulation, which gives a sufficient margin for circuit implementation.

2.2. Implementation of a top system

Figure 5 shows the implementation of a delta-sigma ADC, in which the CM voltage (VCM) equals halfof the supply voltage (VDD). The positive reference (VDACP) and negative reference voltages (VDACN)are equal to the supply voltage and ground, respectively. According to signal’s variation range, thePMOS, NMOS, and CMOS switches are used in different places. A higher supply voltage isapplied for the switches in this implementation, which guarantees an adequately low on-resistanceover the signal range [15]. The switches are controlled by two-phase non-overlap clock signals, asshown in Figure 5. In this study, the input sampling capacitor and the feedback capacitor areshared to reduce power consumption, because the separate capacitor significantly increases the loadcapacitor of the OTA and more current is required to achieve enough unity-gain bandwidth. Inaddition, the separate capacitor greatly increases the chip area, so sharing capacitor [19] is utilized

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Out

put S

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Am

plitu

de [d

BF

S]

Figure 4. Output spectrum of single-bit third-order delta-sigma ADC.

Figure 5. Implementation of the 1-bit, single-ended, SC, delta-sigma ADC.



to improve the area efficiency. The thermal noise effect is reduced by choosing a 400-fF capacitor forthe first integrator as the sampling capacitor. Ideally, it can obtain an 80-dB SNR for a sufficientmargin [19]. The noise shaping occurs inside the loop, and the thermal noise in the other blocks isrelaxed, so smaller sampling capacitors are chosen for them. The sizes of the capacitors arepresented in Figure 5.

2.3. Proposed inverter-based OTA

Transistors working in the weak inversion region can achieve an ultra-low-power consumption, so aproposed OTA is implemented in the weak inversion region, as shown in Figure 6. It mainlyconsists of two parts: an inverter stage (M1 and M2) and a CM control circuit (M3, M4, and M5).At the process of the TT corner and the room temperature, the threshold voltages are 0.48V and0.42V for the PMOS and NMOS transistors, respectively. When VGS<VTH, the transistors work inthe weak inversion region, and the drain current of a transistor is given by [23, 24]

ID ¼ W

LID0 eVGS=nUT � eVGD=nUT

� �(2)

where W and L are the transistor’s width and length, respectively. ID0 and n can be extracted fromexperimental data, and n>1 is a non-ideality factor. UT is the thermodynamic voltage. Figure 6shows that the input of the CM control circuit is a constant voltage, VCM, which is chosen as halfof the VDD in this design. Transistors M4 and M5 have exactly the same current flowing, andaccording to the current in (2), the ratios of the width and length (W/L) of M4 and M5 candetermine the voltage level at node VD. Therefore, by selecting the proper W/L for M4 and M5, wecan obtain the fixed voltage VD and the relationship of |VDS4| = |VGS4| =VGS5 =VDS5 =VDD/2 =VCM.In this design, M1 and M5 have the same size. Both M2 and M3 are half the size of M4. Thus,M1 and M5 ideally have the same bias current, while M2 and M3 have half the bias current ofM4, as presented in Figure 6. Hence:

ID2;3ID4

¼WL

� �2;3 eVGS2;3=nUT � eVGD2;3=nUT� �

WL

� �4 eVGS4=nUT � eVGD4=nUTð Þ ¼ 1

2(3)

where VGS4 =VGS2. Because (W/L)2,3 = 1/2(W/L)4 mentioned above, we can achieve eVGS2;3=nUT �eVGD2;3=nUT ¼ eVGS4=nUT � eVGD4=nUT . In other words, a relation of VGD2,3 =VGD4 can be obtained.Thus, the drain voltage of M3 follows the drain voltage of M4 (VD). The output CM level is wellcontrolled by this simple technique. The proposed output CM control circuit with weak-inversion

Figure 6. The proposed OTA working in the weak inversion region.



region transistors only controls the CM voltage and has no affect on the output swing of the amplifier.In addition, the inverter stage greatly improves the modulator’s power efficiency, as mentioned above.

Because of the channel-length modulation effect for the weak inversion region, the variation of rds isinversely proportional with a drain current. The transconductance can be expressed as gm= ID/nUT bydifferentiating (1) with respect to VGS. Relatively wide transistors are used to achieve a higher gainbandwidth (GBW) and DC gain, as shown in Figure 6.

As mentioned above, the main amplifier is based on an inverter. The CM control circuit with the DCinput (VCM) does not affect the AC characteristics of the OTA. As a result, the transconductance, outputresistance, and GBW of the OTA can be expressed as follows:

Gm≈ gm1 þ gm2 (4)

Rout ≈Rop==Ron≈ rds1==rds2½ �==rds3 (5)

GBW ≈Gm= 2π CL;eff þ CP� ��

(6)

where CL,eff is the effective load capacitor, and CP is the parasitic capacitor because of the widetransistors in the proposed OTA. Table II summarizes the AC simulation results of the OTA in thefirst integrator at room temperature. The lower load capacitance and smaller output swing for thesecond and third stages in delta-sigma ADC allow adoption of smaller-current and smaller-sizeOTAs for them. Consequently, using the optimized power consumption and sizes, the delta-sigmaADC achieves a good performance in this study.

The temperature and process variation may cause increases or decreases in threshold voltage of atransistor. Hence, the transistors in the OTA should be biased so that they are deeply in weakinversion to compensate for any possible threshold voltage variation. However, this methodsignificantly increases the size of the transistors in the OTA and also tremendously increases thepower consumption of the OTA. For example, operating the process in the FF corner at atemperature of 85 °C significantly wastes both the chip size and the power consumption. Therefore,the authors of [25] propose a current regulator circuit to obtain a constant current in the inverterstage at different corners and different temperatures. However, the current regulator also consumespower and occupies area; consequently, it is unsuitable for WSN applications. In addition, chips inthe same silicon area generally operate in the same process corners. Therefore, in this study, thetransistors in the OTA are strongly biased in weak inversion by only considering the temperaturevariation (�20 °C to 80 °C). The corner variation is considered using different supply voltages andCM voltages to achieve a similar current. This proposed strategy greatly reduces the area and power.The OTA has enough bandwidth, so the proposed delta-sigma ADC achieves similar performance ina wide temperature range (as confirmed by the simulated results shown in Figure 10).

The single-ended structure means that the power supply noise may be the main noise of the delta-sigma ADC; however, in-band power noise of the delta-sigma modulator is attenuated because ofnoise shaping in the delta-sigma ADC. Simulated results show an approximately �22-dB power

Table II. AC simulation results of proposed OTA.

Parameter Value

Supply voltage (V) 0.7Quiescent current (μA) 4.2Power consumption (μW) 2.9DC gain (dB) 51.7Phase margin (degree) 82.6Unity-gain bandwidth (MHz) 21.3Effective load capacitor (CL,eff; fF) 320



supply rejection ratio (PSRR), and it drops at the frequency of about 50 kHz which is out of thebandwidth of delta-sigma ADC. In addition, a regulator that applies a good supply voltage for ADCcan be used, as shown in Figure 1. Furthermore, this design is studied for wireless sensor networkapplications, and the requirement of the delta-sigma ADC is relatively low, as mentioned in theintroduction. In other words, to a certain extent, the effect of the power noise for the delta-sigmaADC can be tolerated in this study.

2.4. Mismatch effect

The output CM level is implicitly controlled, so the matching property of the circuit is critical foraccurate operation. The mismatch of the MOS transistors is characterized by the random variation inthe difference in threshold voltage VTH and current factor β. β≈μCoxW/L, where μ is the mobility ofthe charge carriers, Cox is the gate oxide capacitance per unit area, and W and L are the width andlength of a transistor [23]. When transistors work in the weak inversion region, the variance of thecurrent difference is written by [23]

δ2 Ið ÞI2

¼ δ2 βð Þβ2

þ δ2 VTHð ÞnUTð Þ2 ¼ 1

WLAβ

2 þ AVTH2

nUTð Þ2" #

(7)

where AVTH and Aβ are proportionality constants. They are dependent on the CMOS process. Widertransistors can achieve smaller δ2(β)/β2 and δ2(VTH). The n and UT are mentioned above. Table IIIshows the matching proportionality constants of this work.

Assuming the W/L of M3 in Figure 6 has approximately +1% variation, the drain current of M3 isincreased by 1% as (2). However, the total currents of M2 and M3 are equal to the current of M1, andthe drain currents of M1 and M2 are biased. The drain voltage of M3 has to decrease to offset theincreasing current. M1, M2, and M3 share the same drain voltage, so the drain current of M2 startsto decrease and the drain current of M1 is increased. When the total currents of M2 and M3 equalthe drain current of M1, the drain voltage of M3 is fixed. In other words, the output CM voltage iscontrolled. In the simulation, the output CM level shows a different effect when different transistorsvary in size, where the reference common-mode voltage with a ±3-mV variation is assumed andadopted. When W/L of M1 (M2 or M3 or M4 or M5) has an approximately 1% variation, the outputCM level changes in a range from �1.5mV to 1.5mV. The delta-sigma ADC in this study cantolerate these mismatch effects because of the CIFF structure with its advantage of low output swing[22].

The effect of mismatch is reduced by adopting wide transistors to achieve a mismatch of lessthan 0.02% for a sufficient margin [26]. The proposed transistor sizes in Figure 6 have standarddeviations of current δ(I)/I of about +0.016% for NMOS transistors and 0.011% for PMOStransistors at room temperature. This gives a sufficient margin, so the mismatch effect in thisstudy is extremely weak.

2.5. Implementation of other circuits

Figure 7 presents the adopted clock generator circuit [19], which consists of logic gates. Two non-overlapping clocks with their delays, as indicated by P1d and P2d in Figures 5 and 7, are thengenerated. Figure 8 shows the 1-bit quantizer (which is used as the comparator), a set–reset (SR)latch circuit, and a feedback-control circuit in this study. The quantizer, with its simple structure,

Table III. Matching proportionality constants.

Technology Type AVTH (mVμm) Aβ (%μm)

0.13μm [this work] NMOS 5.5 0.8PMOS 3.5 0.7


Figure 7. Non-overlapping clock generator.

Figure 8. Comparator (quantizer), SR latch, and feedback-control circuit.


has a small size and low power consumption. When the quantizer achieves the comparison results,the SR latch circuit obtains, keeps, and holds the comparison outputs until new comparison resultsarrive. A feedback-control circuit applies control signals DP and DN for the DAC feedback circuit,as shown in Figure 5.

3. SIMULATION AND MEASUREMENT RESULTS

Figure 9 shows the simulated SNDR versus temperature. A regulated voltage is assumed as the supplyvoltage for the modulator, and a variation of ±50mV is simulated. The simulated results demonstratethat the proposed modulator at a supply voltage of 0.7V can achieve above a 60-dB SNDR over a widetemperature range from �20 °C to 80 °C [18]. In this work, two key points are considered and studiedfor a wide temperature range. On one hand, we simply assume that the chip operates in the normalnatural environment of people’s lives. On the other hand, the chip itself generates heat duringoperation, which results in a higher temperature. Consequently, a temperature range from �20 °C to80 °C is studied in this work. Table IV presents the simulated results with an OSR of 66 in differentcorners at different temperatures, where a quiescent current of approximately 9μA at roomtemperature is adopted. The proposed delta-sigma ADC shows higher than 60-dB SNDRs for mostcases (different process corners with different temperatures). Figure 10 shows the simulated peakSNDR versus input signal frequency, where a higher than 60-dB SNDR is achieved with differentinput frequencies.

Figure 11 shows a chip microphotography for this design. Measurement uses VDD and VCM

supplied by the power source generators. Table V presents the measured results, and the proposed


Table IV. Simulated results of delta-sigma ADC with bandwidth of 30 kHz and differentcorners with different temperatures.

Process corner Temperature (°C) SNDR (dB)

TT �20 62.625 64.980 63.2

FS �20 58.425 66.180 63.0

SF �20 61.225 69.180 66.0

FF �20 63.025 6680 65.6

SS �20 64.525 61.680 60.5

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20

30

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50

60

70

Temperature (oC)

SN

DR

(dB

)

VDD =700mVVDD =650mVVDD =750mV

Figure 9. Simulated SNDR versus temperature at different supply voltages.

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35

40

45

50

55

60

65

70

Input signal ( kHz)

Pea

k S

ND

R (

dB)

Figure 10. Simulated SNDR versus input signal frequency.



Figure 11. A microphotography of the chip (400μm×200μm).

Table V. Measurement conditions and results.

Parameter Value

Sampling frequency 4MHz 4MHzSignal bandwidth 25 kHz 30 kHzOSR 80 66Supply voltage 0.7V 0.7VPower consumption 7.5μW 7.5μWQuiescent current 9μA 9μAPeak SNR 56.2 dB 55.0 dBPeak SNDR 55.8 dB 54.8 dBDR 47 dB 46 dBCore size 0.08mm2 0.08mm2

CMOS process 0.13μm 0.13μm


delta-sigma ADC obtains a 55.8-dB SNDR with an approximate 9-μA quiescent current at theroom temperature and FFT points of 32 768. Figure 12 shows the measured output spectrumwith a �2.8-dBFS and 7.8125-kHz sinusoidal input signal, where the second and third harmonicsignals are presented. An ultra-low-power consumption is achieved by adopting a single-endedstructure in this study. The adopted single-ended OTAs with a simple structure have a lowPSRR, which induces a relatively high noise floor, as shown in Figure 12. Therefore, a small-amplitude input signal cannot be well recognized, and a smaller dynamic range (DR) compared

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Figure 12. Measured output spectrum with a �2.8-dBFS 7812.5-Hz sinusoidal input signal and 32 768 FFTpoints.



with SNDR is obtained, as shown in Table V. However, the proposed single-ended delta-sigmaADC with inverter-based OTAs has the apparent advantages of an extremely small area and anultra-low-power consumption. Therefore, with an ENOB higher than 8 bits, it is extremely suitablefor acoustic sensor applications in a WSN. In this study, the total chip size of the delta-sigmaADC is approximately 0.08mm2, and the total power consumption is only 7.5μW.

The measurements of the SNR and SNDR versus the input amplitude are presented in Figure 13,where a 56.2-dB peak SNR and a 55.8-dB peak SNDR are achieved for a 25-kHz bandwidth. FOMis generally used to evaluate the performance of the delta-sigma ADC, and it is defined by [19,27],

FOM ¼ Power_Consumption

2�Bandwidth�2 SNDR�1:76ð Þ=6:02 (8)

This design shows a 298-fJ/step FOM for a 25-kHz signal bandwidth and a 278-fJ/step FOM for a30-kHz signal bandwidth. Table VI presents the performance of this study and other sensorapplication studies, and this work shows the competitive characteristics of low-power consumptionand small size. Meanwhile, a good FOM compared to other studies is achieved.

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0

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SN

DR

& S

NR

(dB

)

SNDRp = 55 .8dB@ O SR = 80

SNRp = 56 .1dB@ O SR = 80SNRSNDR

Figure 13. Measured of SNR and SNDR versus input amplitude.

Table VI. Comparison with other sensor applications works.

This work[14]2009

[16]2013

[18]2014

[28]2014

[29]a

2011[30]2013

[31]2009

Applications Acousticsensor

Temperaturesensor

Micro Phone — — Neuralrecording

Biosensor Neuralrecording

Bandwidth (Hz) 25k 50 20k 500k 20k 4.58 4k 8k 1kSNDR (dB) 55.8 55.4 87.9 59 68 59.6 60 48.9 56Power (μW) 7.5 12.21 140 249 140 20 96 96 75.9VDD (V) 0.7 1.5 1.5 1.2 0.4 1.2 1.6 1.6 3.3FOM (pJ/step) 0.298 73.6 0.173 0.327 1.7 0.224 14.7 26.3 73.6Core size (mm2) 0.08 0.75 0.207 0.03 0.27 0.07 1.02 —CMOS process(μm)

0.13 0.5 0.35 0.11 0.13 0.09 0.15 0.5

aThe results are from the simulation.



4. CONCLUSION

This study presents an ultra-low-power and small-size delta-sigma ADC for acoustic sensorapplications in a WSN. The capacitor occupies the main area in the delta-sigma ADC, so a CMcontrolling technique is proposed to improve the area efficiency and reduce the complexity of thecircuit. A 278-fJ/step FOM in a bandwidth of 30 kHz is achieved while consuming a total power ofonly 7.5μW. The total chip size of the proposed delta-sigma ADC is only 0.08mm2 with a 130-nmCMOS process.

ACKNOWLEDGEMENTS

This research was supported in part by the MSIP (Ministry of Science, ICT, and Future Planning), Korea,under the ITRC (Information Technology Research Center) support program (IITP-2015-H8501-15-1002)supervised by the IITP (Institute for Information and Communications Technology Promotion), andsupported in part by the Industrial Core Technology Development Program (10049095, ‘Development ofFusion Power Management Platforms and Solutions for Smart Connected Devices’) funded by the Ministryof Trade, Industry, and Energy.

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http://focus.ti.com/download/trng/docs/seminar/sigcond_3.pdf

http://focus.ti.com/download/trng/docs/seminar/sigcond_3.pdf


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