A 25MS/s 14b 200mW Σ∆ Modulator in 0.18µm CMOS

Pio Balmelli

UT Mixed-Signal/RF Integrated Circuits Seminar Series

April 19th, Austin TX

2 Outline

VDSL specifications

Σ∆ A/D converter features

Broadband Σ∆ modulator architecture

Design description

Measurement results

Conclusion

3 VDSL

Local loop

PC

Localexchange

TelephonePublic

telephonenetwork

Internet

30Mbps

12 [MHz]0.10

VDSL Signal Bandwidth: A/D Specifications:

>24MS/sConversion rate

12-14bitResolution

1mile

4 Σ∆ vs. Nyquist A/D Converters

• No precise sample&hold stage• No complex anti-aliasing filter• Better untrimmed linearity

• Reduced conversion rate

Advantages:

Disadvantage:

Broadband architecture:Low OSR + High sampling frequency

5 Broadband Architecture

Discrete time:• Low jitter sensitivity• No excess loop delay

problem

Loopfilter feed-forward topology:• Small noise contribution of internal stages

fS

x[k]

y[k]

DAC

a1

z-1a2

z-1

Single-loop:• Low capacitor matching

specifications• Relaxed settling accuracy

Q

6 Single-Bit Quantizer

Result:• Single-bit quant.

achieves poorSNR at low OSR

Maximum Input Level

26

28

30

32

34

36

L = 7

L = 3

L = 5

[dB]

-8 -6 -4 -2-7 -5 -3 [dBREF]

Pea

k S

NR

NQ= 1b Constraints:• OSR = 8

L :Filter orderNQ:Quantizer

resolution

7 Quantizer Resolution and Filter Order

Maximum Input Level

Pea

k S

NR

70

80

90

95

-8 -6 -4 -2-7 -5 -3 [dBREF]

[dB]

85

75

Constraints:• OSR = 8• SNR > 95dB

Architecture:• 5th order loopfilter

and 4b quantizer,best tradeoff

L = 4NQ= 5b

L = 5NQ= 4b

L = 9NQ= 3b

L :Filter orderNQ:Quantizer

resolution

8 Block Diagram

96dBSNR-4dBMax input

8OSR5/9

x[k]

y[k]

15 1/13z-1 8 5 2

9 9 8 8 21

4 bitQuantizer

16 levelDAC

21/3

11/6z-1

1/7z-1

1/7zz-1

12

z-12

1/3zz-1

1/7zz-1

1/6zz-1

1/13zz-1

12

z-12

12

12

12

9 Noise and Signal Transfer Function

-120

-80

-40

0

100k 1M 100M[Hz]

[dB]

Noise transfer functionSignal transfer function

6.34MHz

9.86MHz

10M

10 Switch Level Diagram

ϕ1:ϕ2:

x[k]

4 bit quantizer

13C1

y[k]

7rst

15x

4 bit DAC

15 Logarithmicshifter

4

4

15

15C1 3C24C2

C2/6

5C3

7C3 7C4

2C4 3C5

C5

2C4

2CFF8CFF8CFF9CFF9CFF

Dynamic element matching

ϕ1DWACQ

ϕ2

ϕ2

ϕ2

V R V R

Gainstage

To neg.path

To neg.path

11 Data Weighted Averaging

1’scounter

Modulo15 adder

ϕ2

4

ϕ2

15 15

Quantizer DAC

Q[k] Q*[k]

A[k]

Logarithmicshifter

DWA logic

y[k]

• 1st order shaping

• DAC elements usedat maximum rate

• Each element selected same number of times

• DWA logic:

<1mWPower

4nsDelay

96# std. cells

4

[Baird95]

12 DWA Performance

-120

-80

σC1=0.23%

-40

10M

0

Simulated Output Power Spectrum[dB]

100M1M100k[Hz]

DWAw.o. DWA

13

x[k]

Shared capacitorsfor x[k] and VR:

• 3dB less kT/Cnoise

• Reduced amp. load• Fast reference

buffer needed

Input Stage

Referencebuffer

ϕ1

ϕ1

ϕ1

Cu1

Cu2

Cu15

13Cu

ϕ1

ϕ2

VR VR

ChCh

[ ][ ] [ ]d1 R

2Q kCh k 15C V x k 115

⎡ ⎤⎛ ⎞= − −⎜ ⎟⎢ ⎥⎝ ⎠⎣ ⎦

Buffer charge:

ϕ2

Q1[k]

Q2[k]

Q15[k]

S1

S2

S15

S1

S2

S15

14 Reference Buffer

VR

VB

IB

M2

M1

freq.

log(

|Zou

t|)

≈⎛ ⎞+⎜ ⎟

⎝ ⎠2

12

1

1DC

mm

o

Zggg

MAXm

Zg

≈1

1

• M2 reduces lowfreq. Impedance

• IB not modulatedby VR

• Low voltage dropover M2 needed

37mWPower

18ΩZMAX

1ΩZDC

1.2VVR

IB

VR

M2

M1

VB

[Piessens02]

15 Operational Transconductance Amplifier

Vcm

M1 M2OP1

C1 C2C3 C4

Vout

VB

ϕ2ϕ1

ϕ1 ϕ2

ϕ2

ϕ2

ϕ1

ϕ1

• Telescopic cascodefor low power

• Regulated cascodefor high DC gain

• High current forspeed

2, 4, 4, 8Pow. Scaling

53mWPower

0.75VSwing

1.9GHzGBW (70o)

90dBGDCM3 M4

OP2 M6M5

M8M7

Vin

IB

16 Gain Stage• Transistors always in

saturation• Const. gain over temp.

and process variation• Good linearity• Low input capacitance• Low output impedance

500fFOutput Load

16.2mWPower< 5%Gain var. (0.6V)

2GHz3dB BW~7Gain

VBp R3

A

• gmR-constant bias

VCM R2

R1

CCM ϕ1

ϕ1 ϕ2

ϕ2

M1

M2

M3

VoutVout

VinVin

IB1

IB2

[Opris97]

17 Comparator• Minimized load

at node A:High trackingspeedShort regenera-tion time

3.4mVσoffset

~1mWPower

<1ns (1µV)tlatch

2.1GHz (6dB)BW3dB

Q

Q

ϕ2 ϕ1

M1

M2

M3

M4

VB1

VB2

M5

VQ

VQ

NMOS-Latch

rst

Bootstrappedsignal: 2ϕH=Vdd+VT

A

18 SNR, SNDR, and DR

-90 -80 -70 -60 -50 -40 -30 -20 -10 0-10

01020304050607080

Signal Power [dBFS]

Dynamic Range: 84dB

[dB]

Peak SNDR: 72dB

• 2.5MHz signal• Noise power integra-

ted up to 11.14MHz

Peak SNR: 82dB

19 Measured Spectrum

Frequency [MHz]

Mag

. [dB

FS]

1001010.10.010.001

120

80

40

01M FFT

2.5MHz

Mag

. [dB

FS]

120

80

40

0

5MHz

20 Chip Micrograph

• Separateanalog/digitalpad rings

• 0.95mm2 corearea

21 Performance Summary

*Signal frequency at 2.5MHz and noise bandwidth based on main and optional (in brackets) symmetric spectral plans of VDSL.

200mW1.8V

Power ConsumptionVoltage Supply

84dB (82dB)82dB (80dB)72dB (70dB)1.6Vpp (differential)

Dynamic range*Peak SNR*Peak SNDR*Input range

0.18µm 1P6M CMOS0.95mm2

ProcessCore area

25MS/s200MHz8

Conversion RateSampling frequencyOversampling ratio

22 Power Distribution

13%

7%7%3%

8%

8%

3%

6%

19%26%

Ref. bufferOTA 1OTA 2OTA 3OTA 4OTA 5Gain stageQuantizerDWAClock

23 Result Comparison

50

100

80

90

70

60

Dyn

amic

Ran

ge [d

B]

Input Signal Bandwidth [Hz]1M 10M

[5]

[1]

[4]

[2] ThisWork[3]

[6]

[7]

JSSC:[1] Geerts, 2000/12[2] Vleugels, 2001/12[3] Fujimori, 2000/12[5] Feldman, 1998/10

ESSCIRC:[6] Di Giandomenico,

2003*[7] Luh, 2000*

ISSCC:[4] Reutemann, 2002

* Continuous timemodulator

24 Conclusions

VDSL critical ADC specifications

Oversampling limits Σ∆ ADC speed

Broadband Σ∆ ADCLow OSR + high sampling frequency

Measured 82dB SNR at 25MS/s

Best Σ∆ ADC performance