A 22-bit Read-Out IC With 7-ppm INL and Sub-100-...

3086 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 11, NOVEMBER 2019

A 22-bit Read-Out IC With 7-ppm INL andSub-100-μHz 1/ f Corner for DC

Measurement SystemsJaehoon Jun , Student Member, IEEE, Soungchul Park, Student Member, IEEE,

Junho Kang, Student Member, IEEE, and Suhwan Kim , Senior Member, IEEE

Abstract— A 22-bit read-out integrated circuit (IC) isconstructed from a capacitively coupled instrumentation ampli-fier (CCIA) followed by an incremental delta-sigma (��) analog-to-digital converter (ADC), both of which have programmablegain. The CCIA has a cascode Miller-compensated differentialdifference amplifier (DDA) with clamp transistors for energyefficiency. The offset and 1/ f noise of the fully differentialread-out IC are suppressed by chopping and correlated dou-ble sampling (CDS) techniques, which are synchronized withsampling by the ADC. Residual low-frequency noise is reducedby the second-order system-level chopping technique with anon-chip moving-averaged finite impulse response (FIR) filter.Implemented in a standard 0.13-μm CMOS process, the read-out IC achieves a maximum effective resolution (ER) of 21.9 bit,an integral nonlinearity (INL) of 7 ppm, and a 1/ f cornerof 40 μHz. The chip draws only 142 μA from 3-V supplyand 18 μA from the 1.5-V supply, and it has an active areaof 0.65 mm2 including digital filter.

Index Terms— Chopping technique, differential differenceamplifier (DDA), energy efficiency, full-on-chip integration, gainprogrammability, incremental delta-sigma (��) analog-to-digitalconverter (ADC), instrumentation amplifier (IA), read-out.

I. INTRODUCTION

H IGH-RESOLUTION read-out integrated circuits (ICs)are required for precision transducers such as strain

gauges or thermistors [1]–[4]. To read-out sensor’s signals,high-precision dc signal conditioning systems require a read-out IC with a resolution above 20 bit, at a bandwidth of a fewhertz [3], [5]–[7]. Moreover, highly linear gain programmabil-ity and a high energy efficiency should be considered for wideapplication. In cases of thermistor bridges or strain gauges, alow 1/ f corner (<1 MHz) is also required [7]–[9].

A read-out IC typically consists of a low-noise instrumen-tation amplifier (IA) followed by a high-resolution analog-to-digital converter (ADC) [1]–[12], as shown in Fig. 1. IAswith switched-capacitor (SC) [13] or resistive-gain topolo-gies [1], [4] have been used to implement precision read-out

Manuscript received April 3, 2019; revised June 14, 2019; acceptedAugust 8, 2019. Date of publication August 27, 2019; date of currentversion October 23, 2019. This article was approved by Associate EditorDennis Sylvester. This work was supported by Gwanak Analog Technologies,Seoul, South Korea. (Corresponding author: Suhwan Kim.)

The authors are with the Department of Electrical Engineering and Com-puter Engineering, Inter-University Semiconductor Research Center, SeoulNational University, Seoul 08826, South Korea (e-mail: [email protected]).

Color versions of one or more of the figures in this article are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JSSC.2019.2934817

Fig. 1. Simplified block diagram of a typical sensing system.

ICs. Switched-capacitor IAs (SCIAs) are robust againstprocess variation, but they suffer from a poor power-noisetradeoff due to noise folding, which limits their resolution.Resistive-gain IAs (RGIAs), which include current-feedbackIAs (CFIAs), avoid this issue [7]. However, CFIAs require twonoise-critical input stages, which degrade the power efficiencyof the analog front end [10]. Furthermore, to achieve a lowintegral nonlinearity (INL) of 5 ppm and a low 1/ f cornerbelow 0.1 MHz, RGIAs need highly linear external resistorsin their feedback loops [7]. The need for external resistors alsolimits the gain programmability of these IAs and narrows downthe application range of the read-out IC due to the difficultyin system integration. A capacitively coupled IA (CCIA) hasonly a single noise-critical input stage with a rail-to-rail inputcommon-mode range. Because a capacitive-gain network hasinherently high linearity and negligible static power consump-tion, this can achieve low noise and high gain accuracy witha single-chip implementation. A recent implementation [5]achieves a wide gain range (1–128) CCIA with a noiseefficiency factor (NEF) of 6.4, showing a 1/ f corner of 4 MHz.

The replacement of an IA and an ADC with a bridge-to-digital converter (BDC) has recently been proposed toreduce the complexity of the analog circuitry in a read-outIC [14]–[17]. However, a low-noise chopped BDC based ona continuous-time (CT) delta-sigma (��) ADC needs a com-plex digital-to-analog converter (DAC) in a feedback loop oran additional filter [14], [16]. A 20-bit BDC has been reportedin [14], but read-out ICs in [6] and [18], which are not withthe BDC structure, have achieved a better NEF. Furthermore,the input range of a BDC is relatively small (<50 mV), whichlimits the application range of the read-out IC.

This article describes a fully integrated 22-bitprogrammable-gain read-out IC with a low 1/ f cornerfrequency (<100 μHz) for high-accuracy sensor applications.The prototype read-out IC consists of a CCIA and a

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JUN et al.: 22-BIT READ-OUT IC WITH 7-ppm INL AND SUB-100-μHz 1/F CORNER 3087

Fig. 2. Simplified signal path of the read-out IC.

succeeding incremental second-order SC �� ADC and hasa wide programmable gain range from 1 to 128. To mitigateflicker noise and unwanted offset error in the main signal path,chopping and correlated double sampling (CDS) techniquesare used in CCIA and ADC, respectively. A ripple-reductionloop (RRL) is applied to the CCIA to suppress the voltageripple caused by chopping at the output of the CCIA. AlthoughCCIAs have moderate input impedance, the input impedancecan be boosted by a positive-feedback impedance-boostingloop (IBL) [6]. The second-order system-level chopping isalso applied to achieve a further reduced low-frequency noisebelow 100-μHz 1/ f corner frequency. In [6], a differentialdifference amplifier (DDA) is used in the CCIA to operate themain signal path and the RRL path simultaneously to optimizeenergy efficiency. To achieve an even more efficient systemthan [6], the cascode Miller-compensated DDA with clamptransistors is designed including a class-AB output stage. Theread-out IC achieves a maximum effective resolution (ER)of 21.9 bit, an INL of 7 ppm, and an offset of 1.87 μV witha conversion time of 200 ms. It draws only 142 μA from a3.0-V supply and 18 μA from a 1.5-V supply.

This article is organized as follows. In Section II, theread-out IC architecture is described. The implementationdetails of the CCIA and the �� ADC are discussedin Sections III and IV, respectively. Section V describesthe system-level design, while Section VI presents theexperimental results. This article ends with conclusionsin Section VII.

II. PROPOSED READ-OUT IC ARCHITECTURE

Fig. 2 shows the simplified block diagram of the read-outIC, which consists of an input multiplexer (MUX), a low noiseCCIA, and a 24-bit SC �� modulator followed by a digitalfilter and a serial interface. In this work, the voltage gain ofthe ADC is programmable, as well as that of the CCIA. Boththe voltage gains are determined by the capacitive ratio for itsrobustness. The voltage gain of the fully differential read-outsystem is the product of the gains of the CCIA and the ADC,and it can have values of 1, 4, 16, 32, 64, or 128.

Typically, the output of the most sensors is effectivelyconstant during the time required for single data conversion,so that a read-out IC can be multiplexed to cycle betweenseveral sensors. To allow this to happen, a MUX is insertedinto the input stage, and the incremental-type ADC withperiodic self-reset is employed.

The details about the circuit operation and the implementa-tion of the interface circuit are discussed in Sections III–V.

Fig. 3. Simplified block diagram of CCIA.

III. CCIA IMPLEMENTATION

Fig. 3 shows the simplified schematic of the CCIA’s mainsignal path. Basically, the capacitive CIN and CFB determinethe closed-loop gain of the CCIA, which is GIA(= CIN/CFB).Taking into account input-referred noise (IRN), active area,input impedance, and parasitic capacitance, CIN = 16 pFand CFB = 1 or 0.5 pF are chosen for gains of 16 or 32,respectively.

The IRN of the CCIA, which is dominated by the noise ofthe main amplifier, can be expressed as follows:

VN,IN =(

CIN + CFB + CGG

CIN

)VN,AMP (1)

where CGG and VN,AMP are the input gate capacitances andIRN of the main amplifier, respectively. Equation (1) showsthat the noise contribution of CGG decreases as GIA increases.This means that higher energy efficiency can be achieved witha higher gain of the CCIA. Theoretically, the energy efficiencyof the CCIA is about twice higher than that of the CFIAat gains above 10 [10]. In the consideration of the systemoptimization, the CCIA of the read-out IC can be bypassed atlow system gains (<10), which is 1 or 4.

To mitigate offset and flicker noise, a chopping technique isapplied to the CCIA. This is indicated with blue lines in Fig. 3.The chopping frequency fCHOP is set to 30.72 kHz, which ishigher than the 1/ f corner frequency of the un-chopped CCIA,which is 15.1 kHz. With the chopping, 1/ f corner frequencyof 200 MHz can be achieved.

Chopping is effective in suppressing low-frequency noise,but it comes with two side effects in the CCIA. The inputimpedance of the CCIA is limited by the input chopper, andan output ripple is produced by the output chopper. Theseissues can be eased by introducing an RRL and an IBL. Thiswill be explained in Sections III-A and III-B.

A. Ripple Reduction Loop

Noise, together with any unwanted low-frequency offset,is upmodulated by the output chopper CHOUT and filtered outby Gm2 and CC, as shown in Fig. 3. This generates remainedoutput ripple, which is not permissible in the low-noiseapplications.

To suppress the output ripple, an auxiliary RRL, which isshown in Fig. 4, is used in the additional negative-feedbackloop [19].


Fig. 4. Block diagram of RRL, together with the main path of CCIA.

The noise introduced by the SC integrator and Gm3 in theRRL also needs to be considered. The input-referred thermalnoise of the RRL can be calculated by

VN,RRL =(

CIN+CFB+CGG

CIN

) √V 2

N,INT_RRL+V 2N,Gm3

/Gm1

Gm3(2)

where VN,INT_RRL and VN,Gm3 are the noise from the SCintegrator and Gm3, respectively. The low-frequency noise ofthe amplifier of the SC integrator is alleviated using the CDStechnique. As indicated by (2), the noise from the RRL isreduced by Gm ratio, Gm1/Gm3. Fig. 5(a) shows the simulatedinput thermal-noise level as a function of the Gm ratio. WhenGm1/Gm3 > 15, the noise from the CCIA is dominated bythe main amplifier, as shown in Fig. 5(b). In this design,the Gm ratio is chosen to be 25, which is high enough for thenegligible noise of the RRL, while the 1/ f corner only risesto 165 MHz. This is sufficiently low to apply a system-levelchopping technique, which will be discussed in Section V.

B. Impedance-Boosting Loop

The input impedance of the CCIA, which is limited by theinput chopper CHIN, is about 1 M� with 30.72 kHz of fCHOPand 16 pF of CIN. With 100-� resistive sensor, the gain erroris less than 0.01%. An IBL can be provided for the case ofhigh-resistive sensors. The input impedance can be increasedby reducing the input current of the CCIA, which can beachieved with a positive-feedback loop, as shown in Fig. 6.The uncompensated input current IIN and the compensationcurrent IIBL can be expressed as follows:

IIN = VIN

ZIN= 2CIN fCHOPINIA (3)

IIBL = OUTIA − INIA

ZIBL= 2CIBL fCHOP(OUTIA − INIA) (4)

Fig. 5. (a) Simulated IRN level and (b) 1/ f corner versus Gm ratio.

Fig. 6. IBL in CCIA.

Fig. 7. Block diagram of the proposed CCIA.

where ZIBL is the effective impedance of the positive-feedbackpath. At CIBL = CFB, the compensated input current isgiven by

IBOOST = IIN − IIBL = 2CIN fCHOPINIA

GIA(5)


Fig. 8. Circuit diagram of the cascode-compensated DDA.

where GIA is the dc gain of the CCIA. The boosted inputimpedance ZBOOST can be calculated as follows:

ZBOOST = GIA ZIN (6)

where ZIN is the original input impedance without the IBL.To maximize the boosting effect of the IBL, the feedbackcapacitor CIBL is designed to be calibrated in 5-bit resolution.

C. Differential Difference Amplifier

Fig. 7 shows the block diagram of the proposedCCIA, including the negative-feedback RRL and thepositive-feedback IBL. A single fully differential DDA, whichis the most crucial amplifier, is used for the core amplifier inthe CCIA for high energy efficiency and small area occupation.It consists of Gm1, Gm2, Gm3, and the output chopper CHOUT.The dc gain of the CCIA can be given by

GIA = OUTIA

INIA= AIA

1 + AIA(CFB/CIN)(7)

where AIA is the dc gain of the main amplifier in the CCIA.For the high gain accuracy, the dc gain of the DDA is designedto be 122 dB, which results in a low gain error below 25 ppm.

The DDA is the primary noise source of the CCIA.As shown in (1), the noise of the DDA is multiplied by(CIN +CFB +CGG)/CIN, determining a tradeoff between noisegain and 1/ f noise, which must be considered in choosingthe size of the input transistors. In this work, the properlysized PMOS input transistors of Gm1 are chosen with CGGof 490 fF (� CIN = 16 pF) and gm of430 mS, which onlyincrease the noise gain of 3%, with an enough low noise levelof 13.2 nV

√Hz.

The detailed circuit diagram of the two-stage DDA isshown in Fig. 8, and the CHOUT is located at the input of

Fig. 9. Back-to-back pseudo-resistor for dc biasing.

the second stages. The DDA is designed to have a unity-gain bandwidth (UGBW) of 8 MHz to drive the followingSC ADC with complete settling. A CT common-mode feed-back (CMFB) is also designed. Compared to [6], a cascodeMiller-compensation technique is applied to maximize energyefficiency with high UGBW [20]. To reduce static currentconsumption, a class-AB output stage is used with a capaci-tor CC. To lessen the burden of the slewing, two PMOS clamptransistors are added in the first stage of the amplifier, whichare implemented in a folded cascode. The clamp transistorsdraw no static current and only operate at extreme slewingstate. In the slewing state, the drain voltage of the inputtransistors rises. The clamp transistors make current flow whenthe drain voltage reaches the threshold voltage. After slewingoccurs, they stabilize the internal bias of the amplifier and thenthe clamp transistors turn off by themselves.

As previously discussed in Section III-A, the noise ofthe RRL is reduced by the Gm ratio of the input of theDDA. In the proposed DDA, Gm3 is only 17 μS for Gm ratioof 25. The two-stage DDA, which is the most power-hungryblock in the read-out IC, consumes only 120 μA includingthe CT CMFB. With the proposed DDA, the simulated IRNdensity of the CCIA is 16.5 nV/

√Hz.


Fig. 10. (a) Block diagram and (b) schematic of the �� modulator.

D. Common-Mode Biasing

In the CCIA, a floating node occurs at the input of Gm1 dueto the absence of the dc determination. As shown in Fig. 7,parallel bias resistors RBIAS have been added to determine thedc level of the DDA’s input. The noise of the resistors alsoneeds to be contemplated, because they are directly connectedto the input stage of the CCIA. The IRN of these resistors canbe derived as follows:

VN,RBIAS = 1

2π fCHOPCIN

√4kT

RBIAS. (8)

If RBIAS was 1 M�, the input noise density of the biasresistors would be 41.7 nV

√Hz, which exceeds the noise

budget of a 22-bit read-out system. A resistor with a largevalue is required, but a large passive resistor requires a lotof areas. As shown in Fig. 9, back-to-back diode-connectedPMOS pseudo-resistors are used to maintain the noise levelof the system. Although there is an alternative method usinga tunable voltage to cover wide voltage range [21], a sim-ple and area-efficient fixed pseudo-resistor is enough in this

fixed dc biasing. The simulated minimum pseudo-resistanceis about 1 T�, which corresponds to a negligible noise levelof 0.04 nV

√Hz.

IV. �� MODULATOR IMPLEMENTATION

An incremental ADC is required to digitize the outputof the IA. Fig. 10(a) shows the block diagram of theprogrammable-gain incremental �� ADC. It consists of asecond-order, 1-bit �� modulator, implemented as a cascadeof integrators with a feedforward (CIFF) structure, followed bya reconfigurable on-chip decimation filter. The use of a fullydifferential discrete-time (DT) �� modulator avoids applyinga resistive loading to the CCIA.

As shown in Fig. 10(b), separate sampling capacitors CS1and CDAC are used to sample the input VIN_ADC and thereference VREF, respectively. The dc signal gain of the separatesampling �� ADC can be defined by CS1/CDAC(= b1/c1),and one of these capacitances needs to be program-mable. Since changing c1 affects the noise-transfer func-tion (NTF) of the �� modulator, b1 is made programmable


Fig. 11. (a) Proposed block diagram of the system with the associated clock and (b) clock distribution.

coefficient [22], [23]. Due to b1 is independent of the NTF,the stability of the programmable-gain ADC (PGADC) can beassured. With the separated capacitor structure and the variablecoefficient b1, the PGADC can realize a variable gain of 1 or 4.Moreover, the use of separate sampling structure suppressesinput-dependent current from the reference voltages [24], [25].

The amplifiers with SC CMFB in the ADC are implementedin a similar way to that in the CCIA. The input samplingcapacitor CS1 and sampling clock frequency fS of the unity-gain-mode ADC are 6 pF and 61.44 kHz, respectively, andthe ADC draws 34 μA from a 3-V supply. To minimizecircuit nonlinearities in the integrators, bottom-plate samplingis employed, with a non-overlapping clock. Since the firstintegrator is the most critical block of the ADC, the designof its amplifier has to take account of IRN and sampling

error [26], [27]. It has a UGBW of 800 kHz with a 5-pF capac-itive load while occupying three-quarters of the power budgetof the ADC. The amplifier of the second integrator is not crit-ical, so it has a simple single-stage folded-cascode structure,which consumes only 2.5 μA with a 600-fF capacitive load.

The CDS technique is applied to the first integrator to reducethe 1/ f noise of its amplifier [28], but not to the secondintegrator because its noise is shaped out of the band by thefirst integrator. To minimize the static current, a passive adderis used at the input of the comparator.

V. SYSTEM-LEVEL DESIGN

A. Reconfigurable Digital Filter

The oversampled bit-stream (BS) output of the �� modu-lator is averaged by the following reconfigurable decimation


Fig. 12. Proposed input MUX with incorporated system chopper.

Fig. 13. Chip microphotograph.

filter, which is shown in Fig. 11(a). This filter consists ofa sinc3 decimation filter [29] followed by a finite impulseresponse (FIR) filter and a serial interface.

The frequency response of the sinc3 filter is given by

|H (e jw)| =(

sin(π M f / fS)

M sin(π f / fS)

)3

(9)

where M is the programmable downsampling ratio (DSR) ofthe sinc3 filter. The controllable coefficient M is used to varythe output data rate (ODR) of the digital filter. After beingdownsampled by the sinc3 filter, the results of four consecutiveconversions are then combined by a moving-average FIR filter,increasing the ER of the read-out IC by 1 bit. The digital filteris programmable for ODR of 5, 10, 20, and 80 sample persecond (SPS), and it has notches, which effectively suppressout-of-band noise and 50/60-Hz interference.

B. System-Level Chopping

As previously shown in Section III-A, the 1/ f corner fre-quency of 165 MHz is achieved by chopping. To suppress theremaining 1/ f noise and the low-frequency offset, a second-order system-level chopping is applied, which is indicatedin green lines in Fig. 11. As discussed in Section V-A, theresults of four successive sinc3 conversions are combined bythe FIR filter. To achieve the second-order high-pass filtering,the sequence of the system-level chopping signal is chosen to

Fig. 14. Measured read-out IC’s output versus analog gain.

Fig. 15. Measured INL of the read-out IC.

be 1001 or 0110 [30], as shown in Fig. 11(a). This filter onlyreduces the ODR of the read-out IC by a factor of 2, whileproducing a 1-bit improvement of the ER.

The input system-level chopper is incorporated into aninput MUX stage, as shown in Fig. 12. Each input path ofthe MUX consists of three switches, a low ON-resistancemain switch and two dummy switches. To reduce the sideeffects of clock feedthrough and charge injection, the size ofthe dummy switches is half of the main switch [31]. Thisarrangement reduces circuit complexity and the input-referredthermal noise, which is directly affected by the ON-resistanceof the switches. In consideration of the CCIA’s thermal noiselevel of 16.36 nV/

√Hz, the maximum ON-resistance of the

input MUX is set to be 300 �. This MUX results in aninput noise level of 2.2 nV/

√Hz, which is much less than

the thermal noise level produced by the CCIA. An outputsystem-level chopper is implemented in the digital domain,making it relatively tolerant of circuit nonlinearities.

C. System-Level Timing Consideration

Although the RRL suppresses the output ripple of theIA, the sampling timing of the ADC must also be carefullydetermined in the proposed read-out IC. To take account ofthe residual side effects of the choppers and settling error,


Fig. 16. Measured ER versus ODR.

Fig. 17. (a) Measured output noise and (b) noise histogram.

the sampling clock frequency fS is set to twice of the choppingfrequency fCHOP with a 3TS/8 delay, as shown in Fig. 11(b).After the inner choppers swap, there is enough time for the

Fig. 18. Measured PSD of the read-out IC (the residual offset was subtracted,and 16× averaging was applied).

Fig. 19. Measured (a) offset, (b) CMRR, and (c) PSRR.

output ripple to settle before the sampling sequence of theADC begins. Furthermore, the system-level chopper signalsare all synchronized with the timing of the system reset tominimize the unintended effect.

With the proposed timing and the CCIA with sufficientbandwidth, the input sampling stage of the ADC has anegligible settling error with no disturbance of the choppers.

VI. EXPERIMENTAL RESULTS

The programmable-gain read-out IC was fabricated in astandard 0.13-μm CMOS process with an active area of0.65 mm2. Fig. 13 shows an annotated chip microphotograph,


Fig. 20. Measured input impedance.

Fig. 21. (a) Block diagram and (b) photograph of the weighing scale systemdemonstration setup.

which includes both the analog and digital circuits. The fab-ricated chip dissipates only 142 μA from a 3-V supply and18 μA from a 1.5-V supply. The experiment results of theread-out IC and the complete weighing scale system havebeen analyzed. The measurement details are presented in thefollowing sections.

A. Linearity and Noise Measurements

The measured output of the read-out IC versus gain witha fixed input is shown in Fig. 14. As illustrated in Fig. 14,the measured output is highly linear with a coefficient ofdetermination of 0.9999. Fig. 15 shows that the read-out ICachieves an endpoint calibrated INL of 7 ppm.

The measured ER versus the final digital ODR for eachgain of the read-out IC is shown in Fig. 16. Each point inthe plot is based on 212 output data values. It shows thatthe maximum is ER of 21.9 bit, which can also be seen inFig. 17(a). As illustrated in Fig. 17(b), the histogram showsthe output rms noise of 3.99 LSB, which is consistent with the

Fig. 22. Measured weighing scale system’s output (a) with 100-g weightstep and (b) zero weight input.

ER of 21.9 bit in a conversion time of 200 ms. The maximumnoise-free resolution (NFR) is 19.18 bit, which was determinedfrom a 6.6-σ noise distribution satisfying the industry-standardreliability of 99.9%.

Fig. 18 shows the measured output PSD of the read-outIC with the on-chip digital filter and serial interface, recordedover 7 h. The measured noise floor of the read-out IC is equiv-alent to 44 nV/

√Hz including folded noise and ADC noise.

As indicated in Fig. 18, the 1/ f corner frequency is suppressedbelow 40 μHz with a combination of the second-order system-level chopping, inner chopping, and CDS. The read-out ICexhibits an average offset of 1.87 μV, a common-mode rejec-tion ratio (CMRR) of 126 dB, and a power-supply rejectionratio (PSRR) of 121 dB, based on measurements of 18 samplechips (Fig. 19). As shown in Fig. 20, the averaged inputimpedance is boosted by five times with the IBL, and it islimited by the parasitic capacitance. With the higher resolutionof the IBL, the input impedance can be more optimized, whichmakes the boosted line flat.

B. System Demonstrations

The demonstration setup of the read-out IC is shown inFig. 21. The read-out IC has combined with a load cell of600-g capacity to verify a precise weighing scale system. Theexcitation voltage of the load cell is chosen to 3 V, which isthe same with the reference voltage of the ADC. Calibrationcertificated standard weights (CAS F1, 100 g) are used forthe delicate test environment. Fig. 22(a) shows the real-timemeasurement results of the system with a gain of 128 after zerocalibration (ZC). The weight input is scaled up from 0 to 600 gin the step of 100 g. Fig. 22(b) shows the measured noise(σ = 0.04 g) of the manufactured weighing scale with zeroweight input including both electrical and mechanical noises.

C. Performance Summary

In Table I, the performance of the programmable-gainread-out IC is summarized and compared with previously


TABLE I

PERFORMANCE SUMMARY AND COMPARISON

published read-out ICs [1], [3], [5], [6] for high-resolutiondc measurement. Compared to other designs, this work haswide on-chip reconfiguration of gain and conversion time,and it also has a higher resolution and a lower 1/ f corner.The energy-efficient read-out IC achieves a resolution of over21.9 bit in a conversion time of 200 ms. With several noisesuppression techniques, the 1/ f corner frequency is less than40 μHz. The read-out IC exhibits an average offset of 1.87 μV,a CMRR of 126 dB, and a PSRR of 121 dB. The performanceof the read-out IC is also verified by the demonstration systemof the weighing scale.

VII. CONCLUSION

An energy-efficient programmable-gain read-out IC hasbeen implemented in a standard 0.13-μm CMOS 1.5/3.3-Vprocess. On-chip gain programmability is achieved by aread-out IC using only a capacitive network, composed of aCCIA and an incremental SC �� ADC. In the power-hungryCCIA, a cascode Miller-compensated DDA with a class-ABoutput stage and clamp transistors is used to reduce staticcurrent. The two auxiliary loops of the RRL and the IBLare applied to suppress output chopper ripple and boost inputimpedance. In the incremental ADC, the gain programmablecharacteristic is embedded. To minimize the sampling error,the sampling timing of the ADC is well determined consider-ing chopper timing. Thanks to the second-order system-levelchopping, inner chopping, and CDS, low-frequency noise, andoffset are well suppressed. The prototype read-out IC achieves

a 21.9-bit ER, a 7-ppm INL, and a 40-μHz 1/ f corner whileconsuming only 507 μW.

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Jaehoon Jun (S’16) received the B.S. degree inelectrical and computer engineering from SeoulNational University, Seoul, South Korea, in 2013,where he is currently pursuing the Ph.D. degree inelectrical engineering and computer science.

He is currently focusing on the design of low-power high-resolution read-out interface circuitswith analog-to-digital converters for sensor applica-tions. His research interests include the design ofCMOS smart temperature sensors, humidity sensorinterface circuits, precision dc measurement inter-

face circuits for bridge transducers, and other MEMS sensor-applicationinterface circuits.

Soungchul Park (S’19) received the B.S. degreein electrical and computer engineering from SeoulNational University, Seoul, South Korea, in 2016,where he is currently pursuing the Ph.D. degree.

His research interests include analog andmixed-signal integrated circuits and systems.

Junho Kang (S’18) received the B.S. degree in elec-trical and computer engineering from Seoul NationalUniversity, Seoul, South Korea, in 2017, where heis currently pursuing the Ph.D. degree.

His research interests include the design of sensorinterfaces and data converters.

Suhwan Kim (S’97–M’01–SM’07) received theB.S. and M.S. degrees in electrical engineeringand computer science from Korea University, Seoul,South Korea, in 1990 and 1992, respectively, and thePh.D. degree in electrical engineering and computerscience from the University of Michigan, Ann Arbor,MI, USA, in 2001.

From 1993 to 1999, he was with LG Electronics,Seoul. From 2001 to 2004, he was a Research StaffMember with the IBM T. J. Watson Research Center,Yorktown Heights, NY, USA. In 2004, he joined

Seoul National University, Seoul, where he is currently a Professor ofelectrical engineering. His research interests include analog and mixed-signalintegrated circuits, high-speed I/O circuits, and silicon-photonic integratedcircuits.

Dr. Kim was a recipient of the 1991 Best Student Paper Award of the IEEEKorea Section, the First Prize (Operational Category) in the VLSI Design Con-test of the 2001 ACM/IEEE Design Automation Conference, the Best PaperAward of the 2009 Korean Conference on Semiconductors, and the 2011 BestPaper Award of the International Symposium on Low-Power Electronics andDesign. He served as a Guest Editor for the IEEE JOURNAL OF SOLID-STATE

CIRCUITS Special Issue on the IEEE Asian Solid-State Circuits Conference.He has also served as the Organizing Committee Chair for the IEEEAsian Solid-State Conference and the General Co-Chair and the TechnicalProgram Chair for the IEEE International System-on-Chip (SoC) Conference.He has participated multiple times on the Technical Program Committeeof the IEEE International SOC Conference, the International Symposiumon Low-Power Electronics and Design, the IEEE Asian Solid-State CircuitsConference, and the IEEE International Solid-State Circuits Conference.

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