A 10-mc/s, 0.5-μm CMOS constant-fraction discriminator having built-in pulse tail cancellation

$: A 10-mc/s, 0.5-μm CMOS constant-fraction discriminator having built-in pulse tail cancellation$
1130 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 49, NO. 3, JUNE 2002

A 10-Mc/s, 0.5-�m CMOS Constant-FractionDiscriminator Having Built-In Pulse Tail Cancellation

D. M. Binkley, Senior Member, IEEE, B. S. Puckett, Member, IEEE, B. K. Swann, Member, IEEE,J. M. Rochelle, Member, IEEE, M. S. Musrock, Member, IEEE, and M. E. Casey, Member, IEEE

Abstract—A 0.5- m, fully-integrated CMOS, constant-fractiondiscriminator (CFD) is presented for 10-Mc/s operation. The CFDutilizes a timing-shaping filter to provide amplitude insensitivetime discrimination without delay lines or other external com-ponents. Continuous-time baseline restorers are used to cancelCMOS dc offsets and provide signal tail cancellation for boththe arming and constant-fraction signals. Near total signal tailcancellation at 100 ns permits operation at count rates up to 10Mc/s. Measured intrinsic timing resolution is 40 to 90 ps FWHMfor a 3.7:1 input dynamic range and measured walk is 20 ps fora 2.7:1 dynamic range increasing to 80 ps for a 3.7:1 dynamicrange. Measured timing resolution for an LSO/PMT detectoragainst a plastic/PMT detector is 1.00-ns FWHM at low countrates increasing to 1.27-ns FWHM at 6.0 Mc/s. The CFD is partof a 0.5- m CMOS front-end integrated circuit designed forlarge-area, high-count-rate LSO or BGO detectors used in PETmedical imaging.

Index Terms—Analog CMOS integrated circuits, constantfraction discriminator (CFD), front-end electronics, nuclearpulse timing, positron emission togography (PET), pulse tailcancellation.

I. INTRODUCTION

CONSTANT fraction discriminator (CFD) time pickoff,being substantially free of time walk for varying input

pulse amplitude, is used for positron emission tomography(PET) and other systems requiring timing coincidence mea-surement. In recent years, the high detector density of modernPET systems has resulted in CMOS integration of the front-endelectronics, including fully integrated CFD circuits [1]. How-ever, these early systems were designed in 2-m CMOS foroperation at dead times of approximately 600 ns. The recentcommercialization of large-area LSO PET detectors requiresCFDs having substantially less dead time of 100 ns. A 0.5-mCMOS CFD meeting these requirements is presented here.

Manuscript received November 25, 2001; revised March 14, 2002. This workwas supported by CTI PET Systems, Inc., and Concorde Microsystems, Inc.

D. M. Binkley was with Concorde Microsystems, Inc., Knoxville, TN 37922USA. He is now with the Electrical and Computer Engineering Departmentat the University of North Carolina at Charlotte, Charlotte, NC 28223 USA(e-mail: [email protected]).

B. S. Puckett was with the University of Tennessee, Knoxville, TN 37901USA. He is now with Analog Devices, Inc., Greensboro, NC 27410 USA(e-mail: [email protected]).

B. K. Swann and J. M. Rochelle are with Concorde Microsys-tems, Inc., Knoxville, TN 37922 USA (e-mail: [email protected];[email protected]).

M. S. Musrock and M. E. Casey are with CTI PET Systems, Inc., Knoxville,TN 37922 USA (e-mail: [email protected]; [email protected]).

Publisher Item Identifier S 0018-9499(02)06143-9.

II. CFD OVERVIEW

A block diagram of the CMOS CFD is shown in Fig. 1.Constant-fraction (CF) shaping, normally done with an externaldelay line and attenuation network [2], is implemented in amonolithic shaping filter. In this shaping filter, an attenuatedversion of the CFD input signal is subtracted from a delayedversion of the input signal rendering an output-pulse zerocrossing time that is independent of input amplitude [3], [4].Inside the CF shaping filter, a five-pole lowpass filter providesthe needed signal delay, replacing the delay line used in thetraditional CFD [2]. A delay-select line allows the time delayto be selected at nominally 4.5 or 7.5 ns to accommodate eitherfast or slow rise-time photomultiplier tubes (PMTs).

Both the CF and arming circuits shown in Fig. 1 include con-tinuous-time baseline restorer (BLR) circuits to cancel dc base-line errors due to circuit offsets and varying event count rates.In addition, these BLR circuits provide built-in signal decay tailcancellation through continuous-time, wideband, negative feed-back. The pulse tail cancellation, needed for high count-rate op-eration, is illustrated at the CF and arming BLR outputs. The CFBLR circuit holds the CF signal baseline near zero whereas thearming BLR holds the arming signal baseline below zero by anamount equal to the selected CFD arming threshold.

A CF comparator is used to sense the zero crossing at theCF BLR output, providing the needed amplitude-independenttime pickoff. An arming comparator is used to enable or armtime discrimination only when the arming BLR output exceeds apreset CFD arming threshold. Arming logic provides traditionalarming where the CFD output is present whenever both armingand zero-crossing detection occur, or slow rise time reject (SRT)arming where the output is present only if arming precedes zero-crossing detection.

III. CIRCUIT OPERATION

A. Pulse-Tail Cancellation Methods

When the duration of a detector decay tail limits operationat high count rates, it is usually necessary to utilize pulse-tailcancellation to shorten the decay tail and permit a rapid returnto the baseline. When the decay tail is exponential, the zero ina pole-zero network can effectively cancel the pole associatedwith the tail decay [5]. The pole-zero network will necessarilyintroduce its own pole, but the time constant associated withthis pole can be made shorter than the original decay tail timeconstant. If the pole-zero network is tuned to the decay tail ofthe detector pulse, which may be due to either detector oper-ation or a pole in the detector preamplifier, the pulse duration

0018-9499/02$17.00 © 2002 IEEE

BINKLEY et al.: A CMOS CONSTANT-FRACTION DISCRIMINATOR HAVING BUILT-IN PULSE TAIL CANCELLATION 1131

Fig. 1. Block diagram of the CMOS CFD. The circuit uses a nondelay-line CF shaping filter for monolithic integration. Wideband, continuous-time baselinerestorers provide dc offset cancellation and pulse tail cancellation. The built-in pulse-tail cancellation permits operation at 10-Mc/s count rates.

can be reduced considerably. Pole-zero tail cancellation tech-niques have been reported in bipolar integrated circuits [6], [7]and CMOS integrated circuits [8] to reduce the long ion decaytail associated with proportional chamber detectors. Due to therequirements of tuning a pole-zero network over CMOS processvariations and the large decay time constant difference of LSOand BGO scintillation detectors (having 40 ns and 300 ns decaytime constants respectively), the pole-zero technique is not usedin the CMOS CFD presented here.

If the zero of a pole-zero network is placed at the origin (0 Hzor dc), the circuit reduces to a simple, single-pole high-passfilter. Such a circuit has the advantage of totally blocking dcsignals, including CMOS mismatch related voltages while elim-inating the need for tuning the zero frequency. This type of cir-cuit is used in a CMOS integrated circuit [9] for canceling thedecay associated with straw tube ionization chambers. The con-tinuous-time BLR used in the CMOS CFD presented here hassimilar response to the single-pole high-pass filter, providingpulse tail cancellation without tuning while also removing cir-cuit dc offsets.

B. Continuous-Time BLR for Pulse Tail Cancellation

Signal dc offset and pulse-tail cancellation is provided in theCMOS CFD by a continuous-time BLR conceptually illustratedin Fig. 2. Here error between the BLR output signal and a base-line reference causes output current in transconductor. Thiscurrent charges capacitor, changing its voltage so the BLRoutput error is cancelled through difference amplifier. Delayelement provides a sampling delay to minimize BLR can-cellation of the input signal leading edge.

If sampling delay is not present, , the BLR hasresponse given by

(1)

where

(2)

Fig. 2. Block diagram of the continuous-time BLR. The circuit removes dcoffsets and cancels the decay tail of the input signal.

The BLR response in (1) is equal to the response of asingle-pole CR highpass filter having gain of and timeconstant of as given in (2).

If an exponentially decaying scintillation detector signal withzero rise time is applied to the BLR with , the resultingoutput signal response is given by

(3)

where is the scintillator decay time constant. The time-do-main output signal for is then given by

(4)

If , effective pulse-tail cancellation is possiblewhere the first term in (4) is a desired, near-unity positive-de-caying exponential having the shorter highpass time constant,

and the second term is an undesired, much smaller nega-tive-decaying exponential tail having the longer scintillator timeconstant . This is illustrated in Fig. 3 for BGO and LSO de-tector signals applied to the BLR having an 8-ns highpass timeconstant.


Fig. 3. Illustration of pulse tail cancellation for BGO and LSO signals applied to BLR without sampling delay.

At high count rates, the undesired exponential tail (secondterm in (4)) results in a baseline shift that can be expressed as afraction of the desired signal peak (first term in (4)). This frac-tion for a periodic count rate having periodis found from thesum of previous pulse decay tails and is given by

(5)

For a BLR highpass time constant of 8 ns ( ns) anda periodic count rate of 10 MHz ( ns), (5) gives abaseline error of 1.8 for LSO ( ns) and 6.7 forBGO ( ns) signals. The baseline error without the BLRwould be much higher at 8.9 for LSO and 253 for BGOsignals as given by the summation in (5) without the multiplierof .

C. CFD Arming Signal

The detector signal connecting to the arming BLR (Fig. 1)in the CMOS CFD has finite rise time due to the rise time ofthe detector PMT and subsequent amplification stages. The de-tector signal rise time (10%–90%) is approximately 10 ns andis modeled here by a zero rise time signal applied to a lowpassfilter consisting of three real, 2.5-ns poles.

When this 10-ns rise-time signal is applied to the armingBLR, some cancellation occurs along the leading edge of thesignal. The addition of a sampling delay ( in Fig. 2) reducesthis leading-edge signal loss. Sampling delay is introduced bythree real, 1-ns real poles that approximate one deliberate andtwo parasitic poles in the CMOS implementation of the armingand CF BLRs.

Fig. 4. illustrates the arming BLR output for BGO and LSOdetector signals having 10-ns rise times. The output is shownwith and without the 3-ns sampling delay for a BLR highpasstime constant of 8 ns. There is a 28% increase in output signallevel for both BGO and LSO signals when the sampling delayis included. At 100 ns, the baseline error is4.4 (relative tothe peak output signal) for both BGO and LSO signals, withor without the sampling delay. The LSO baseline, however, de-cays much more rapidly at a time constant of 40 ns compared to300 ns for BGO. Increasing the sampling delay somewhat above3 ns would increase the BLR output signal level with little ef-fect on pulse tail cancellation. However, the sampling delay in-troduces extra phase shift in the BLR negative feedback loopaffecting feedback stability and response.

D. CFD Constant-Fraction Signal

In addition to connecting to the arming BLR, the detectorsignal also connects to the CF shaping filter (Fig. 1). This circuit,illustrated in Fig. 5, subtracts the input signal from a delayedversion having gain of two providing an output zero crossingthat is independent of input amplitude. This nondelay-line CFDcircuit, utilizing a signal fraction of one-half and delay providedby multiple real poles, is described in detail in [3], [4]. As de-scribed later, this circuit lends itself to monolithic CMOS im-plementation using a current-mode lowpass delay circuit.

Fig. 5 and other nondelay-line time pickoff circuits suitablefor monolithic integration are similar to the traditional CFD cir-cuit where a fraction of the input signal is subtracted from adelayed version of the input using a delay line [2]. One circuitutilizes the delay associated with the distributed resistance andcapacitance of monolithic structures, such as polysilicon resis-


(a)

(b)

Fig. 4. Illustration of pulse tail cancellation in CFD arming signals for (a) BGO and (b) LSO detector signals applied to BLR with and without sampling delay.

Fig. 5. Block diagram of CF shaping filter. This nondelay-line circuit providesan output zero crossing that is insensitive to input amplitude.

tors [10]. Another circuit subtracts a fraction of the input signalfrom a single-pole highpassed version of the input [11] givingequal response as the circuit of Fig. 5 for a single-pole delay [3].Additionally, it is possible to utilize a single-pole, highpass CRfilter to create an amplitude-independent zero crossing [12]. Thecircuit of Fig. 5, however, utilizes a high number (five) of iso-lated poles resulting in less deterioration in output zero-crossingrise time or slope.

Like the CFD arming channel, the CF channel utilizes a BLRto cancel circuit dc offsets and provide pulse-tail cancellation(Fig. 1). This BLR is identical to the one described for the

arming channel. Fig. 6 illustrates the CF BLR output for BGOand LSO detector signals having 10-ns rise times. Again, theoutput is shown with and without the 3-ns sampling delay fora BLR highpass time constant of 8 ns. There is a 33% increasein output signal level for both BGO and LSO signals when thesampling delay is included. At 100 ns (not shown in Fig. 6), thebaseline error is 3.7 (relative to the peak output signal) forBGO and 4.4 for LSO signals with the sampling delay. Asin the arming signals of Fig. 4, the baseline decays much morerapidly for LSO signals compared to BGO signals.

E. CFD Arming and CF Signals for 10-MHz Periodic Events

Fig. 7 shows the arming and CF signals for BGO signals at aperiodic count rate of 10 MHz, with and without the presenceof the BLRs. Fig. 8 shows the arming and CF signals for LSOsignals at the same count rate. Again, BLR time constants of8 ns are used along with a 3-ns sampling delay. Significantpulse pileup reduction is evident, especially for the BGOsignals (Fig. 7) where arming threshold discrimination and


(a)

(b)

Fig. 6. Illustration of pulse tail cancellation for (a) BGO and (b) LSO CF signals applied to BLR with and without sampling delay.

zero-crossing CF timing would be impossible without the pulsetail cancellation provided by the BLRs. The baseline error is

25 mV or 12.5% of the 200 mVpk signal for the BGO armingsignals. This error is 26 mV or 10.8% of the 240 mVpk signalfor the BGO CF signals. The baseline error is29 mV or 5%of the 580 mVpk signal for the LSO arming signals. This erroris 36 mV or 5% of the 725 mVpk signal for the LSO CFsignals.

F. CFD Arming and CF Signals for 10-Mc/s Random Events

Actual BGO and LSO signals are not periodic events butPoisson events occurring randomly in time. Monte Carlo simu-lation was performed in order to estimate the baseline mean andstandard deviation. Single event signals were convolved with aseries of impulses occurring randomly in time. The resulting sig-nals were sampled immediately before the impulses (or detectorevents) to assess the spectrum of the baseline signal. One mil-lion events were simulated at an average count rate of 10 Mc/sfor each baseline signal considered.

The Monte Carlo simulated baseline mean is9.3 mV or(4.7% of the 200 mVpk signal) with a standard deviation of60.9 mV (30.5% of the signal) for the BGO arming signals. Thebaseline mean is 8.4 mV (3.5% of the 240 mVpk signal) witha standard deviation of 76.3 mV (31.8% of the signal) for theBGO CF signals. The baseline mean is21.9 mV (3.8% of the580 mVpk signal) with a standard deviation of 171 mV (29.5%of the signal) for the LSO arming signals. The baseline mean is

19.5 mV (2.7% of the 725 mVpk signal) with a standard devi-ation of 217 mV (29.9% of the signal) for the LSO CF signals.

Interestingly, the simulated baseline means are less than thosereported in Section III-E for periodic events. However, the stan-dard deviation of the baseline signals is significantly greaterthan the means and is nearly 30% the signal peak for both BGOand LSO signals. This illustrates that there is considerable fluc-tuation of the baseline associated with the random time occur-rence of events. The baseline signals have a nonGaussian spectrahaving maximum density at zero volts with a decaying distribu-tion for negative voltages. This distribution appears somewhatexponential for LSO signals and asymmetrically Gaussian forBGO signals.


(a)

(b)

Fig. 7. Illustration of pulse tail cancellation for (a) arming and (b) CF signals for BGO signals applied at a periodic rate of 10 MHz.

IV. CMOS CIRCUITS

A. Description

A large number of custom, 0.5-m analog CMOS circuitsmake up the integrated CFD illustrated in Fig. 1. Differentialcurrent-mode and voltage-mode circuits are used in the armingand CF channels to minimize even-order distortion, powersupply noise coupling, noise coupling from other circuits, andsystematic circuit offsets. Traditional CMOS logic circuits areused for the arming logic with the exception of flip flops that

have been designed for low metastability to maximize logicperformance for signals near the CFD threshold.

Fig. 9 is a single-ended depiction of the differential circuitsused in the CF shaping filter and its associated BLR. The CFDdetector input voltage is converted to multiple signal currents( ) by an input transconductor and current mirror system.One signal current is delayed and given a current gain of two( ). Another signal current is subtracted from this currentgiving an output CF current ( ). This current is converted tovoltage ( ) by low-capacitance high-resistance polysilicon


(a)

(b)

Fig. 8. Illustration of pulse tail cancellation for (a) arming and (b) CF signals for LSO signals applied at a periodic rate of 10 MHz.

resistors (two of these since all signals are differential). Thisvoltage is sampled by the BLR circuit which provides a correc-tion current ( ) to cancel circuit dc offsets and the signaldecay tail. The differential output voltage ( ) provides anamplitude-independent zero crossing that is sensed by the CFcomparator.

The BLR circuit of Fig. 9 consists of an operational transcon-ductance amplifier (OTA) designed for linear operation at inputvoltages up to approximately 1 V. The current output of this OTAfeeds an internal compensation capacitor creating a correction

voltage. This voltage is sensed by another OTA that provides thenecessary BLR output correction current. Unlike the gated BLRcircuits used in a previous 2-m PET front-end integrated cir-cuit [1] and described in [13], the BLRs in the 0.5-m CMOSCFD operate with continuous-time negative feedback.

Fig. 10 shows an abbreviated schematic of the five-pole delaycircuit shown in Fig. 9. This is a differential current-mode cir-cuit consisting of grounded-gate MOSFETs where signal polesare introduced by the addition of poly-poly capacitors betweenthe MOS sources and ground. This results in the introduction of


Fig. 9. CMOS implementation of CF shaping filter with BLR for circuit dcoffset and signal tail cancellation. The actual circuit utilizes differential signalpaths.

Fig. 10. Abbreviated schematic of CMOS current-mode delay circuit used inCF fraction shaper. Three of the five lowpass poles are shown.

independent, isolated real poles having time constants of 0.9 nsas approximated by , where is the total source ca-pacitance and is the MOS transconductance. The pole timeconstants are increased to 1.5 ns when differential capacitorsare introduced across related MOS sources. These capacitorsare connected by MOS switches to provide a “long” CF delaysetting of approximately 7.5 ns compared to the normal settingof approximately 4.5 ns. This permits the use of slower rise timePMTs in scintillation detectors.

Low-voltage biasing techniques are used to set the gate biasof the grounded gate MOS devices in Fig. 10. This permits amaximum number of ground-gate stages without the introduc-tion of current mirrors. The use of grounded-gate MOS stagesdriven from high impedances (current mode) significantly re-duces the introduction of MOS dc mismatch and noise due tothe high level of MOS source degeneration. External transcon-ductor and current mirror circuits dominate the MOS dc mis-match and noise of these grounded-gate stages.

Circuitry for the CFD arming channel is similar to that of theCF shaper shown in Fig. 9, except the signal delay and signalsubtraction circuits are omitted. Here, the input signal currentsare summed with the BLR output currents with the differential

arming voltage sensed by the BLR circuit. An integrated 8-banalog-to-digital converter provides a deliberate CFD thresholdoffset at the input of the arming BLR. This lowers the armingbaseline by the selected CFD threshold such that the armingcondition is met when the arming signal exceeds zero.

B. Performance Simulations

Post-layout SPICE simulations were performed on the fullCMOS CFD for statistically noiseless LSO and BGO detectorsignals at a periodic rate of 10 MHz. Signals representing 1x,0.5x and 1.5x photopeak levels were used to simulate a 3:1 dy-namic range.

The differential arming and CF signal voltages simulated inthe CMOS CFD closely match those shown in Figs. 7 and 8for BGO and LSO signals, respectively, with the exception that1x, 0.5x and 1.5x signals are used in the CMOS simulations.The simulated BGO arming signal is 142 mVpk (1x) having abaseline error shift of 18 mV or 12.7% of the peak signal. Thesimulated BGO CF signal is 188 mVpk (1x) having a baselineerror of 20 mV or 10.6% the signal peak. The simulated LSOarming signal is 480 mVpk (1x) having a baseline error shiftof 25 mV or 5.2% of the peak signal. The simulated LSO CFsignal is 680 mVpk (1x) having a baseline error of34 mV or5% the signal peak. The BGO signals are smaller because ofthe smaller input levels required due to severe pulse pileup (seeFig. 7).

Since the simulated CMOS CFD signals for periodic eventsat 10 MHz closely match the signals shown in Figs. 7 and 8, it isexpected that the mean and standard deviation of the baselineswould be similar to those predicted in Section III-F for randomevents at 10 Mc/s. Here the baselines were found to have max-imum density at zero volts with a decaying distribution for neg-ative baseline voltages.

Time pickoff error for the CMOS CFD was simulated for10-MHz periodic events including the arming and CF compara-tors and the arming logic in addition to the arming and CF cir-cuits previously described. A 1.2-ns peak-to-peak timing error isobserved for 10-MHz BGO signals over the 3:1 dynamic range.This time pickoff error is much less at 350 ps peak-to-peak forthe larger LSO signals at the same rate and dynamic range.

Most of the time pickoff error is time walk for the 3:1 dy-namic range input due to the presence of a nonzero baselineat the CF signal. This baseline error, described above, is ap-proximately 10% and 5% of the BGO and LSO CF pulses re-spectively for 1x photopeak signals at a count rate of 10 MHz.The baseline error reduces to near zero at low count rates, beinglimited only by the CMOS mismatch offset at the input of theCF BLR circuit. The presence of input amplitude induced CFDtime walk caused by CF baseline error is discussed in detail in[14]. Measured CFD amplitude walk, described later, is only80 ps for a 3.7:1 dynamic range at low count rates where theCF baseline is nearly zero. High count rate walk timing errorsof 1.2 ns (BGO) and 350 ps (LSO) peak-to-peak should negli-gibly increase timing resolution above the intrinsic timing reso-lution of approximately 3 ns (BGO) and 1 ns (LSO) FWHM forLSO/PMT and BGO/PMT scintillation detectors.

The CMOS CFD simulations do not include the statisticalnoise of the detectors and the statistical occurrence of overlap-


Fig. 11. Measured intrinsic timing resolution and walk.

ping pulses associated with random events in time. Simulationof timing resolution and energy cutoff resolution of CFD circuitsis described in [15] where scintillation statistical noise, PMTsingle-electron response and transit time spread, and impulseresponse of the front-end and CFD circuits are used in MonteCarlo simulations. This assumes the front-end CFD circuits aresufficiently linear. These Monte Carlo simulations can be fur-ther expanded to include pulse pileup and baseline fluctuationassociated with random detector events at high count rates.

Although not studied in detail, initial Monte Carlo timingsimulations were performed considering the pulse pileup andbaseline fluctuation simulations described in Section III-F.These simulations indicate the non-Gaussian baseline spectrumdistorts the CFD timing spectrum some from the normalGaussian spectrum expected. A Gaussian timing spectrum isexpected for timing on a large number of photoelectrons with orwithout the presence of Gaussian electronic noise or Gaussianbaseline fluctuation at high count rate.

CMOS CFD timing jitter, measured at 90 ps FWHM or lessas described below, is much easier to predict than the resolutiondue to detector statistical noise and pulse pileup, especially sincethe CF shaping circuit is a continuous-time circuit. Steady-statenoise analysis (or SPICE simulation with accurate MOS noisemodels) can be used to find the CF signal noise. Timing jitter isthen found by dividing the total rms noise on the CF signal bythe zero-crossing slope. This assumes the CF signal noise suf-ficiently exceeds the noise present at the input of the CF com-parator.

V. MEASUREDPERFORMANCE

The 0.5- m CMOS CFD was fabricated using the MOSISfabrication service. Fig. 11 shows measured intrinsic timing res-olution and walk for voltage pulse inputs having a 2-ns rise time,

increased to approximately 5 ns by the input transconductorsystem that provides signal currents to the CFD circuits. Jitterdecreases from 90 ps FWHM (23-mV input) to 40 ps FHWM(85-mV input). Walk is 20 ps for inputs between 23 and 63 mV(2.7:1 dynamic range), increasing to 80 ps for inputs between 23and 85 mV (3.7:1 dynamic range). The increase in walk for the85-mV input signal, corresponding to a differential CFD inputcurrent of approximately 170A for a 2-mS transconductancein the input transconductor system, is due primarily to time dis-tortion in the current-mode delay circuit (Fig. 10). Here, a largesignal current causes device currents to deviate measurably fromtheir fixed dc bias currents.

Fig. 12 shows measured energy discrimination at fourthreshold levels for a LSO/PMT detector excited by aNasource. The gated energy spectra indicate the CFD armingthreshold can be set at 150 keV to essentially collect allevents surrounding a 511-keV photo peak associated with PETapplications.

Measured timing resolution for a LSO/PMT detector andreference plastic/PMT detector is 1.0 ns FWHM and 1.8 nsFWTM at count rates below 400 kcps when excited by aNasource. The timing resolution increases to 1.12, 1.21 and 1.27ns FWHM for count rates of 1.4, 3.2 and 6.0 Mc/s respectively.Timing resolution at the count rate of 6.0 Mc/s is illustratedin Fig. 13. An FWTM measure of timing resolution is notmeaningful at this count rate where the random coincidencerate approaches or exceeds 10% the timing photopeak value.An F source is used for the high count rate data and theenergy threshold for all timing measurements was 250 keV.

VI. CONCLUSION

A fully-integrated, 0.5- m CMOS CFD has been designedand evaluated for high-count-rate PET applications. Measured


Fig. 12. Measured energy discrimination at four threshold levels forNa source and LSO/PMT detector.

Fig. 13. Measured timing resolution for a LSO/PMT detector with plastic/PMT reference detector excited by anF source at a count rate of 6.0 Mc/s.

timing jitter and walk (3.7:1 dynamic range) are under 100 psFWHM and low count-rate timing resolution for a LSO/PMTdetector against a plastic/PMT detector is 1.0 ns FWHM and 1.8ns FWTM. The timing resolution degrades modestly to 1.27 nsFWHM at a count rate of 6.0 Mc/s.

The complete CMOS CFD was simulated at the transistorlevel by SPICE for detector signals over a 3:1 dynamic rangeat a periodic count rate of 10 Mc/s. These simulations show apeak-to-peak timing error of 350 ps for LSO signals and 1.2 nsfor BGO signals, the BGO signals exhibiting severe pileup(over 250%) prior to the BLR circuits. These simulationssuggest the CMOS CFD will degrade timing resolution onlyslightly above the intrinsic resolution of LSO/PMT (approx-

imately 1 ns FWHM) and BGO/PMT (approximately 3 nsFWHM) detectors at high count rates.

Methods for Monte Carlo performance simulation weredescribed to include detector statistical noise and pulse pileupat high count rates. These effects were intrinsically consideredin the measurements. The CMOS CFD is part of a 0.5-mfront-end integrated circuit designed for large area, high countrate LSO or BGO detectors used in PET medical imaging.

ACKNOWLEDGMENT

The authors wish to acknowledge C. Hopper, University ofNorth Carolina at Charlotte, for assistance in preparing thispaper.


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A 10-mc/s, 0.5-μm CMOS constant-fraction discriminator having built-in pulse tail cancellation

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