Post on 10-Sep-2020
Kunal Datta and Prof. Hossein HashemiMing Hsieh Department of Electrical Engineering
Contact: Kunal Datta (213)-587-1109, kdatta@usc.edu
220 fF
10 Ω
400 fF
96 pH
VIN
48 pH 200 fF
80 pH
10 pF
2 x 16 m40 pH
75 Ω
52 pH
150 fF
10 Ω
400 fF
96 pH
Vb_Core VOUT
260 Ω
260 Ω
42 fF
VCC_Driver
86 pH
10 pF
6 x 16 m
VCC_Core
44 pH
1.7mm
1mm
Performance at Peak Pout
Performance Metric Simulated Performance Measured Performance
Technology Node IBM 130nm SiGe BiCMOS IBM 130nm SiGe BiCMOS
Center Frequency / BW-1dB 39 GHz / 3.5 GHz 39 GHz / 4 GHz
Output Power 19.2 dBm (84 mW) 19.6 dBm (91 mW)
Power Gain 8 dB 8.9 dB
Drain Efficiency (η) 25.5% 16.1%
PAEMAX 21.4% 14%
1.3mm
0.8m
m
200 fF
140fF
VC
L1
C12
Vout
L2
500fF10K
58pH
51pH
100Ω
46pH
60fF6x12um
6x16um
VCC_Core
VBias
10 pF
Avalanche Compensated Bias Circuit
140 fF
10 Ω
250 fF
96 pH
48 pH
80 pH
10 pF
2 x 16 m62 pH
75 Ω
VCC_Driver
VIN
Performance Metric Simulated Performance
Technology Node IBM 130nm SiGe BiCMOS
Center Frequency / BW-1dB 45 GHz / 4 GHz
Output Power 22.15 dBm (165 mW)
Power Gain 11.5 dB
Drain Efficiency (η) 31.5%
PAEMAX 29%
140 fF
10 Ω
250 fF
96 pH
48 pH
80 pH
10 pF
2 x 16 m62 pH
75 Ω
VCC_Drive
r
VIN
VCC_Core
Vout
500fF
1K
58pH
1K
140fF
46pH
60fF6x12um
6x16um
6x12um60fF
100Ω
500fF
VBias_Cor
e
Avalanche Compensated Bias Circuit
1.3mm
0.8m
m
Performance Metric Simulated Performance
Technology Node IBM 130nm SiGe BiCMOS
Center Frequency / BW-1dB 45 GHz / 4 GHz
Output Power 23.4dBm (220 mW)
Power Gain 12.7dB
Drain Efficiency (η) 25%
PAEMAX 24%
t
Control Bits (n)
Unit Module Output Power
(Pout)
Total PowerCombining Loss (0.5dB
per combiner)
Total Output Power
(Pout_Total)
Pout_Total
Resolution (2n)
System PAE (25% PAE per unit module)
225.0dBm (316mW)
1.0dB 30dBm 4 19.8%
322.5dBm (176mW)
1.5dB 30dBm 8 17.6%
420.0 dBm(100mW)
2.0dB 30dBm 16 15.6%
517.5 dBm(56mW)
2.5dB 30dBm 32 14%
Port 1
Port 2
Port 3
120μm
80μm
920μ
m
80μm
M2
50μm
8.5μm
AM
Wilkinson Power Combiner
RFin RFout
Unit Module
VCC
Unit Module
VCC
Unit Module
VCC
Unit Module
VCC
Technological Constraints
Topological Constraints
Pout
PA
E
Linear
Saturated
Desired
Class A
Class D,E,F
ClassBClass C
Linearity
PA
E
Linear PA
Saturated PA Desired Performance
Breakdown voltage of transistors scale down with increasing fT & fmax. Vbreakdown < 6 V (in 130nm SiGe process), hinders watt-level power
generation.
Efficiency decreases with frequency due to -20 dB/dec roll off in power gain.
Higher ohmic loss in passives at higher frequency (due to lower skin depth)degrades efficiency.
Peak efficiency in linear PAs degrade with power back-off.
Maintaining high efficiency with power back off is essential for modulatingsignals with high Peak to Average Power Ratio (PAPR) (as in OFDM).
Saturated/switching PAs can give higher efficiency but at the cost of linearity.
a(n)
Modulator+
Rect-to-Polar
(n)
Calibration and Control
Sensing RecieverAM-AM, AM-PM, Phase Error, Delay, Sensing Receiver Calibration
Miscellaneous Controls
Data In
AM-PM Pre-distortion
AM-AM Pre-distortion
LUTs
Digital Baseband
Serial Port Interface
Crystal
XTAL Oscillator
Digital ΔΣ Modulator
I/Q VCO
Digital to Phase Converter (DPC)
PLL
Binary-to-Therm
Saturated PA Array + Combiner
Digital Envelope Combiner (DEC)
Phase Skew Calibration
FDEC
FDPC
I-Q & Phase Calibration
Ref
Q
Synthesizer
Digital ΔΣ Modulator
Nn
m1
2
N
VDD
VDD
VDD
Phase Distribution
Clock Gen I
RF Out
Saturated/switching class PAs in individual power modules for high efficiency.Amplitude modulation using low-loss switching supplies. Phase modulation using phase-shifters. ∆Σ modulators for minimizing in-band quantization noise. Digital polar architecture ensures high PAE at both peak and average power.
Active Device ON
Active Devices OFF
VCC
VoutVC
L1iL
iDevice iload
RLoad
XL
L2 C2
VB+VSIG
VCC
Vou
tVC
L1
isw
RLoad
XL
L2 C2
ron
VC
tVB+VSIG
Vin
VCC
VoutVC
L1
iCRLoad
L2 C2
Csub
t
VC
XL
VB+VSIG
Vin
t
Vin
VC
Vout
IDevice
High VCC (for higher Pout) causes avalancheinduced base instability.
Interconnect parasitic degrade fMAX of the deviceand lower performance.
Passive networks must be properly chosen tohave high enough self resonating frequency.
Passive structures and interconnect are modeledusing electromagnetic simulators.
Small signal and large signal stability areanalyzed using periodic steady state simulations.
Avalanche phenomenon can be alleviated byusing series stacking of transistors to increasestability margin without compromising powerand PAE performance.
VCC
VoutVC
L1
C12
iL
iDevice
iCiload
RLoad
XL
L2 C2
C11
Vmid
CC RDC2
RDC1
VB+VSIG
VBias
t
Vbe1
Vbe2
Vmid
VC
t
Vout
IC
Vb2
Vb1
Active Devices ON
VCC
Vout
VC
L1
isw
RLoad
XL
L2 C2
Vmid
Cπ2
CC RDC2
RDC1
ron
ron
t
t
VBias
VB+VSIG
t
Vb1
Vb2
Vb2
Vb1
VCC
VoutVC
L1
C12
iC RLoad
XL
L2 C2
C11
Vmid
Cπ2
CCRDC2
RDC1
Vmid
t
VC
Vmid
t
Vb2
VBias
VB+VSIG
Vb1
t
Vb1
Vb2
Active Devices OFFSeries stacking of devices ensure
higher voltage swing across the same load resulting in higher output power
Measurement of stacked devices.
Large signal characterization andmodeling of SiGe HBTs.
Designing other blocks of the digitalpolar transmitter.
Large signal nonlinear stabilityanalysis.
Deriving efficiency limit of activedevices in power amplifierimplementation.
Analyzing trade-off of performancevs stability in mm-wave poweramplifiers.
Watt-Level Efficient Linear Power Amplifier in Sillicon
Technology BiCMOS
Frequency 45 GHz
Peak Power 36 dBm
Power Added Efficiency (PAE)at peak power
65%
RF Bandwidth 3.5 GHz
Data rate (64 QAM) 0.520 Gbps
Bandwidth 100 MHz
Error Vector Magnitude (EVM) < 2%
ACPR @ 1*BWch < –55 dBc
High Data Rate Wireless CommunicationActive RadarsActive mm-Wave Imaging
23GHz 29GHz 35GHz 59GHz 64GHz 71GHz 76GHz 81GHz 86GHz 92GHz 95GHz 110GHz 122GHz
Automotive Radar
Radio Navigation
MilitaryISM
Fixed Wireless
Fixed Wireless
Fixed Wireless
Radio Astronomy
ISM
Automotive Radar
mm-Wave Spectrum Allocation
H2O
O2
O2
Absorption Spectra