Post on 16-Mar-2016
description
A 4th Order Continuous-Time ADC with VCO-Based Integrator and Quantizer
ISSCC 2009, Session 9.5
Matt Park1, Michael H. Perrott2
1 Massachusetts Institute of Technology, Cambridge, MA USA2 SiTime Corporation, Sunnyvale, CA, USA
2Motivation
A highly digital receive path is very attractive for achieving multi-standard functionality A key issue is achieving a wide bandwidth ADC with high
resolution and low power- Minimal anti-alias requirements are desirable for simplicity
Continuous-Time Sigma-Delta ADC structureshave very attractive characteristics for this space
LNA
ADC
AnalogAnti-Alias
Filter
DigitalChannel
Filter
ADC
cos(wot)
sin(wot)
I
Q
SampleClock
3A Basic Continuous-Time Sigma-Delta ADC Structure
Sampling occurs at the quantizer after filtering by H(s) Quantizer noise is shaped according to choice of H(s)
- High open loop gain required to achieve high SNR
DAC
H(s)
clock
IN OUT
Multi-LevelQuantizer
We will focus on achieving an efficient implementationof the multi-level quantizer by using a ring oscillator
4 Input: analog tuning of ring oscillator frequency Output: count of oscillator cycles per Ref clock period
Ring Oscillator
Register
Reset
Ref
Count
Out
Ref
Count
Counters
Out 15 30
VtuneVtune
OscillatorPhases
12 21
Alon, Stojanovic, HorowitzJSSC 2005
Kim, Cho, ISCAS 2006
Similar approaches:
Application of Ring Oscillator as an ADC Quantizer
5VCO-Based Quantizer Also Shapes Delay Mismatch
Barrel shifting through delay elements- Mismatch between delay elements is first order shaped
Enable
Enable
Enable
Enable
Measurement 1
Measurement 2
Measurement 3
Measurement 4
6Benefits of VCO-based Quantization
Much more digital implementation- No resistor ladder or differential gain stages
Offset and mismatch is not of critical concern Metastability behavior is improved
A
A
IN
A
CLK
Vdd
N
1
1
0
N-Stage Ring Oscillator
N-bit Register
Pre-Amp Comparator
N-Stage
Resistor
Ladder
IN
CLK
110 01
Buffer
Vdd
Implementation is high speed, low power, low area
7VCO
1- z-1
Quantizer
First Order
Difference
Ref
Vtune Out
2Kv
s1- z-1
T
1
T
Vtune Out
VCO Sampler
VCO
Noise
Quantization
Noise
First Order
Difference
ff
-20 dB/dec
Output
Noise
f
20 dB/dec
VCO KvNonlinearity
Frequency Domain Model of VCO Quantizer
VCO modeled as integrator and Kv nonlinearity Sampling of VCO phase modeled as scale factor of 1/T Quantizer modeled as
addition of quantization noise
Key non-idealities:- Quantization noise
- First order shaped!- VCO noise- VCO Kv nonlinearity
8Example SNDR with 20 MHz BW (1 GHz Sample Rate)
105 106 107 108-100
-80
-60
-40
-20
0
20
40
60
Frequency (Hz)
A
m
p
l
i
t
u
d
e
(
d
B
)
Simulated ADC Output Spectrum
2Kv
s1- z-1
1
T
Vtune Out
VCO Sampler
VCO
Noise
Quantization
Noise
First Order
Difference
ff
-20 dB/dec
Output
Noise
f
20 dB/dec
VCO KvNonlinearity
Conditions SNDR
Ideal 68.2 dB
VCO Thermal Noise 65.4 dB
VCO Thermal + Nonlinearity 32.2 dB
VCO Kv nonlinearity iskey SNDR bottleneck
Kvco: 5% linearityVCO noise:-100
dBc/Hz@ 10 MHz
9Reducing the Impact of Nonlinearity using Feedback
Place VCO-based quantizer within a continuous-time Sigma-Delta ADC structure- Quantizer nonlinearity suppressed by preceding gain
stage
Iwata, Sakimura, TCAS II, 1999Naiknaware, Tang, Fiez, TCAS II, 2000
VCO-based
Quantizer
Gain and
Filtering
DAC
Vtune
Ref
In Out
Peak SNDR limited by Kv non-linearity to 67 dB (20 MHz BW)10
A Second Order Continuous-Time Sigma-Delta ADC
DOUT
VIN
973 MHz
IDAC1 IDAC2
Vtune
VA V
B
VCO-based Quantizer & Barrel-Shift
DEM
31
Straayer, PerrottVLSI 2007
Third order noise shaping with a second order structure!
0.13u CMOS IC
How Do We Overcome Kv Nonlinearity to Improve SNDR?
11
Voltage-to-Frequency VCO-based ADC (1st Order )
In prior work, VCO frequency is desired output variable- Input must span the entire non-linear voltage-to-frequency
(Kv) characteristic to exercise full dynamic range- Strong distortion at extreme ends of the Kv curve12
Proposed Voltage-to-Phase Approach (1st Order )
VCO output phase is now the output variable- Small perturbation on Vtune allows large VCO phase shift- VCO acts as a CT integrator with infinite DC gain
13High SNDR requires higher order
Proposed 4th Order Architecture for Improved SNDR
Goal: ~80 dB SNDR with 20 MHz bandwidth- Achievable with 4th order loop filter, 4-bit VCO-based quantizer- 4-bit quantizer: tradeoff resolution versus DEM overhead
Combined frequency/phase feedback for stability/SNDR14
Schematic of Proposed Architecture
Opamp-RC integrators- Better linearity than Gm-C, though higher power
Explicit DWA
15
Schematic of Proposed Architecture
Passive summation performed with resistors- Low power- Must design carefully to minimize impact of parasitic pole
Explicit DWA
16
Schematic of Proposed Architecture
DEM explicitly performed on phase feedback- NRZ DAC unit elements
DEM implicitly performed on frequency feedback- RZ DAC unit elements (Note: Miller, US Patent (2004))
17
Behavioral Simulation (available at www.cppsim.com)
VCO Kv non-linearity Device noise Amplifier finite
gain, finite BW DAC and VCO
unit element mismatch
Key Nonidealities
VCO nonlinearity is not the bottleneck for achievable SNDR!
0.1 1.0 10.0 100.0-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20FFT PLOT
ANALOG INPUT FREQUENCY (MHz)
A
M
P
L
I
T
U
D
E
(
d
B
)
Only VCO Kv
Non-Linearity:
SNDR ~ 95 dB
Selected Noise,
Non-Linearity:
SNDR ~ 85 dB
20 MHz Bandwidth
85 dB SNDR!
Circuit Details
19
en0 en1 en2 en4
en0 en1 en2 en4
VCO Integrator Schematic
15 stage current starved ring-VCO - 7 stage ring-VCO
shown for simplicity- Pseudo differential
control- PVT variation
accommodated by enable switches on PMOS/NMOS
Rail-to-rail VCO output phase signals (VDD to GND)
Straayer, VLSI 2007
20
VCO Quantizer Schematic
Phase quantization with sense-amp flip-flop - Single
phase clocking
Rail-to-rail quantizer output signals (VDD to GND)
Nikolic et al, JSSC 200021
outm outp
inp inm
clk
clk
clk
d
d
q
q
d
d
q
q
d
d
q
q
d
d
q
q
d
d
q
q
d
d
q
q
d
d
q
q
Phase Quantizer, Phase and Frequency Detector
Phase OutputFrequency Output
d
d
q
q
d
d
q
q
d
d
q
q
d
d
q
q
d
d
q
q
d
d
q
q
d
d
q
q
22
Highly digital implementation- Phase sampled &
quantized by SAFF- XOR phase and
frequency detection with FF and XOR
Automatic DWA for frequency detector output code- Must explicitly
perform DWA on phase detector output code
iout,m
iout,p
Retiming
Flip-Flop
Low-Swing
Buffer
Current DAC
Unit-Element
clk
data
D
DB
Q
QB iout,p
iout,m
am
ap
Vinp
VDD
VSS
Vinm
Vinp
Vbias,n
Vcasc,n
VinmVinp
i
o
u
t
,
m
i
o
u
t
,
p
(same cell for Vinm) Low-swing
buffers- Keeps switch
devices in saturation
- Fast on / Slow off reduces glitches at DAC output
- Uses external Vdd/Vss
Resistor degeneration minimizes 1/f noise
Main Feedback DAC Schematic
Yan et alJSSC 2004
Bit-Slice of Minor Loop RZ DAC
RZ DAC unit elements transition every sample period- Breaks code-dependency of transient mismatch (ISI)- Uses full-swing logic signals for switching
PMOS Drivers
NMOS Drivers
up
dump,p
clk
clkb
VDD
datab
clkb
data
clkVDD
dump,n
inp
inm
inp
up
outp outm
inm
Vcasc,n
Vbias,n
Vcasc,p
Vbias,p
dump,n
dump,p
vcm
24
Opamp Schematic
Modified nested Miller opamp- 4 cascaded gain stages, 2
feedforward stages- Behaves as 2-stage Miller near
cross-over frequencies- Opamp 1 power is 2X of
opamps 2 and 3 (for low noise)
Parameter ValueDC Gain 63 dBUnity-Gain Frequency 4.0 GHzPhase Margin 55Input Referred Noise Power (20 MHz BW)
11 uV (rms)
Power (VDD = 1.5 V) 22.5 mW
Mitteregger et al, JSSC 2006
25
Gm Gm
Gm
inm
inp
Vcm Vcm
Vcm
Vbp
VbnVcm
outp
outm
DEM Architecture (3-bit example)
Achieves low-delay to allow 4-bit DEM at 900 MHz- Code through barrel shift propagates in half a sample period
Therm. to Binary
Barrel Shift8 8
5 2 3 65 2 3 6
3 3
Accumulator
clk
NRZDACInputs
PhaseQuantizerOutput
See also:Yang
ISSCC 2008
Die Photo (0.13u CMOS)
Die photo courtesy of Annie Wang (MTL)
27
Active area 0.45 mm2
Sampling Freq 900 MHz
Input BW 20 MHz
Supply Voltage 1.5 V
Analog Power 69 mW
Digital Power 18 mW
SNDR (20MHz)SNR (20MHz)
0-10-20-30-40-50-60-70-80
0
20
40
60
80
100
-20
S
N
D
R
/
S
N
R
(
d
B
)
M
a
g
n
i
t
u
d
e
(
d
B
)
0
20
40
60
80
100
-20
-40
Input Amplitude (dBFS)0.1 1.0 10.0 100.0
Frequency (Hz)
100,000 pt. FFT
Peak SNDR = 78.1 dBPeak SNR = 81.2 dB
Measured Results
78 dB Peak SNDR performance in 20 MHz- Bottleneck: transient mismatch from main feedback DAC
Architecture robust to VCO Kv non-linearity
28Figure of Merit: 330 fJ/Conv with 78 dB SNDR
Transient DAC mismatch is likely the key bottleneck
Behavioral Model Reveals Key Performance Issue
Amplifier nonlinearity degrades SNDR to 81 dB DAC transient
mismatch degrades SNDR to 78 dB- DEM does
not help- Could be
improved with dual RZ structure0.1 1.0 10.0 100.0
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20FFT PLOT
ANALOG INPUT FREQUENCY (MHz)
A
M
P
L
I
T
U
D
E
(
d
B
)
Only VCO Kv
Non-Linearity:
SNDR ~ 95 dB
Selected Noise,
Non-Linearity:
SNDR ~ 78 dB
20 MHz Bandwidth
Conclusion
VCO-based quantization is a promising component to achieve high performance ADC structures- High speed, low power, low area implementation- First order shaping of quantization noise and mismatch- Kv non-linearity was a limitation in previous approaches
Demonstrated a 4th-order CT ADC with a VCO-based integrator and quantizer- Proposed voltage-to-phase conversion to avoid
distortion from Kv non-linearity- Achieved 78 dB SNDR in 20 MHz BW with 87 mW power Key performance bottleneck: transient DAC mismatch
30
A 4th Order Continuous-Time ADC with VCO-Based Integrator and QuantizerISSCC 2009, Session 9.5MotivationA Basic Continuous-Time Sigma-Delta ADC StructureApplication of Ring Oscillator as an ADC QuantizerVCO-Based Quantizer Also Shapes Delay MismatchBenefits of VCO-based QuantizationFrequency Domain Model of VCO QuantizerExample SNDR with 20 MHz BW (1 GHz Sample Rate)Reducing the Impact of Nonlinearity using FeedbackA Second Order Continuous-Time Sigma-Delta ADCHow Do We Overcome Kv Nonlinearity to Improve SNDR?Voltage-to-Frequency VCO-based ADC (1st Order S-D)Proposed Voltage-to-Phase Approach (1st Order S-D)Proposed 4th Order Architecture for Improved SNDRSchematic of Proposed ArchitectureSchematic of Proposed ArchitectureSchematic of Proposed ArchitectureBehavioral Simulation (available at www.cppsim.com) Circuit DetailsVCO Integrator SchematicVCO Quantizer SchematicPhase Quantizer, Phase and Frequency DetectorMain Feedback DAC SchematicBit-Slice of Minor Loop RZ DACOpamp SchematicDEM Architecture (3-bit example)Die Photo (0.13u CMOS)Measured ResultsBehavioral Model Reveals Key Performance IssueConclusion