Report - 16-Bit 1-of-2 FET Multiplexer/Demultiplexer (Rev. K · 2011. 8. 6. · SEL TEST L L A = B1 H L A = B2 X H A = B1 and A = B2 logic diagram (positive logic) 8B1 1B1 8A 1A SEL1 1B2 8B2

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