RMO4C-2

A Low-Noise 40-GS/s

Continuous-Time Bandpass ΔΣ ADC

Centered at 2 GHz

Theo Chalvatzis and Sorin P. Voinigescu

The Edward S. Rogers Sr.

Department of Electrical and Computer Engineering

University of Toronto

Toronto, Canada

RFIC - San Francisco June 11-13, 2006

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Outline

• Motivation

• ADC system level architecture

• Circuit design

• Measurements

• Conclusion

RFIC - San Francisco June 11-13, 2006

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Motivation• Direct sampling receiver for 2-GHz CDMA basestation

• Transistor fT of 150..250 GHz and low-BVCEO naturally point to

1-bit ΔΣ digitization of RF signal

• Continuous-Time Bandpass ΔΣ topology offers:– Higher resolution and lower power than other ADC types– Low complexity (simple layout is important at 40 GHz!)– LNA as input stage

LNA

High-Speed ADCDuplexer/BPF

TO DSP

Digital Receiver

RFIC - San Francisco June 11-13, 2006

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System Level Architecture

• 2-GHz Gm-LC BPF

• 1-bit quantizer as DFF

• RZ pulse DACs

• Loop design in s-domain

2m1 m2

2 22 2

o

2m2fb2 fb1

2 2 22 2 2 2

o o

G G s DAC(s)C s +ω

H(s)=

G G Gs s1+ + DAC(s)C Cs +ω s +ω

DAC(s) the TF of RZ DAC

D

Q

Gm2

RZDAC1

RZDAC2

CLOCK

2GHz BPF 2GHz BPFDFF

DIGITAL

OUTPUT

DRIVERRF

INPUTG

m1

CLOCKTREE

Fs=40GHz

Gfb1

Gfb2

LNA & BPF1 BPF2

RFIC - San Francisco June 11-13, 2006

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New Loop Filter Topology

• MOS-HBT cascode provides:– Linearity and low-noise with

no degeneration– Lower power supply

(VGS<VBE)

• Bias at peak-gm current density

for maximum linearityLE for input 50Ω matching:

LEE for common mode rejection

oE

T

ZL = ω

VB

VB

INP INN

VCC

(2.5V)

VTUNE

FEEDBACKN

LC

CC

CVAR

LE

LE

LEE

FEEDBACKP

D

Q

Gm2

RZDAC1

RZDAC2

CLOCK

2GHz BPF 2GHz BPFDFF

DIGITAL

OUTPUT

DRIVERRF

INPUTG

m1

CLOCKTREE

Fs=40GHz

Gfb1

Gfb2

RFIC - San Francisco June 11-13, 2006

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New RZ DAC Topology

• DAC with RZ pulse for immunity against loop delay

• Higher switching speed due to MOS-HBT cascode

• High gm/ITAIL ratio (due to HBT)

DFFP

CLKP CLKN

DFFN

VGTAIL

VCC

(2.5V)

VB

DACP DACN

Q1 Q2

M1 M2

M3

ITAIL

Q3 Q4

D

Q

Gm2

RZDAC1

RZDAC2

CLOCK

2GHz BPF 2GHz BPFDFF

DIGITAL

OUTPUT

DRIVERRF

INPUTG

m1

CLOCKTREE

Fs=40GHz

Gfb1

Gfb2

RFIC - San Francisco June 11-13, 2006

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New 40-GHz Quantizer Topology

INP

CLKP

INN

VCC

(2.5V)

CLKN

VG

OUTP

OUTN

• MOS-HBT MSM flip-flop:– 3 latches to compensate for

metastability– MOS on clock path to

improve speed with low supply

– HBT on data path for high gain

Min swing at quantizer input: 10mVpp

3 stages needed for full logic swing (300mVpp) at DAC input

D

Q

Gm2

RZDAC1

RZDAC2

CLOCK

2GHz BPF 2GHz BPFDFF

DIGITAL

OUTPUT

DRIVERRF

INPUTG

m1

CLOCKTREE

Fs=40GHz

Gfb1

Gfb2

RFIC - San Francisco June 11-13, 2006

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40-GHz Bandwidth Clock Distribution

• External clock distributed to 3

latches and 2 DACs

• EF-MOS-HBT cascode for

increased bandwidth and

large capacitive load drive

D

Q

Gm2

RZDAC1

RZDAC2

CLOCK

2GHz BPF 2GHz BPFDFF

DIGITAL

OUTPUT

DRIVERRF

INPUTG

m1

CLOCKTREE

Fs=40GHz

Gfb1

Gfb2

EXTERNAL CLOCK

EF-INV EF-INV

EF-INV

EF-INV

EF-INV

EF-INV

VB V

BINP INN

VCC

(2.5V)

VG

OUTN OUTPV

CCV

CC

10.8mA 33.8mA

44.4mA 58.6mA

44.4mA 65.2mA

TO DACs(I

LOAD=60mA)

TO DFF(I

LOAD=62mA)

RFIC - San Francisco June 11-13, 2006

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Fabrication and Characterization of loop filter breakout and ADC

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ADC Die Photograph

1.52x1.58mm2

• ADC and filter breakout fabricated in

STM’s 0.13μm SiGe BiCMOS:

– HBT fT/fmax=150/160 GHz

– 2μm finger width n-MOSFET fT/fmax=80/90 GHz

• Total power dissipation 1.6W from 2.5V

D

Q

Gm2

RZDAC1

RZDAC2

CLOCK

2GHz BPF 2GHz BPFDFF

DIGITAL

OUTPUT

DRIVERRF

INPUTG

m1

115mW

62.5mW 175mW

645mW

512.5mW 94mW

RFIC - San Francisco June 11-13, 2006

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Loop Filter – Measurements

• Linearity and noise measured on a filter test structure

• Optimum bias point for maximum linearity: 0.4mA/μm

RFIC - San Francisco June 11-13, 2006

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ADC – S-parametersSingle-ended measurements

• Q=17 and BW3dB=120MHz

• ADC stable up to 65GHz

• S22<-7dB up to 65GHz and <-15dB up to 22GHz

RFIC - San Francisco June 11-13, 2006

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ADC – Spectrum Measurements

• No idle tones present in-band

• Inset shows > 35dB/dec noise shaping

Single-tone at 2-GHz ON Single-tone at 2-GHz OFF

RFIC - San Francisco June 11-13, 2006

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ADC – SNDR Measurements

• SNDR measured with

Spectrum Analyzer

• Resolution BW lowered

until noise floor

remained constant

(RBW < 50 KHz)

• Measurements taken for

bandwidths between

1 MHz and 120 MHz

RFIC - San Francisco June 11-13, 2006

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ADC – SNDR vs BW Measurements

• SNDR=55dB over 60 MHz

• SNDR=52dB over 120 MHz

RFIC - San Francisco June 11-13, 2006

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ADC – SFDR Two-Tone Measurements

• Two-tone test with

2 GHz RF inputs at

10 MHz spacing

• PIN= -30dBm

• SFDR=61dB

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ADC – 40-Gb/s Eye Diagram Jitter Measurements

• 2-GHz input sinusoid

• Feedback turned-off

• JitterRMS=375fs

• Jitter does not affect

ADC resolution

RFIC - San Francisco June 11-13, 2006

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ADC PerformanceCenter Frequency 2 GHzClock Rate 40 GHzOSR 333SNDR 55dB/60MHz

52dB/120MHzSFDR 61 dBPower Supply 2.5 VPower Dissipation 1.6 WFOM 18 pJ/bit

Ref Process Fs (GHz) Fc (GHz) BW (MHz) SNDR (dB) FOM (pJ/bit)[2] (BP) Si 3.8 0.95 0.2 49 1473[3] (BP) InP 3.2 0.8 25 41 400[4] (BP) InP 4 1 60 47.4 135[6] (LP) InP 8 - 62.5 57.4 24This work SiGe BiCMOS 40 2 60 55 26

40 2 120 52 18

Figure of Merit (FOM) definition (lower better):

2 2DC

ENOB

PFOM

BW

RFIC - San Francisco June 11-13, 2006

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Conclusion

• First mm-wave sampling ΔΣ ADC in any

technology (> 2xFs)

• Direct RF A/D Conversion at 2-GHz with 9-bit

resolution over 60 MHz

• 11 bits over 60 MHz possible in this topology with:– Improved filter linearity– Higher filter Q

• Best FOM among all ADCs with clocks > 1 GHz

• 40-48 GS/s design scalable to 3.5/5/12 GHz

RFIC - San Francisco June 11-13, 2006

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Acknowledgements

• Eric Gagnon and Morris Repeta for system

performance specifications

• Nortel Networks for funding support

• STMicroelectronics for chip fabrication

• ECTI for lab access

• CMC for CAD tools