IBM Research

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1

Reliability of advanced CMOS devices and circuits

James H. StathisIBM Thomas J. Watson Research CenterYorktown Heights, NY

IBM Research

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p substrate, doping α*NA

L/α xd/α

GATEn+ source

n+ drain

WIRINGVoltage, V / α

W/αtox/α

CMOS Scaling Rules

SCALING:Voltage: V/αOxide:Oxide: ttox ox //ααWire width: W/αGate width: L/αDiffusion: xd /αSubstrate: αNA

RESULTS:Higher Density: ~α2

Higher Speed: ~αPower/ckt: ~1/α2

Power Density:Power Density: ~Constant~Constant

R. H. Dennard et al., IEEE J. Solid State Circuits, (1974).

tox scaling requiredfor short channel control

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p substrate, doping α*NA

L/α xd/α

GATEn+ source

n+ drain

WIRINGVoltage, V / α

W/αtox/α

CMOS Scaling Rules

SCALING:Voltage: V/αOxide:Oxide: ttox ox //ααWire width: W/αGate width: L/αDiffusion: xd /αSubstrate: αNA

RESULTS:Higher Density: ~α2

Higher Speed: ~αPower/ckt: ~1/α2

Power Density:Power Density: ~Constant~Constant

R. H. Dennard et al., IEEE J. Solid State Circuits, (1974).

11Å

tox scaling requiredfor short channel control

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p substrate, doping α*NA

L/α xd/α

GATEn+ source

n+ drain

WIRINGVoltage, V / α

W/αtox/α

CMOS Scaling Rules

SCALING:Voltage: V/αOxide:Oxide: ttox ox //ααWire width: W/αGate width: L/αDiffusion: xd /αSubstrate: αNA

RESULTS:Higher Density: ~α2

Higher Speed: ~αPower/ckt: ~1/α2

Power Density:Power Density: ~Constant~Constant

R. H. Dennard et al., IEEE J. Solid State Circuits, (1974).

Approaching atomistic and quantum-mechanical boundariesAtoms are not scalable!

11Å

tox scaling requiredfor short channel control

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Device Scaling

Conventional bulk device or partially-depleted SOI (PDSOI)– Aggressive gate dielectric

scaling for improved short channel control

– Increased random doping fluctuations due to width and length scaling

– Spacer thickness decreasing• Becoming comparable to old

gate dielectric thickness (~10nm)

50-65

65-80

80-100

120-130

170-180

Device Pitch (nm)

15

22

11

32

45

Node

Extension

Si substrate

Extension

BOX

Halo

PolyGate

NiSi

Band-edgegate

NiSi

Gate Oxide

tSi

NiSiExtension

EmbeddedStressor

SOI

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CMOS Scaling: Oxide electric field increasing

Field driven wearout

increasing

4 6 8 10

100 65 nm

45 nm

350 nm

- ΔV m

ax (

mV)

Eoxide (MV/cm)

estimated NBTI at 10 years

source: IEDM and VLSI Eox = (Vgate / telectrical) = (CV/ε)

1980 1985 1990 1995 2000 20050

1

2

3

4

5

6

7

8

9

10

Fiel

d (M

V/c

m)

year published

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Major MOSFET oxide failure mechanisms

Bias/Temperature Instability – NBTI

– PBTI

Dielectric Breakdown

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Negative-bias-temperature instability

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VDD

0v VDD

pFET on-state

Negative-bias-temperature instability

Bias conditions during circuit operation of a CMOS inverter. With input at Ground, output is High and the p-MOS device (top) is under uniform negative gate bias with respect to its substrate.

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Thermal activation (~0.2eV)VDD

0v VDD

pFET on-state

Negative-bias-temperature instability

Bias conditions during circuit operation of a CMOS inverter. With input at Ground, output is High and the p-MOS device (top) is under uniform negative gate bias with respect to its substrate.

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Believed to be caused by an electrochemical reaction with a hydrogen related species in the oxide, reacting with holes in the pfet channel.First described by Miura and Matukura. Jpn. J. Appl. Phys., vol. 5, p. 180, 19661966.

Thermal activation (~0.2eV)VDD

0v VDD

pFET on-state

Negative-bias-temperature instability

Bias conditions during circuit operation of a CMOS inverter. With input at Ground, output is High and the p-MOS device (top) is under uniform negative gate bias with respect to its substrate.

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Negative-bias-temperature instability (NBTI)

Basic features:

– PFET threshold voltage shift• negative threshold voltage (Vt) shift• interface states and positive oxide charge

drive current reductioncircuit speed reduction

– Power law time dependence

– Nitrided oxide has larger shift and shallower slope• Nitridation of gate oxide makes it worse

“The Negative Bias Temperature Instability in MOS Devices: A Review”, J.H. Stathis and S. Zafar, Microelectronics Reliability, 46, 270-286 (2006).

0 4x104 8x1040.00

0.01

0.02

nitrided oxide SiO2-Δ

Vt (

V)

time (sec)

(a)

101 102 103 104 10510-4

10-3

10-2

10-1

(b)

nitrided oxide SiO2

-ΔV

t (V

)

time (sec)

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“PBTI” in high-k NFET

“PBTI” is a Vt shift observed under positive bias (i.e., in n-FET)– Not seen in SiO2/poly under normal

use conditions

– Charge trapping in high-k layer

-3 -2 -1 0 1 2 310-3

10-2

10-1

SiO2/HfO2/TiN(tHfO2= 2.2 nm)

SiON/poly-Si(tSiON= 1.3 nm)

SiON/poly-Si(tSiON= 1.3 nm)

NBTI

2.2nm

abs(Δ

V t) at 1

00 s

(V)

Vg-VT (V)

PBTI

0.0 0.5 1.0 1.5 2.0 2.5 3.00.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

Vg = 1.8 V

Vg = 2.2 V

ΔVt @

Qin

j = 1

03 C

/cm

2 (V)

HfO2 Thickness, tHfO2 (nm)

A. Kerber et al., to be published, IEEE Trans. Dev. and Mater. Reliab.

S. Pae et al., IRPS 2008.

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NBTI and PBTI in SRAM

Static noise margin analysis (butterfly curve)

VDD

PRPL

NRNL

BL BR

WL

‘0’ ‘1’

NBTI

PBTI

‘1’ ‘1’

‘1’

AXL AXRVRVL

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Effect of PBTI on SRAM

Vt increase in both nfets– SNM better than asymmetric case– Not worst-case

Vt increase in one nfet– Worst case degradation,

SNM decreases

J.C. Lin, et al., IRPS 2007.

Initial SNM

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Effect of combined NBTI & PBTI

Relative sensitivity:– SRAM cell is ~2x more

sensitive to PBTI compared to NBTI

Symmetric degradation of cells leads to little increase in failure probability – Worst case is asymmetric

PBTI degradation

0 0.5 1 1.5 2 2.50.8

1

1.2

1.4

1.6

1.8

2

2.2

WPR:WNL

( δS

NM

/ δV t,P

R):(δS

NM

/ δV t,N

L)

Typical design corner

(ΔSN

M / Δ

V t,P

BTI

) :

(ΔSN

M / Δ

V t,N

BTI

)

WPL,PR : WNL,NR

0 0.5 1 1.5 2 2.50.8

1

1.2

1.4

1.6

1.8

2

2.2

WPR:WNL

( δS

NM

/ δV t,P

R):(δS

NM

/ δV t,N

L)

Typical design corner

(ΔSN

M / Δ

V t,P

BTI

) :

(ΔSN

M / Δ

V t,N

BTI

)

WPL,PR : WNL,NR

0 20 40 60 80 1000.1

1

10

100

1,000

ΔVt,NL [mV]

# of

faul

ty c

ells

in 1

00M

B m

emor

y

ΔVt,PR=0

ΔVt,PR=50mV

ΔVt,PR=100mV

Worst case

Sym. effect

T=85oC and Vdd=0.9V

0 20 40 60 80 1000.1

1

10

100

1,000

ΔVt,NL [mV]

# of

faul

ty c

ells

in 1

00M

B m

emor

y

ΔVt,PR=0

ΔVt,PR=50mV

ΔVt,PR=100mV

Worst case

Sym. effect

0 20 40 60 80 1000.1

1

10

100

1,000

ΔVt,NL [mV]

# of

faul

ty c

ells

in 1

00M

B m

emor

y

ΔVt,PR=0

ΔVt,PR=50mV

ΔVt,PR=100mV

Worst case

Sym. effect

T=85oC and Vdd=0.9V

A. Bansal et al., IRPS 2009.

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R. Degraeve et al., TED 45, 904 (1998).

Oxide breakdown

Critical defect density

(NBD)

Defect generation leading to breakdown

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Statistical Distribution of Breakdown

Time-to-Breakdown (TBD), or Charge-to-Breakdown (QBD), is a statistically distributed quantity– Random defect generation

The Weibull Distribution is an ‘extreme value’distribution in ln(x) and is appropriate for a ‘‘weakest-link’’ type of problem.– The weakest link in a chain controls the failure of the whole

chain

– If any one spot on a dielectric breaks, the entire device is broken

– If any transistor fails, the whole circuit or chip fails

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Weibull Distribution

F is the cumulative failure probability, i.e., the population fraction failed by age x, where x can be either charge or time. The characteristic life T63 corresponds to the charge or time where 63.2% of samples fail, and β is called the slope parameter, or Weibull slope.Plotting W≡ln[-ln(1-F)] against ln(x) gives a straight line with slope β.

β

⎟⎟⎠

⎞⎜⎜⎝

⎛−

−= 631)( Tt

BD etF

E.Y. Wu et al. Semic. Sci. Technol 15, 425 (2000).

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Thickness-dependent Weibull slope

“Percolation” model

Defects generated randomly in oxide until a conducting (“percolating”) path is formed– Widely accepted, common to all physical models of defect generation

Explains thickness-dependent NBD and Weibull slope

toxa0/2

R. Degraeve et al., IEDM 1995, p. 866.

Random defect generationConnection from one electrode toward the other

J. H. Stathis, J. Appl. Phys. 86, 5757 (1999).

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“Progressive” (gradual) breakdown

Gate breakdown is not a sudden, catastrophic process.It occurs gradually, over a measurable time scale.

3.6x106 3.8x106 4.0x106 4.2x106

0.0

20.0µ

40.0µ

60.0µ

80.0µ

100.0µ PFET, -2.1 V, 1.5 nm

Def

ect C

urre

nt (A

)

Stress Time (s)

F. Monsieur et al., Microelectron. Reliab. 41, 1035 (2001).B.P. Linder et al., Electron Dev. Lett. vol 23, p. 661 (2002).T. Hosoi et al., IEDM 2002, pp. 155-158F. Monsieur et al., IRPS2002 and IRPS2003.B.P. Linder et al., IRPS 2003, p. 402.

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Weibull distribution plus progressive breakdown

PBDPBDPBDPBDBD tdtfttftf ΔΔΔ−= ∫∞

)()()(0

Convolution of breakdown time distributionandpost-breakdown growth time distribution

Curvature on Weibull plot

S. Tous et al., Elec. Dev. Lett. 2008, p. 949.

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Post-breakdown growth time distribution

E. Wu et al., IEDM 2007, p. 493.

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Progressive breakdown implications

after T. Hosoi et al., SSDM 2002 pp. 155-158

BD

BD

When does a circuit fail?When does a circuit fail?

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Transfer curves of inverters after oxide BD(experiment and model)

R. Rodríguez et al.: IRPS 2003 p. 11; EDL 24, 114 (2003); ESREF ’03.

0.0 0.4 0.8 1.20.0 0.4 0.8 1.2

0.0

0.4

0.8

1.2

measured model

negative stress

increasing-V stress

fresh

Vin (V)

~10-5×V5 A

~10-4×V5 A

~10-4×V4 A

~10-4×V3 A

~10-4×V2 A

~10-5×V5 Aincreasing+V stress

fresh

positive stress

V out (

V)

Vin (V)

See further: B. Cheek et al.: IRPS 2004 p. 110.and: H-M. Huang et al., IRPS 2004 p. 593.

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10-7 10-6 10-5 10-4 10-3 10-2 10-10.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

BD model:I=K×V5

0.13μm SRAM (1.2V) drain p-source n-source

SNM

/ SN

Mfre

sh

IBD (A) (current through BD spot for V=Vdd)

Effect of oxide breakdown on SRAM (model)

50% reduction in SNM for BD current > 50 μA

worst case: n-source BD– pulls down voltage at

opposite node– loads weaker p-FET

VL VR

R. Rodríguez et al., Electron Dev. Lett. 23, 559 (2002).

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Summary: effects of oxide wearout in circuits

Negative Bias Temperature Instability (NBTI)

Positive Bias Temperature Instability (PBTI)

Hot Carrier Injection (HCI)– All transistors in circuit may

be degraded simultaneously, or particular individuals may be more vulnerable• Depending on circuit history

Oxide Breakdown (Progressive Breakdown)– Generally, only one broken

gate in a circuit • Breakdown is a statistically

rare event

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Acknowledgements

Barry LinderErnest WuAditya BansalSufi ZafarAndreas KerberEd Cartier

– This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.