Lecture 16 ESC 201A : Introduction to
Electronics
Transistor Circuits, and Transistor Amplifiers
rhegde
Dept of EE IIT Kanpur
Show this circuit is an inverter (I/p switches
between 0 and +5V) : HW
+5 V
+ 5 V
5 KΩ
100 KΩOutput
+Vcc
Vo
Example-3
100Fβ =
we assume that transistor is in forward active mode and carry out analysis
0.7 21.5BBB
B
VI AR
µ−
= =2.15C F BI I mAβ= =
5 1.45CE C CV I R V= − × = −Since VCE < 0.2V, our assumption is incorrect and transistor is actually in saturation mode.
IC IB
+ VBE -
+ VCE -
In saturation mode: C F BI Iβ≠
The transistor model in saturation is
B
E
CICIB
0.7V 0.2V
5 0.2 1.63CI mAK−
= =
Base current is same as before:
IC IB
4.745.216.1
===A
mAII
B
Cforced µ
β
AIB µ5.21=
Example-4
100Fβ =
Find IC and VCE
Example-4
100Fβ =
Find IC and VCE
0.7 0BB B B E EV I R I R− + + + =
IE = IB + ICIE = (β +1)IB
0.7 14.29(1 )BB
BB E
VI AR R
µβ
−= =
+ +
IC = β IB
1.429C F BI I mAβ= =
( 1) 1.443E F BI I mAβ= + =
0CC C C CE E EV I R V I R− + + + =2.129CEV V=
16V
3.6kΩ
470kΩ
510Ω
+ VCE -
IC
β=120
Example-5 Find IC and VCE
16V
3.6kΩ
470kΩ
510Ω
+ VCE -
IC
β=120
IC+IB
IC+IB
IB
mAmAII
mAkk
I
IkIkI
BC
B
BBB
9.10158.0120
0158.05101214706.3121
7.0160510)121(7.04706.3)121(16
=×==
=×++×
−=
=++++−
β
BBBC IIII 121)1( =+=+ β
16V
3.6kΩ
470kΩ
510Ω
+ VCE -
IC
β=120
IC+IB
IC+IB
IB mAImAI
C
B
9.10158.0
=
=
VVVkI
CE
CEB
13.87.04700158.007.0470
=+×=
=−+
Forward Active Mode Base Emitter (BE) junction is forward biased and Base Collector (BC) junction is reverse biased
0.7BEV V≅FB
C
II
β=
Current Gain
0; 0; 0B C EI I I≅ ≅ ≅ Transistor acts like an open circuit
Cut off Mode Both the junctions are reverse biased
Saturation Mode Both the junctions are forward biased
0.7BEV V≅ 0.5BCV V≅ 0.2BE BCV V V− ≅
Let us analyze this circuit • Choose RC = 1 kΩ • Vi < Vγ
o Transistor in cut off o IB=0; IC=0 o V0=VCC
V CC 5 V
R C R B
47 k Ω V i
V 0
I B
I C
V BE +
-‐‑ V CE + -‐‑
Vo vs Vi
0
1
2
3
4
5
6
0 0.2 0.4 0.6 0.8
V o(V)
Vi (V)
Vo as Vi increases … • RC = 1 kΩ • Vi > Vγ
o KVL in the BE loop: V CC 5 V
R C R B
47 k Ω V i
V 0
I B
I C
V BE +
-‐‑ V CE + -‐‑
BEBBi VRIV +=
B
BEiB R
VVI −=
Load line?
Vi > Vγ
• KVL in the CE loop:
• As Vi increases …
CECCCC VRIV +=
V CC 5 V
R C R B
47 k Ω V i
V 0
I B
I C
V BE +
-‐‑ V CE + -‐‑
B
BEiB R
VVI −=
CCCCCE RIVVV −==0
BC II β=100=β
Vo as Vi increases …
How low can it go? V0 =VCE =VC −VE = −VBC +VBEVBC =VBE −VCEVBE = 0.7 V CC
5 V R C
R B 47 k Ω
V i
V 0
I B
I C
V BE +
-‐‑ V CE + -‐‑
VVCE 2.0≅When
VVBC 5.0=Both CB and BE juncMons are forward biased and the transistor enters into saturaMon
Add and Subtract VB
Display this on the DSO
Please Verify
βforced < βF
Vi > Vγ
• KVL in the CE loop:
• As Vi increases …..
CECCCC VRIV +=
V CC 5 V
R C R B
47 k Ω V i
V 0
I B
I C
V BE +
-‐‑ V CE + -‐‑
B
BEiB R
VVI −=
CCCCCE RIVVV −==0
BC II β=100=β
What happens if RC increases?
Slope represents gain in active region
What is the transition point if Rc=15kΩ?
V CC 5 V
R C R B
47 k Ω V i
V 0
I B
I C
V BE +
-‐‑ V CE + -‐‑
Transistor Circuit Analysis
Circuit VO+vo
VIN(dc)
vin
VIN(dc)
VOdc Circuit small signal Circuit
vin
vo
dc analysis Small signal analysis
Small Signal Model or ac Model
cb
rπ
e
+vπ-
gmvπ
T T
BQ CQ
V VrI Iπ β= =
CQm
T
Ig
V=
The small signal model is valid only when
26 300TkTv V mV at Kqπ << = =
This model is valid for both npn and pnp transistors
IB1
IB2
IB4
IB3
r0 not completely flat vπ
Complete Analysis: dc +ac
1. Dc analysis Capacitor is like an open circuit under dc
vin
v0
V0
1. Dc analysis 0.7CC
BQB
VIR−
=
CQ BQI Iβ= ×
( )O CC CQ CV dc V I R= − ×
mAIBQ 0215.0=
mAICQ 15.2=
VV 85.20 = Can you plot the load line?
β=100
V0
DC voltage sources are shorted and dc current sources are open circuited
Analysis is done at frequencies for which impedance due to capacitor is small so that capacitor can be considered as short.
Small signal Analysis
vin
v0
vin
v0 v0
b
rπ
e
+vπ-
gmvπ
cNext, the transistor is replaced by its small signal model
Small signal Analysis
vin
v0
Small signal Analysis
rπ+vπ-
gmvπb c
e
vin
vout
RB RC200K 1K
vin
v0
v0
vin
rπ+vπ-
gmvπb c
e
vin
vout
RB RC200K 1K
rπ+vπ-
e
voutbvin RB gmvπ RC
c
inv vπ =
o m Cv g v Rπ= − ×Simplify
om C
in
v g Rv=−
vin
v0
rπ+vπ-
e
voutbvin RB gmvπ RC
c
om C
in
v g Rv=−
861000086.00 −=×−=−= Cmin
Rgvv
SmVmA
VI
gT
CQm 086.0
2515.2
===
vin
v0
Common Emitter (CE) Amplifier
R1
R2 CE
VCC
RC
RE
CB
VS
VSrπ
+vπ−
RB
b
e
c
gmvπ
RC
vo
Emitter is the common terminal between input and output ports !
vin
vin
Common Emitter (CE) Amplifier
R1
R2 CE
VCC
RC
RE
CB
VS
56 kΩ
8.2 kΩ 1.5 kΩ
6.8 kΩ
22 V
βF=90
vin
dc Analysis
RC
VCC
RERB
VB
RC
RE
VCCVCC
R1
R2
Ω=+
×== k
kkkkRRRB 15.72.8562.856
21
2. Apply Thevenin’s theorem
VRR
RVV CCB 81.22.642.822
21
2 ==+
×=
1.5 kΩ
6.8 kΩ
7.15 kΩ
2.81 V
RC
VCC
RERB
VB 1.5 kΩ
6.8 kΩ
7.15 kΩ
2.81 V
kIkI EQBQ 5.17.015.781.2 ++=
)11(;F
CQEQF
CQBQ II
II
ββ+==
mAI
kIkI
CQ
CQCQ
32.1
5.19011
9015.711.2
=
⎟⎠
⎞⎜⎝
⎛ ++=
SmVmA
VI
gT
CQm 0528.0
2532.1
===
CE
RC
RE
CB
VSRB
VSRB
RC
VSRB rπ
gmvπ+vπ−
RC
vo
35968000528.00 −=×−=−== Cmin
v RgvvA
6.8 kΩ
vin
vin
vin
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