147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

Department of ECE Page 1

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

CIRCUIT DIAGRAM:

CURRENT- SERIES FEEDBACK AMPLIFIER:

Without feedback:

Without feedback:

Department of ECE Page 2

C1

0.1uF

RE

600Ω

R1

51KΩ

C2

0.1uFQ1

BC107A

12Vdc

RC

2.4KΩ

R2

9KΩ

CRO

CE

5.3uF

+

−

RL

4.7KΩ

Vin = 20mVf = 20 Hz– 20KHz

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

1. CURRENT SERIES FEEDBACK AMPLIFIER

AIM: 1. To design a Current Series feedback amplifier for the following

specifications.Vcc=12 V, Ic=2mA,VBE=0.6V, hfe=200.

2. To plot the frequency response graph for the amplifier with and without feedback.

3. To calculate the following parameters with and without feedbacka) Voltage gainb) Bandwidth

EQUIPMENTS REQUIRED:

EQUIPMENTRANGE QUANTITY

Power supply (0-30)V 1CRO (0-20)MHz 1Function generator (0-1)MHz 1

COMPONENTS REQUIRED: COMPONENT QUANTITYBJT BC107 1ResistorsCapacitors

DESIGN:

Given Specifications are Vcc=12 V, Ic=2mA,VBE=0.6V, hfe=200.

Rule of Thumb:

IC ≈ IE

re=26mV/IE

re=26×10-3/2×10-3 = 13 Ω

hie=hfe re=2.6 KΩ

Department of ECE Page 3

Q1

BC107

RC

2.4KΩ

CRO

RE

600Ω

0

C1

0.1uF

R1

51KΩ

C2

0.1uF

12Vdc

R2

9KΩ

+

−

RL

4.7KΩ

Vin = 20mVf = 20Hz – 20KHz

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

CURRENT- SERIES FEEDBACK AMPLIFIER:

With Feedback:

Department of ECE Page 4

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

To find RE:

To find RC:

To find biasing resistors R1 and R2:

Current through R2:

Applying Voltage divider rule,

MODEL GRAPH:

Department of ECE Page 5

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

F requency Response of Current Series Feedback Amplifier

Bandwidth without feedback = f3 – f2.Bandwidth with feedback = f4 – f1.

Department of ECE Page 6

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

by solving (1) & (2) we get

To find CE:

Let the smallest frequency f = 500 Hz

To find CC:

rin=hie=2.6KΩ

XCC=3.2KΩ

CC=1/ (2πfXcc)

Department of ECE Page 7

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

TABULATION:

Without Feedback:Vin =

Frequency Vo Volts Gain = Vo/Vs Gain (dB) = 20log(Vo/Vs)

With feedback:Vin =

Frequency Vo Volts Gain = Vo/Vs Gain (dB) = 20log(Vo/Vs)

Department of ECE Page 8

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

PROCEDURE:

1. Connect the circuit as per the circuit diagram2. Set Vs = 50mV, using the signal generator3. Keeping the input voltage constant, vary the frequency from 20Hz to 20

KHz in regular steps and note down the corresponding output voltage.4. Plot the graph: gain (dB) vs. frequency.5. Find the input and output impedances.6. Calculate the bandwidth from the graph.7. Note the phase angle, bandwidth, input and output impedance.8. Remove emitter resistance (RE), i.e., feedback loop, and follow the same

procedure (1 to 7).

RESULT:

Thus the Current-series feedback amplifier was designed for the given specifications and the frequency response graph was plotted for the circuit with and without feedback. The results are summarized as follows:-

Current SeriesWith Feedback

Without Feedback

BandwidthVoltage Gain

Department of ECE Page 9

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

CIRCUIT DIAGRAM:

VOLTAGE-SHUNT FEEDBACK AMPLIFIER:

Without feedback:

Department of ECE Page 10

C1

0.1uF

RE

600Ω

R1

51KΩ

C2

0.1uFQ1

BC107A

12Vdc

RC

2.4KΩ

R2

9KΩ

CRO

CE

5.3uF

+

−

RL

4.7KΩ

Vin = 20mvf = 20Hz – 20KHz

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

2. VOLTAGE SHUNT FEEDBACK AMPLIFIER

AIM: 1. To design a Voltage Shunt feedback amplifier for the following

specifications.Vcc=12 V, Ic=2mA,VBE=0.6V, hfe=200.

2. To plot the frequency response graph for the amplifier with and without feedback.

3. To calculate the following parameters with and without feedbacka. Voltage gainb. Bandwidth

EQUIPMENTS REQUIRED:

EQUIPMENT RANGE QUANTITYPower supply (0-30)V 1CRO (0-20)MHz 1Function generator (0-1)MHz 1

COMPONENTS REQUIRED:

COMPONENT RANGE QUANTITYBJT BC107 1ResistorsCapacitors

DESIGN:

Given Specifications are Vcc=12 V, Ic=2mA,VBE=0.6V, hfe=200.

Rule of Thumb:

IC ≈ IE

re=26mV/IE

re=26×10-3/2×10-3 = 13 Ω

hie=hfe re=2.6 KΩ

Department of ECE Page 11

Q1

BC107A

C1

0.1uF

CRO

R5

2.2KΩ

1C4

0.1uF

V2

R2

9KΩR4

600Ω C3

5.3uF

R151KΩ

C2

0.1uF

R32.4KΩ

12Vdc

f=20Hz-20KHz

VAMPL = 20mV

RL

4.7KΩ

9KΩ

−

+

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

VOLTAGE-SHUNT FEEDBACK AMPLIFIER:

With Feedback:

Department of ECE Page 12

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

To find RE:

To find RC:

To find biasing resistors R1 and R2:

Current through R2:

Applying Voltage divider rule,

Department of ECE Page 13

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

MODEL GRAPH:

F requency Response of Voltage-shunt Feedback Amplifier

Bandwidth without feedback = f3 – f2.Bandwidth with feedback = f4 – f1.

Department of ECE Page 14

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

by solving (1) & (2) we get

To find CE:

Let the smallest frequency f = 500 Hz

To find CC:

rin=hie=2.6KΩ

XCC=3.2KΩ

CC=1/ (2πfXcc)

TABULATION:

Department of ECE Page 15

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

With Feedback:

Vin = ------ VFrequency Vo Volts Gain = Vo/Vs Gain (dB) =

20log(Vo/Vs)

Without feedback:

Vin = …… V

Frequency Vo Volts Gain = Vo/Vs Gain (dB) = 20log(Vo/Vs)

Department of ECE Page 16

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

PROCEDURE:

1. Connect the circuit as per the circuit diagram2. Set Vs = 50mV, using the signal generator3. Keeping the input voltage constant, vary the frequency from 20Hz to 20

KHz in regular steps and note down the corresponding output voltage.4. Plot the graph: gain (dB) vs. frequency.5. Find the input and output impedances.6. Calculate the bandwidth from the graph.7. Note the phase angle, bandwidth, input and output impedance.8. Connect the feedback resistor (Rf) between the base and the collector to

form the feedback loop, and follow the same procedure (1 to 7).RESULT:

Thus the Voltage-shunt feedback amplifier was designed for the given specifications and the frequency response graph was plotted for the circuit with and without feedback. The results are summarized as follows:-

Voltage-shuntWith Feedback

Without Feedback

BandwidthVoltage Gain

SERIES AND SHUNT FEEDBACK AMPLIFIER

Sample viva questions:

1.2. What are the advantages of negative Feedback amplifier when compare

with amplifier?3. What will happen to the Bandwidth, gain, output and input resistance of

voltage series feedback amplifier because of feedback?4. Define negative feedback.5. What is the type of feedback employed in feedback amplifier? 6. Compare Oscillator and Amplifier.7. Define Desensitivity and Sensitivity factor.8. When a feedback amplifier is said to be stable?9. A common – emitter circuit without By-pass capacitor is called a negative

current feedback circuit why?10. Current series amplifier is a Transconductance amplifier: Justify?11. Voltage Shunt amplifier is a Transresistance amplifier: Justify?12. A common – collector amplifier circuit is an example of which negative

feedback circuit?

Department of ECE Page 17

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

CIRCUIT DIAGRAM:

RC PHASE SHIFT OSCILLATOR:

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147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

3. DESIGN OF RC PHASE SHIFT OSCILLATOR

AIM: 1. To design and construct a RC Phase shift oscillator for the following

specifications.Vcc = 12V, Ic = 2mA, VBE = 0.6V, hfe = 200, f = 2 KHz, C = 0.01µF

2. To plot the output sine waveform graph for the Oscillator.

EQUIPMENTS REQUIRED:

EQUIPMENT RANGE QUANTITYPower supply (0-30)V 1CRO (0-20)MHz 1

COMPONENTS REQUIRED:

COMPONENT RANGE QUANTITYBJT BC107 1ResistorsCapacitors

DESIGN:

Given Specifications are Vcc = 12V, Ic = 2mA, VBE = 0.6V, hfe = 200, f = 2 KHz, C = 0.01µF

Rule of Thumb:

IC ≈ IE

re=26mV/IE

re=26×10-3/2×10-3 = 13 Ω

hie=hfe re=2.6 KΩ

Department of ECE Page 19

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

MODEL GRAPH:

Department of ECE Page 20

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

To find RE:

To find RC:

To find biasing resistors R1 and R2:

Current through R2:

Applying Voltage divider rule,

Department of ECE Page 21

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

TABULATION:

Department of ECE Page 22

Amplitude (Volts)

Time Period T (Seconds)

Frequency f (KHz)

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

by solving (1) & (2) we get

To find CE:

Let the smallest frequency f = 500 Hz

To find CC:

rin=hie=2.6KΩ

XCC=3.2KΩ

CC=1/ (2πfXcc)

To find the feedback capacitor C:

Given f = 2 KHz, C = 0.01µF

Department of ECE Page 23

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

C = 1 / (2π f R√6) = 0.01µF

Department of ECE Page 24

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

To find R´

R´ = R- Ri

= 2.2 K Ω - (R1 || R2 || hie) = 2.2 K Ω – (7.65K Ω || 2.6K Ω)

= 2.2 K Ω – 1.94K ΩR´ = 260 Ω

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Switch on the power supply and observe the output on the CRO (Sine wave).

3. Note down the practical frequency and compare it with the theoretical

frequency.

RESULT:

Thus the RC phase shift oscillator was designed for the given frequency and the output sine waveform was plotted.

Theoretical frequency of the oscillator = 2 KHz.Practical frequency of the oscillator =

Department of ECE Page 25

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

CIRCUIT DIAGRAM:

HARTLEY OSCILLATOR:

Department of ECE Page 26

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

4. DESIGN OF HARTLEY OSCILLATOR

AIM: 1. To design and construct a Hartley oscillator for the following

specifications.Vcc = 12V, Ic = 2mA, VBE = 0.6V, hfe = 200, f = 100KHz, L1 = 1mH

2. To plot the output sine waveform graph for the Oscillator.

EQUIPMENTS REQUIRED:

EQUIPMENT RANGE QUANTITYPower supply (0-30)V 1CRO (0-20)MHz 1

COMPONENTS REQUIRED:

COMPONENT RANGE QUANTITYBJT BC107 1ResistorsCapacitors

Design :

Given Specifications are Vcc = 12V, Ic = 2mA, VBE = 0.6V, hfe = 200, f = 100KHz, L1 = 1mH

Rule of Thumb:

IC ≈ IE

re=26mV/IE

re=26×10-3/2×10-3 = 13 Ω

hie=hfe re=2.6 KΩ

Department of ECE Page 27

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

MODEL GRAPH:

Department of ECE Page 28

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

To find RE:

To find RC:

To find biasing resistors R1 and R2:

Current through R2:

Applying Voltage divider rule,

Department of ECE Page 29

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

TABULATION:

Department of ECE Page 30

Amplitude (Volts)

Time Period T (Seconds)

Frequency f (KHz)

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

by solving (1) & (2) we get

To find CE:

Let the smallest frequency f = 500 Hz

To find CC:

rin=hie=2.6KΩ

XCC=3.2KΩ

CC=1/ (2πfXcc)

To find the feedback capacitor C:

Given f = 100 KHz, L1 = 0.1 mH, L2 = 2.4mH

Department of ECE Page 31

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

Department of ECE Page 32

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

PROCEDURE:

1. Connect the circuit as per the circuit diagram.2. Switch on the power supply and observe the output on the CRO (Sine wave).3. Note down the practical frequency and compare it with the theoretical

frequency.

RESULT:

Thus the Hartley oscillator was designed for the given frequency and the output sine waveform was plotted.

Theoretical frequency of the oscillator = 100 KHz.Practical frequency of the oscillator =

Department of ECE Page 33

C20.01uF

Cc

0.1uF

12Vdc

Q1

BC107A

Cc

0.1uF

0

0

R2

9KΩ

C10.1uF

L

0.2mH

R1

51KΩ

CE

5.3uF

Rc

2.4KΩ

CRO

R4600Ω

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

CIRCUIT DIAGRAM:

COLPITTS OSCILLATOR:

Department of ECE Page 34

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

5. DESIGN OF COLPITTS OSCILLATOR

AIM: 1. To design and construct a Colpitts oscillator for the following

specifications.Vcc = 12V, Ic = 2mA, VBE = 0.6V, hfe = 200, f = 100KHz, C1 = 0.1µF

2. To plot the output sine waveform graph for the Oscillator.

EQUIPMENTS REQUIRED:

EQUIPMENT RANGE QUANTITYPower supply (0-30)V 1CRO (0-20)MHz 1

Components Required:

COMPONENT RANGE QUANTITYBJT BC107 1ResistorsCapacitors

DESIGN:

Given Specifications are Vcc = 12V, Ic = 2mA, VBE = 0.6V, hfe = 200, f = 100KHz, C1 = 0.1µF

Rule of Thumb:

IC ≈ IE

re=26mV/IE

re=26×10-3/2×10-3 = 13 Ω

Department of ECE Page 35

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

hie=hfe re=2.6 KΩ

TABULATION:

Department of ECE Page 36

Amplitude (Volts)

Time Period T (Seconds)

Frequency f (KHz)

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

To find RE:

To find RC:

To find biasing resistors R1 and R2:

Current through R2 :

Applying Voltage divider rule,

Department of ECE Page 37

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

MODEL GRAPH:

Department of ECE Page 38

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

by solving (1) & (2) we get

To find CE:

Let the smallest frequency f = 500 Hz

To find CC:

rin=hie=2.6KΩ

XCC=3.2KΩ

CC=1/ (2πfXcc)

To find the feedback capacitor C2:

Given f = 100 KHz, L = 0.2mH.Let C1 = 0.1μF.

Department of ECE Page 39

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

Department of ECE Page 40

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

PROCEDURE:

1. Connect the circuit as per the circuit diagram.2. Switch on the power supply and observe the output on the CRO (Sine wave).3. Note down the practical frequency and compare it with the theoretical

frequency.

RESULT:

Thus the Colpitts oscillator was designed for the given frequency and the output sine waveform was plotted.

Theoretical frequency of the oscillator = 100 KHz.Practical frequency of the oscillator =

OSCILLATORS

Sample Viva Questions:

1. What type of feedback is preferred in oscillators?2. How does oscillation start in oscillators?3. List out the applications of oscillators4. Which oscillator is very suitable for audio range applications?5. Which oscillator is suitable for RF range applications?6. Which oscillator is suitable for low frequency applications?7. Amplifier circuit is necessary in an oscillator, why?8. Three RC sections are used in RC Phase Shift oscillators why?9. Generally negative feedback is employed in amplifiers whereas positive feedback is employed in oscillators, why?10. For low frequency applications, we apply RC oscillators and not LC oscillators why?

Department of ECE Page 41

R1

15KΩ

C1

1uF

CRO

0.01uF

12Vdc

C3

1uFQ1

BC107

0

0.2mH

FREQ = 100KHzVAMPL = 1V

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

CIRCUIT DIAGRAM:

Department of ECE Page 42

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

6. TUNED CLASS C AMPLIFIER

AIM: To design a Tuned Class C amplifier for the following specifications.Vcc = 12V, f = 100KHz

To plot the frequency response graph for the amplifier.To calculate the following parameters with and without feedback

c) Voltage gaind) Bandwidth

EQUIPMENTS REQUIRED:

EQUIPMENT RANGE QUANTITYPower supply (0-30)V 1CRO (0-20)MHz 1Function generator (0-1)MHz 1

COMPONENTS REQUIRED:COMPONENT RANGE QUANTITYBJT BC107 1ResistorsCapacitors

PROCEDURE:

1. Connect the circuit as per the circuit diagram2. Set Vs=50mV(say), using the signal generator.3. Keeping the input voltage constant, vary the frequency from 0Hz to 1

MHz in regular steps and note down the corresponding output voltage.4. Plot the graph: Gain(dB) Vs frequency.

Department of ECE Page 43

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

MODEL GRAPH:

TABULATION:Vin =

Frequency Vo Volts Gain = Vo/Vs Gain (dB) = 20log(Vo/Vs)

Department of ECE Page 44

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

DESIGN:

The given specification is Vcc = 12V, f = 100KHz

Let us assume

The resonant frequency f ,

L = 1

4π2(1002)k20.01μ

L = 0.2mH

Department of ECE Page 45

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

Department of ECE Page 46

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

RESULT:

Thus the Tuned Class C amplifier was designed and constructed and the frequency response was plotted in the graph. The results are summarized as follows :

The theoretical resonant frequency = 100 KHz.The practical resonant frequency =The lower cut-off frequency =The upper cut-off frequency =Bandwidth of the tuned amplifier =

Sample Viva Questions:

1. What do you mean by tuned amplifier?2. Define Class C amplifier.3. Define Q factor.4. Why Q factor is kept as high as possible in tuned circuit?5. Mention the applications of Class C tuned amplifier.6. What is meant by loaded and unloaded Q of tank circuit?7. What is the need for neutralization in tuned amplifier?

Department of ECE Page 47

RB

620kΩ

Q1

BC107

RB

620kΩ

C

1.162nF

RC

4.9kΩ

10Vdc

RC

4.9kΩ C

1.162nF

Q2

BC107

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

CIRCUIT DIAGRAM:

Department of ECE Page 48

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

7. DESIGN OF ASTABLE MULTIVIBRATOR

AIM: 1. To design and construct an astable multivibrator for the following given

specifications:

2. To plot the collector voltage and base voltage waveform of the two transistors.

EQUIPMENTS REQUIRED:

EQUIPMENT RANGE QUANTITYPower supply (0-30)V 1CRO (0-20)MHz 1Function generator (0-1)MHz 1

COMPONENTS REQUIRED:

COMPONENT RANGE QUANTITYBJT BC107 1Resistors

Capacitors

DESIGN:

The given specifications are,

To find RC:-

Apply KVL to collector circuit,

To find resistance R1 and R2:-

Apply KVL to the base,

Department of ECE Page 49

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

MODEL GRAPH:

TABULATION:

Parameters Amplitude (V) Time (ms)

VB2

VC1

VB1

VC2

Department of ECE Page 50

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

IB should be greater than IB(min)

To find Capacitance C:-

Time Constant T for astable multivibrator is,

PROCEDURE:

1. Connect the circuit as per the circuit diagram.2. Switch on the power supply.3. Observe the waveform both at base and collector of Q1 and Q2.4. Plot the waveform.

RESULT:

Thus an astable multivibrator was designed and constructed for the given specifications and its output waveforms were observed.

Department of ECE Page 51

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

CIRCUIT DIAGRAM:

MONOSTABLE MULTIVIBRATOR:

8. DESIGN OF MONOSTABLE MULTIVIBRATOR

Department of ECE Page 52

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

AIM: 1. To design and construct a monostable multivibrator for the following given specifications:

2. To plot the collector voltage and base voltage waveform of the two transistors.

EQUIPMENTS REQUIRED:

EQUIPMENT RANGE QUANTITYPower supply (0-30)V 1CRO (0-20)MHz 1Function generator (0-1)MHz 1

COMPONENTS REQUIRED:

COMPONENT RANGE QUANTITYBJT BC107 1Resistors

Capacitors

DESIGN:

The given specifications are

For stable state assume transistor Q1 is OFF and Q2 is ON.

.Due to symmetry, Rc2 = Rc1 =Rc

=10µA

Select hence take IB2 = 2.5 IB2 (min)

Time Constant

Department of ECE Page 53

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

MODEL GRAPH:

TABULATION:

Parameters Amplitude (V) Time (ms)

VB2

VC1

VB1

VC2

Trigger Input

Department of ECE Page 54

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

As

When Q1 is OFF, Let us take

0 = -2R1 + 0.2R2

R1 + R2 R1 + R2

-2R1 + 0.2R2 =0 0.2R2 = 2R1

R2 = 2R1/ 0.2 Assume R1 = 10kΩ

R2 = 100kΩ Assume Commutative capacitor C1 = 100pF.

PROCEDURE:

1. Connect the circuit as per the circuit diagram.2. Switch on the power supply and observe the output waveform at the collector

of Q1 and Q2.3. Sketch the waveform.4. Trigger the monostable multivibrator with a pulse and observe the change in

waveform.5. Sketch the waveform and observe the changes before and after triggering the

input to the circuit.

RESULT:

Thus the monostable multivibrator was designed and constructed for the given specifications and its output waveforms were observed.

Department of ECE Page 55

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

CIRCUIT DIAGRAM:

BISTABLE MULTIVIBRATOR

Department of ECE Page 56

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

9. DESIGN OF BISTABLE MULTIVIBRATOR

AIM: 1. To design and construct a monostable multivibrator for the following given specifications:

3. To plot the collector voltage and base voltage waveform of the two transistors.

EQUIPMENTS REQUIRED:

EQUIPMENT RANGE QUANTITYPower supply (0-30)V 1CRO (0-20)MHz 1Function generator (0-1)MHz 1

COMPONENTS REQUIRED:

COMPONENT RANGE QUANTITYBJT BC107 1Resistors

Capacitors

DESIGN:

The given specifications are

Assume Q1 is at cut-off and Q2 is at saturation.

Q1 is at cut-off, so VB1 should be at negative potential.

Assume R1 = 10KΩ

Department of ECE Page 57

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

MODEL GRAPH:

Department of ECE Page 58

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

By symmetry RC1 = RC2= Rc

If IB2 > IB2 (min), then Q2 is in saturation.

As IB2 > IB2 (min), Q2 is in saturation.

The resolution time is 2τ, where τ = RC.

Department of ECE Page 59

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

TABULATION:

Parameters Amplitude (V) Time (ms)

VB2

VC1

VB1

VC2

Trigger Input

Department of ECE Page 60

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

PROCEDURE:

1. Connect the circuit as per the circuit diagram.2. Switch on the power supply and observe the output waveform at the collector

of Q1 and Q2.3. Sketch the waveform.4. Apply a threshold voltage VT(pulse voltage) and observe the change of states

Q1 and Q2.5. Sketch the waveform.

RESULT:

Thus the monostable multivibrator was designed and constructed for the given specifications and its output waveforms were observed.

MULTIVIBRATORS

Sample Viva Questions:

1. What is the multivibrator?2. List the applications of monostable multivibrator.3. Which mutivibrator would function as a time delay unit? Why?4. How a Schmitt trigger is different from a multivibrator?5. Mention the applications of astable multivibrator.6. Define commutating capacitor.7. What are the other names for bistable multivibrator?8. Which multivibrator would be useful for each of the following purpose?

a. time-delay unitb. memory devicec. frequency divisiond. adjustable pulse width generatore. reference clock to synchronize timings in digital systems.

Department of ECE Page 61

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

CIRCUIT DIAGRAM:

TABULATION:

DIFFERENTIATOR:

Vi = 2V pp, f = 1 KHz

Resistance R

(ohms)

Amplitude

(Volts)Time (ms)

1 K

10 K

100 K

INTEGRATOR:

Vi = 2Vpp , f = 100 KHz

Resistance R

(ohms)

Amplitude

(Volts)Time (ms)

27

10 K

100 K

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10. DESIGN OF DIFFERENTIATOR AND INTEGRATOR

AIM: 1. To design a high pass RC circuit and observe its response for the given

square waveform for T<<RC, T=RC and T>>RC.

2. To design a low pass RC circuit and observe its response for the given square waveform for T<<RC, T=RC and T>>RC.

EQUIPMENTS REQUIRED:

EQUIPMENT RANGE QUANTITYCRO (0-20)MHz 1Function generator (0-1)MHz 1

COMPONENTS REQUIRED:

COMPONENT RANGE QUANTITYResistors

Capacitors

PROCEDURE:

Time constant of the circuit RC= 0.0198 ms

1. Apply a square wave of 2v p-p amplitude as input.

2. Adjust the time period of the waveform so that T>>RC, T=RC,T<<RC and

observe the output in each case.

3.Draw the input and output wave forms for different cases.

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MODEL GRAPH:

LOW PASS RC CIRCUIT:

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HIGH PASS RC CIRCUIT:

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RESULT:

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147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

Thus the integrator and differentiator circuits are designed and their output response for various time constants are obtained

CIRCUIT DIAGRAM:

CLIPPERS:

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11. CLIPPERS AND CLAMPERS

AIM: To obtain the output response for various non linear wave shaping circuits

– Clippers and Clampers.

EQUIPMENTS REQUIRED:

EQUIPMENT RANGE QUANTITYPower supply (0-30)V 1CRO (0-20)MHz 1Function generator (0-1)MHz 1

COMPONENTS REQUIRED:

COMPONENT RANGE QUANTITYDIODE IN4001 1Resistors

Capacitors

THEORY:

CLIPPERS:The basic action of a clipper circuit is to remove certain portions of the

waveform, above or below certain levels as per the requirements. Thus the circuits which are used to clip off unwanted portion of the waveform, without distorting the remaining part of the waveform are called clipper circuits or Clippers. The half wave rectifier is the best and simplest type of clipper circuit which clips off the positive/negative portion of the input signal. The clipper circuits are also called limiters or slicers.

CLAMPERS:The clamping network is one that will clamp an input signal to a different DC

level. The network consists of a capacitor, a diode and a resistance, but it can also have an independent DC supply to introduce an additional DC shift.

The magnitude of R and C must be chosen such that the time constant, τ = RC, is large enough to ensure that the voltage across the capacitor does not discharge significantly during the interval when the diode is non-conducting.

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CLAMPERS:

Negative peak clamped at positive reference level:

Positive peak clamped at negative reference level:

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DESIGN:

CLAMPER : For proper clamping, τ >100T

where T is the time period of input waveformIf frequency is 1 kHz with peak-peak input voltage of 10V, T=1ms

τ = RL.C=100×T = 100ms Let C=1μf

RL= 100KΩ Select C =1μF and RL =100 kΩ

THEORETICAL CALCULATIONS:

Positive peak clipper: Vr=2v, Vγ=0.6v When the diode is forward biased Vo =Vr+ Vγ =2v+0.6v = 2.6v When the diode is reverse biased the Vo=Vi

Positive base clipper: Vr=2v, Vγ=0.6v When the diode is forward biased Vo=Vr –Vγ = 2v-0.6v = 1.4v When the diode is reverse biased Vo=Vi . Negative base clipper: Vr=2v, Vγ=0.6vWhen the diode is forward biased Vo = -Vr+ Vγ = -2v+0.6v = -1.4v When the diode is reverse biased Vo=Vi . Negative peak clipper: Vr=2v, Vγ=0.6v When the diode is forward biased Vo= -(Vr+ Vγ) = -(2+0.6)v =-2.6v When the diode is reverse biased Vo=Vi .

PROCEDURE: 1. Connect the circuit as per circuit diagram shown in Fig.1 2. Obtain a sine wave of constant amplitude 8 V p-p from function generator and apply as input to the circuit. 3.Observe the output waveform and note down the amplitude at which clipping occurs 4. Draw the observed output waveforms.

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MODEL GRAPH:

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Negative peak clamped at positive reference level:

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Positive peak clamped at negative reference level:

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RESULT:

Thus the performance of various clipping and clamping circuits were observed.

CIRCUIT DIAGRAM:

CMOS INVERTER:

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0

M 2

M b re a k N

V

V 2TD = 0

TF = 0P W = 0 . 5 m sP E R = 1 m s

V 1 = 5 V

TR = 0

V 2 = 0 V

V 1

0 V d c

0

0

M 1

M b re a k P

CMOS NAND gate:

15. SIMULATION OF CMOS INVERTER, NAND AND NOR GATES

AIM:

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0

M 5

M b re a k N

0

V 3TD = 0

TF = 0P W = 0 . 5 m sP E R = 1 m s

V 1 = 5 V

TR = 0

V 2 = 0 V

M 4

M b re a k P

M 6

M b re a k N

0

0

V 1TD = 0

TF = 0P W = 0 . 5 m sP E R = 1 m s

V 1 = 5 V

TR = 0

V 2 = 0

V 25 V d c

V

M 3

M b re a k P

147451 Electronic Circuits II & Simulation Lab II Yr / IV sem

To simulate the CMOS inverter, NAND and NOR circuits.

SOFTWARE REQUIRED:

PSPICE Orcad family release 9.2.

PROCEDURE:1. Go to start Orcad capture New project.2. Create a blank project, then draw the circuit by taking appropriate

components and simulate the diagram.3. Observe the output waveforms.4. Ebipolar – BC107A

Breakout – mbreakP,mbreakNSource – Vdc,Vpulse,VSRC,Vsin

Analog P – r,c,L

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CMOS NOR gate:

V 2

TD = 0

TF = 0P W = 0 . 5 m sP E R = 1 m s

V 1 = 0 v

TR = 0

V 2 = 0

V 45 v d c

V 3

TD = 0

TF = 0P W = 0 . 5 m sP E R = 1 m s

V 1 = 5 v

TR = 0

V 2 = 0

0

M 2

M b re a k N

0

M 1

M b re a k N

0

V

M 5

M b re a k P

0

V

M 3

M b re a k P

V

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RESULT:

Thus the CMOS inverter, NAND and NOR circuits were simulated and output waveforms are

CMOS inverter

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CMOS NAND

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CMOS NOR GATE

CIRCUIT DIAGRAM:

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16. SIMULATION OF DIFFERENTIAL AMPLIFIER

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AIM:To simulate the differential amplifier circuit and obtain the output waveform

using PSPICE.

SOFTWARE REQUIRED:

PSPICE Orcad family release 9.2.

PROCEDURE:1. Go to start Orcad capture New project.2. Create a blank project, then draw the circuit by taking appropriate

components and simulate the diagram.3. Observe the output waveforms.

RESULT:Thus the simulation of differential amplifier was done using PSPICE.

CIRCUIT DIAGRAM:

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U 2

u A 7 4 1

3

2

74

6

1

5+

-

V+

V-

O U T

O S 1

O S 2V

V 2

A C = 0TR A N = 0

D C = 0 v

v 5

1 5 v

R 3

1 k

0

R 1

4 k

v 3

A C = 0TR A N = 0

D C = 5 v

0

0

V

V 1

A C = 0TR A N = 0

D C = 0 v

0

V 4

1 5 v

R 4

1 k

V

0

R 2

2 k

V

0

TABULATION : b 0 b1 b2 Theoritical

ValuePractical Value

Digital to analog

17. SIMULATION OF DIGITAL TO ANALOG CONVERTER

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AIM:To simulate the digital to analog converter using PSPICE.

SOFTWARE REQUIRED:

PSPICE Orcad family release 9.2.

THEORY:Binary weighed resistor DAC makes use of a summing amplifier using op-

amp. When there are n-bits in the digital codes there is a requirement of n number of binary weighed resistors from R to R / 2n-1.

V0 = -Rf [ bo/ Ro + b1/R1 + b2/R2]

PROCEDURE:1. Go to start Orcad capture New project.2. Create a blank project, then draw the circuit by taking appropriate

components and simulate the diagram.3. Observe the output waveforms.

RESULT:Thus the simulation of digital to analog converter was done using PSPICE.

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CIRCUIT DIAGRAM:

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18. DESIGN AND SIMULATION OF II ORDER LOW-PASS BUTTERWORTH FILTER

AIM:

1. To design a second order Butterworth low-pass filter for the following given specifications

2. Use PSPICE to plot the frequency response of the output voltage of the filter designed from 10Hz to 10 KHz.

SOFTWARE REQUIRED:

PSPICE Orcad family release 9.2.

DESIGN:

A second order filter exhibits a stop band roll off of -40 dB/decade. The general form the second-order low-pass filter is given by

where K is the dc gain.

The Butterworth response requires that The transfer function of

the sallen-key circuit gives to achieve a Butterworth response with sallen key topology. Therefore we must reduce the gain by 1/K.

Given specifications are

Let us consider the design of the II order LPF from that we can design the Butterworth II order LPF.

II ORDER LOW-PASS FILTER DESIGN:

The cut-off frequency fo is given by,

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Therefore,

Choose C less than or equal to 1μF.

Let C = 0.01μF

Gain of the amplifier is,

II ORDER BUTTERWORTH LOW-PASS FILTER DESIGN:

The transfer function of sallen key circuit gives

The transfer function of Butterworth filter gives

To achieve the Butterworth response, reduce gain by 1/K. The gain reduction can be achieved by adding a voltage-divider network consisting of Ra and Rb.

The values of Ra and Rb must be such that Rin = R2 and the voltage across Rb is Vi/K. i.e.

Voltage across Rb,

Solving these two equations for Ra and Rb

Here K=4,

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Butter worth low pass

PROCEDURE:

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1. Go to start → all → programs → capture.2. Select file in the menu bar → new project.3. Choose location C: programfiles/orcad/……4. Create a blank project.5. Draw the circuit diagram in the schematic editor.6. Create new simulation profile from Pspice menu.7. In simulation settings select ac sweep and logarithmic scale. Choose the

frequency range from 10Hz to 10 KHz.8. Save the project and click run and observe the output waveform.

RESULT: Thus the Butterworth low pass filter of second order was designed and

simulated using PSPICE.

CIRCUIT DIAGRAM:

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19. DESIGN AND SIMULATION OF II ORDER HIGH-PASS BUTTERWORTH FILTER

AIM:

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1. To design a second order Butterworth low-pass filter for the following given specifications

|H(jω) |= 1, fo = 1 KHz, Q = 0.707, Vcc = 15V.2. Use PSPICE to plot the frequency response of the output voltage of the

filter designed from 10Hz to 10 KHz.

SOFTWARE REQUIRED:

PSPICE Orcad family release 9.2.

DESIGN:II ORDER BUTTERWORTH HIGH-PASS FILTER DESIGN:

The transfer function of sallen key circuit gives

The transfer function of Butterworth filter gives

To achieve the Butterworth response, reduce gain by 1/K. The gain reduction can be achieved by adding a voltage-divider network consisting of Ca and Cb.

The values of Ca and Cb must be such that Cin = C2 and the voltage across Cb is Vi/K. i.e.

Ca + Cb = C2

Then, Ca / (Ca +Cb) = 1/K

Ca = C2/K

C2 = 0.01 × 10-6 / 1.586 = 6.305 nF.

Cb = C2 – 6.305nF = 3.965 nF.

PROCEDURE:

1. Draw the circuit diagram in the schematic editor.

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2. Create new simulation profile from Pspice menu.3. In simulation settings select ac sweep and logarithmic scale. Choose the

frequency range from 10Hz to 10 KHz.4. Save the project and click run and observe the output waveform.

RESULT: Thus the butterworth high pass filter of second order was designed and

simulated using PSPICE.

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VIVA QUESTIONS:

1. What is difference between linear and non-linear wave shaping circuits.

2. What is meant by lower 3-db frequency of high-pass circuit?

3. What is meant by fractional tilt?

4. Why response of amplifier does not remain flat at all frequencies.

5. Explain condition of RC circuit to work as differentiation.

6. Why RC circuits are preferred over RL circuits for large time constant

applications.

7. What do you mean by a linear network?

8. What do you mean by Linear Wave Shaping?

9. For a long time constant RC high pass circuit with a symmetrical square wave

input, find the tilt.

10. Integrators are preferred over the differentiators. Why?

11. Why RC circuits are commonly used as compared to RL circuits?

12. Why does comparator differ from clipper?

13. What is drawback of having diode as series element in clipper?

14. What is drawback of having diode as shunt element in clipper?

15. What is the difference between regenerative and non-regenerative comparator.

16. What is difference between output from clipping and clamping circuit?

17. Define an ideal differential amplifier.

18. Define common-mode rejection ratio.

CIRCUIT DIAGRAM

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R 61 0 K

R 29 1 . 6 7 K

0

0

C 11 0 0 P F

0

Q 2

B C 1 0 7 A

0

0

R 3

1 0 K

V 2

TD = 0

TF = 0P W = 0 . 5 M SP E R = 1 m s

V 1 = 1 2 V

TR = 0

V 2 = -1 2 v

V

C 2

1 0 0 P F

V

V 1

TD = 0

TF = 0P W = 0 . 5 M SP E R = 1 m s

V 1 = 1 2 V

TR = 0

V 2 = -1 2 v

R 45 . 9 K

V

R 19 1 . 6 7 K

V

V 31 2 V D C

Q 1

B C 1 0 7 A

R 55 . 9 K

20. SIMULATION OF BISTABLE MULTIVIBRATOR

AIM:

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To simulate the bistable multivibrator circuit and obtain the output waveform using PSPICE.

SOFTWARE REQUIRED:

PSPICE Orcad family release 9.2.

PROCEDURE:1. Go to start Orcad capture New project.2. Create a blank project, then draw the circuit by taking appropriate

components and simulate the diagram.3. Observe the output waveforms.

RESULT: Thus the bistable multivibrator was designed and simulated using PSPICE.

CIRCUIT DIAGRAM:

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21.SIMULATION OF ASTABLE MULTIVIBRATOR

AIM:

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To simulate the astable multivibrator circuit and obtain the output waveform using PSPICE.

SOFTWARE REQUIRED:

PSPICE Orcad family release 9.2.

PROCEDURE:1. Go to start Orcad capture New project.2. Create a blank project, then draw the circuit by taking appropriate

components and simulate the diagram.3. Observe the output waveforms.

MODEL GRAPH:

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RESULT: Thus the astable multivibrator was designed and simulated using PSPICE.

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CIRCUIT DIAGRAM

22. SIMULATION OF MONOSTABLE MULTIVIBRATOR

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AIM:To simulate the monostable multivibrator circuit and obtain the output

waveform using PSPICE.

SOFTWARE REQUIRED:

PSPICE Orcad family release 9.2.

PROCEDURE:1. Go to start Orcad capture New project.2. Create a blank project, then draw the circuit by taking appropriate

components and simulate the diagram.3. Observe the output waveforms.

MODEL GRAPH:

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RESULT: Thus the monostable multivibrator was designed and simulated using PSPICE.

SPECIFICATIONS:

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BC 107 – NPN GENERAL PURPOSE TRANSISTOR

FEATURES:- Low Current (max. 100mA)- Low Voltage (max. 45 V)

For IC = 2mA, VCE = 5V

hfe(min) = 110hfe(max) = 450Vbe(min) = 550mVVbe(typ) = 620mVVbe(max) = 700mV

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