A 2-GHz Direct Sampling ΔΣ Tunable Receiver with 40-GHz

Sampling Clock and on-chip PLL

T. Chalvatzis1, T. O. Dickson1,2 and S. P. Voinigescu1

1 University of Toronto, Toronto, CA2 now with IBM T.J. Watson Research Center, NY, USA

Outline of Presentation

• Motivation

• Circuit design– Loop filter– PLL

• Measurement results

• Summary

Motivation

• Direct sampling receiver for 2-GHz radio with 60 MHz BW– CT BP ΔΣ ADC with SNDR of 55dB/60MHz

[Chalvatzis et al., JSSC, May 2007]– Investigation of clock jitter impact with on-chip

clock source

LNA

Duplexer/BPF

TO DSP

Digital Receiver

ADC

CLOCK

System Architecture

• 2-GHz Gm-LC BPF• Fourth order loop• 1-bit quantizer as DFF

with FCLK=40GHz

• RZ pulse DACs• 40-GHz VCO/PLL

QDGm2

RZDAC1

RZDAC2

40-GHzEXTERNAL

CLOCK

2GHz BPF 2GHz BPF DFFDIGITAL

OUTPUT

DRIVERRF

INPUTGm1

CLOCKTREE

40-GHz VCO

G fb1 G fb2

LNA

PFD CP

DIV/16

SEL

CLOCKSELECT

2.5-GHzREF

System Level Design

• Design methodology in continuous-time

• System level simulation for accurate analysis of loop delay

• Loop coefficients:– Gm1=22mS, Gm2=15mS– Gfb1=50mS, Gfb2=150mS

SNDR=61dB over 60 MHz in Matlab Simulink

SNR vs clock jitter

• Clock jitter effect simulated for FS=40GHz, OSR=333

• PLL jitter < 1.4 ps (rms) for 10 bits resolution

Δ: quantizer step

[Ortmanns et al.,

ISCAS 2003]

2IN

2 2DAC t

V 2OSRSNR=

2 F σ

SNR vs resonator Q

• Quantization noise integrated over BW for FS=40GHz

• Q >18 for 10 bits resolution

2IN

2 / 2

/ 2

VSNR=

( )6

O

O

F BW

F BWS

NTF jf dfF

VB VB

INP INN

VTUNE

LCCC

CVAR

LE LE

LEE,1

VB VB

VCC (2.5V)

VTUNE OUTNOUTP

LCCC

CVAR

M 1 M 2

Q1 Q2

M 3 M 4

Q3 Q4

LNA/Gm1 Gm2

BPF BPF

VGTAIL

Q5

M 7M 6M 5

Loop Filter

• MOS-HBT cascode for high linearity and low noise• EF limit voltage headroom, current source adds noise

Loop filter with EF

Modified Loop Filter

• MOS-HBT cascode for high linearity and low noise• EF limit voltage headroom, current source adds noise

VB VB

INP INN

VTUNE

LCCC

CVAR

LE LE

LEE,1

VB VB

VCC (2.5V)

VTUNE OUTNOUTP

LCCC

CVAR

VG

M 1 M 2

Q1 Q2

M 3 M 4

Q3 Q4

CB

RGLEE,2 RG

LNA/Gm1 Gm2

BPF BPF

CB

Modified Loop Filter

D/A Converter – Quantizer

• DAC and quantizer with MOS-HBT cascodes [Chalvatzis et al., JSSC, May 2007]

• MOS on clock path to improve speed with low supply• HBT on data path for high gain

DAC Latch

DFFP

CLKP CLKN

DFFN

VGTAIL

VCC

(2.5V)

VB

DACP DACN

Q1 Q2

M1 M2

M3

ITAIL

Q3 Q4INP

CLKP

INN

VCC

(2.5V)

CLKN

VG

OUTP

OUTN

Digital Receiver – PLL Blocks

• 40-GHz PLL design from 2.5V challenging• Combination of MOS-HBT transistors in PLL blocks

P h a se F req u en cy D etecto r

D Q

D Q

R E F

D IV

'1 '

'1 '

R E S E T

U P

D O W N

C h a rg eP u m p

T o L o o pF ilter

C L K

V B IA S

D

R L

Q 2Q 1 Q 4Q 3

M 2M 1

V C C (2 .5 V )

R E S E T

Q

Q 6Q 5 Q 7

M 4M 3

R L R L R L

Resettable Latch

Digital Receiver – PLL Blocks

• 40-GHz PLL design from 2.5V challenging• Combination of MOS-HBT transistors in PLL blocks

P h a se F req u en cy D etecto r

D Q

D Q

R E F

D IV

'1 '

'1 '

R E S E T

U P

D O W N

C h a rg eP u m p

T o L o o pF ilter

U P

V C C (2 .5V )

D O W N

IR E FV T U N E

C M F B

Charge Pump

VCO

• Colpitts VCO topology with HBT [Dickson et al., CSICS 2006]

• VCO biased for minimum phase noise

• Differential tuning with accumulation mode MOS varactors

VTUNEP

C1

C1

LB

LB

CVARN

CVARN

CVARP

VTUNEN

CVARP

LEE

LEER

CMC

CM

VBIAS

Q2Q1

CN

CN

LPL

P

VCC

(2.5V)

Fabrication and characterization of digital receiver

Fabrication

• ADC with on chip VCO/PLL in STM 0.13μm SiGe BiCMOS

• Power dissipation 2.19W from 2.5V

• Chip size 1.59x2.39mm2

ADC

PLL SEL

RFIN

DIGITALOUT

PLLREF

• Phase noise/jitter measured on PLL test structure• RMS jitter: σt=849fs• Jitter limited SNR for Fo=2GHz and OSR=333 ->

SNR=66.7dB

PLL measurements

• Phase noise < -103dBc/Hz at 1 MHz offset from 40-GHz carrier

VCO measurements

Spectrum measurement with PLL

• ADC tested with external and on-chip clock

• No significant degradation from on-chip clock

• Feedthrough from 2.5GHz PLL reference does not degrade performance

SFDR measurement

SFDR=59dB

SNDR measurement

SNDR measured for FIN=2GHz, FS=40GHzSNDR = 59.8dB over 60 MHz

Dynamic Range

ADC noise floor the same (-65dBm/60MHz) when external and on-chip clock employed

Digital Receiver Performance

Fo 2GHz

Fs 40GHz

BW 60MHz

SNDR 59.8dB

ENOB 9.65bits

SFDR 59dB

P1dB -2.8dBm

DR 58.5dB

Power 2.19W

FoM65.5GHz/W

15.3pJ/bit

ENOB

DC

2 ×2BWFoM=

P

Conclusion

• First mm-wave sampling ΔΣ digital receiver in any semiconductor technology

• Digital receiver achieves 9.65-bit resolution over 60 MHz

• Removing EF pair in filter helps to increase linearity of ADC loop filter

• For 10-bits resolution, jitter from on-chip VCO/PLL not limiting performance

• Noise floor set by resonator Q

Acknowledgements

• Nortel Networks for funding support• John Ilowski and Eric Gagnon for

discussions• STMicroelectronics for chip fabrication• Prof Miles Copeland for advice on the

manuscript• Ricardo Aroca for help with testing• CMC for CAD tools• Jaro Pristrupa for CAD support