Wavelets @ CPU

David Barina

April 15, 2014

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Wavelet

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Discrete Wavelet Transform

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Lifting

α

β

γ

δ

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2-D DWT

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2-D Separability

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What have I done?

loop fusion

removed prologs/epilogs

influence of CPU cache

SIMD-vectorization

parallelization

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Loop Fusion

read

write

F

F

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Removed Prologs and Epilogs

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Influence of CPU Cache

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SIMD Vectorization

4 × 4 6 × 2

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Image Processing and Buffers

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Parallelization

prolog

overlay

overlay

segment

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Results

Intel Core2 Quad @ 2.00 GHz

10 Mpx

CDF 9/7, 1 level, in-place

approach best algorithm time/px speed-up

separable diag. 17.23 ns 1.0×single-loop diag. 2 × 2 9.55 ns 1.8×core diag. 2 × 2 8.79 ns 2.0×super-core vert. 4 × 4 5.33 ns 3.2×parallel (4) vert. 4 × 4 1.55 ns 11.1×

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Future Work

merge several levels

merge forward and inverse cores

another wavelets

combine with EAW

another platforms (ARM, GPU, FPGA)

another transforms

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Example (AMD Opteron)

1.0ns

10.0ns

100.0ns

1.0k 10.0k 100.0k 1.0M 10.0M 100.0M

tim

e /

pix

el

pixels

naive verticalnaive diagonal

single-loop verticalsingle-loop diagonal

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