6

Vol. 5 No.7/ Jul. 2011

A 12-bit Fully Differential SAR ADC with Dynamic Latch Comparator for Portable Physiological Monitoring

ApplicationsLi Yu, Jin-yong Zhang, Lei Wang, Jian-guo Lu

ABSTRACT A 12-bit low-power Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is presented using dynamic latch comparator to realize power consumption of 47.86μW under 1.8V supply voltage. Fully differential structure and hybrid 9-bit charge-redistribution capacitive and 3-bit resistor string DAC techniques are adopted to achieve balance between high precision and small area. Fabricated in SMIC 0.18-µm 1P6M mixed-signal CMOS technology, the ADC only occupies 0.39mm2 active area and the DNL/INL achieve 0.6LSB and 0.8LSB respectively.

1 Introduction

Today, there is a growing demand for low-power, small-size, and ambulatory physiological signals

acquisition system. A crucial and power consuming building block of the physiological signals acquisition system is the Analog Front-End (AFE), which defines the quality of the extracted signals. Meantime, the realization of a portable device for physiological signal recording is important for monitoring human or nonhuman subjects without restricting their mobility [1]–

[3]. In portable applications, there is a constant demand for reduced device size and weight without impacting recording quality. A feasible solution is to integrate most of the AFE circuitry onto an IC and perform telemetry on the physiological signal to a remote computer. And due to the recording electrodes might pick up many others unneeded interferences or artifact signals as well as the physiological electronics is too weak to detect, therefore, we need a amplifier and a low pass filter to reduce the common mode noise, amplify the physiological signal and realize different low cut-off frequencies for different physiological signals. Then, the signal is passed through ADC to become a digital signal. After that, these digital data will be processed in PCs or microprocessors. Thus, low frequency, low noise and low power are three critical characteristics of AFE for portable physiological monitoring application and a total fully differential AFE is shown in Fig. 1 in order to realize better immunity to common-mode noise and interferences.

Fig. 1. Fully differential AFE architecture

ADC is the key to mixed signal SOCs in that it provides the interface between the physical world and digital processing. Speed, resolution, and power consumption are three critical parameters for an ADC. Analyzing and processing digital signals are dependent on specific demands. However, the ADC operates continuously. Therefore, the power consumption is a very important factor in the ADC circuit design. It is known that the successive approximation register ADC (SAR ADC) architecture is well suitable for large-scale wireless sensor networks and physiological applications due to its moderate speed, moderate resolution and very low-power consumption characteristics. The primary sources of power consumption in a SAR ADC are the comparator and charge/discharge of the capacitor array [4]-[5]. As most physiological signals have low frequency, small amplitude characteristics (e.g. EEG<150Hz、25~300µV and ECG<250Hz、0.5~4mV), dynamic latch comparator and fully-differential structure are used to lower the power consumption as well as input noise respectively. And in order to achieve optimization in high precision and small area, a hybrid 9-bit charge-redistribution capacitive and 3-bit resistor string DAC is implemented in the chip. Recently, there has been a few reported SAR ADC implementations [4]–[7], however, some of them do not adopt hybrid DAC structure or even fully differential structure, and the others use operational amplifier-based comparator.

This paper proposes a fully differential SAR ADC with dynamic latch comparator and the details about circuit design are organized as followings: the architecture and the design are discussed in Section 2 and the simulation results are summarized in Section 3. Finally, summary of this design is offer in Section 4.

2 Architecture and Design

7

A 12-bit Fully Differential SAR ADC with Dynamic Latch Comparator for Portable Physiological Monitoring Applications

The ADC architecture of the fully differential successive approximation ADC which was proposed

consists of two hybrid capacitor and resistor arrays, a gated comparator with offset cancellation, a successive approximation register (SAR) and control logic. Various possible structures to realize the track and hold function exist. In this solution the capacitor array is used as a track and hold stage and as a DAC (Main DAC) to perform the successive approximation. To increase the resolution and to avoid a large capacitor array another DAC (Sub DAC) is used which interpolates the least significant bit of the capacitive Main DAC and is implemented by resistor array.

Fig. 2. The ADC architecture

Fig. 2 shows the block diagram of a 12 bit converter which comprises a 9 bit capacitive Main DAC and a 3 bit resistive Sub DAC. Fully differential operation reduces charge injection errors, is less susceptible to common-mode noise and provides a large output voltage swing – an appealing feature for low-voltage physiological applications.

Fig. 3.Timing of SAR ADC

The whole conversion is divided into three parts, as shown in Fig. 3. The first part is the discharge phase, which is placed before tracking phase. In the discharge phase the capacitors of the two arrays (two Main DACs) are discharged by the switches S3 to have a well defined starting point for the tracking phase. The second part is tracking phase, during tracking phase the offset cancellation is performed by closing the sample switch S1 as well as the input switches S2. The last

part is successive approximation phase in which the ADC conversion is realized. In tracking phase, the common-mode voltage (VCM), which is derived from the reference voltage as (VDD+VSS)/2, is applied to the comparator .stage. This means that the operating point of the comparator stage is the same during the offset cancellation as it is at all critical decisions during the successive approximation. This enables a wide variation of the common mode input voltage [4].

A. Hybrid DACIn deep submicron technologies SAR ADC have become a popular approach to implement ADCs due to reduced analog content which is always difficult to design under low VDD conditions. Charge-redistribution capacitive arrays are the preferred choice for the DAC used in the successive approximation ADCs. However for each additional bit the number of capacitors rise exponentially which limits the maximum resolution of the ADC usually to around 8-10 bits due to large capacitor ratios and small area to perimeter ratio of the unit capacitor. To avoid these problems a resistor string DAC can be used which provides small area and high speed operation compared to charge-redistribution capacitive DAC [8]. However, due to switch resistance between resistor strings causing large differential nonlinearity (DNL) errors and hardly achieving good integral nonlinearity (INL) which limits their resolution to usually less than 10 bits [9].

Fig. 4. Schematic and working princple of hybrid DAC

The linearity of the SAR ADC is dependent upon the capacitor matching in the capacitor array. Each capacitor in the capacitor array (Main DAC) consists of numbers of unit capacitors. A unit capacitance of 100fF metal-insulator-metal capacitor (MIMCAP of 12.8μm× 8μm) is chosen to guarantee the 12-bit linearity requirement. A layout floor plan of the capacitor array is depicted in Fig. 5. In order to improve linearity and tolerate process gradients, common-centroid layout technique is utilized. A dummy capacitor ring is also used on the edges of the capacitor array to ensure that all unit capacitors in the capacitor array have the same structure around them.

Meanwhile, in order to avoid large capacitor on chip, which is area consuming, a resistor string type Sub DAC

8

Vol. 5 No.7/ Jul. 2011

is used for reducing the number and value of capacitors, achieving optimization in high precision and small area.

B. Dynamic Latch ComparatorThe comparators are the key components in ADC, as they build the link between analog and digital domains. The latch type comparators offer high speed, very low static power consumption and more flexibility of power management, which makes them more attractive for the design over their counterpart. In a dynamic latch type comparator, a clock is used to set the comparator in active mode or stand-by mode. In active mode, the P logic and N logic are connected. The comparator samples the input and compares two differential input voltages, but the output is not available to the circuit. Once a decision is required from the comparator, the clock changes it to stand-by mode by disconnecting the P logic and N logic. At this point, the output stays at a state that reflects the last decision of the input stage. This type of comparator will not be sensitive to noise once it has made the decision, because the input has been effectively disconnected from the output by the latch signal.

Fig. 6. Dynamic latch comparator core circuit

Fig. 6 shows dynamic latch comparator core circuit. When φ1 is high (φ2 is low), the proposed comparator works in active mode and store the conversion result in latch, Then φ2 is changed from low to high (φ1 turns from high to low), stand-by mode is performed. For power issue, the proposed comparator is operated only for the moments when it compares the values. The comparator is necessary at every clock cycle, but there is no need to compare the voltage for the whole conversion

time. Therefore, the comparator has dynamic operation.

C. Successive Approximation RegisterThe most common successive approximation operation strategy is as follows: A flip-flop FF1 is set at clock time t0. It contributes its particular weight to a summing bus, which is one input term to a comparator amplifier. The other is the analog signal to be converted. The output of the comparator amplifier becomes the control bus which determines whether the FF1 shall remain set or whether it shall be reset at t1. At t1 the next most significant flip-flop FF2 is set and the same simple procedure is repeated. Any FF is operable for only two clock pulses per conversion cycle [10].

Fig. 7.Schematic of SAR Logic

D. Digital Control LogicThe purpose of using digital control logic is to generate three different ADC timing signals as well as two clocks that differential SAR ADC needs, moreover, by implementing in digital method, clocks can be adjusted easily and precisely.

Fig. 8. Layout of digital control logic

3 Simulation Results

The proposed SAR ADC with band pass filter is realized in the SMIC 0.18-µm 1P6M mixed-signal

CMOS technology. Cadence spectre simulator is used for simulation.

It can be seen from the comparator output that the minimum voltage precision is 5µV and the latency is less than 10nS with a 1µA biasing current. As a 12 bit ADC with a supply voltage of 1.8V, Least Significant Bit (LSB) voltage is approximately 1.8/212-1 = 0.44mV, 5µV precision of comparator can meet the requirement. The DNL and INL of the proposed SAR ADC are shown in

Fig. 5.Layout of SAR ADC

9

A 12-bit Fully Differential SAR ADC with Dynamic Latch Comparator for Portable Physiological Monitoring Applications

Fig. 10 and have range of 0.4/-0.2LSB and 0.4/-0.4LSB, respectively.

Fig. 10. Simulation result of DNL/INL of SAR ADC

The total power dissipation of the ADC is 47.86μW at 100KS/s sampling rate and supply voltage of 1.8V. The typical figure of merit (FOM) definition of the ADCs is defined as:

The FOM of this work corresponds to 0.66pJ/ step .

4 Conclusion

A 12-bit fully differential SAR ADC with dynamic latch comparator is realized in a SMIC 0.18-µm 1P6M

mixed-signal CMOS technology. Since no consistent DC current, the dynamic latch comparator offers high speed, very low static power consumption and more flexibility of power management. The feature of low power dissipation, low input signal noise and distortion as well as moderate resolution and area makes it well-suited for portable physiological monitoring application.

References[1] K. A. Ng and P. K. Chan, “A CMOS Analog Front-End IC for

Portable EEG/ECG Monitoring Applications,” IEEE Trans. Circuit and Systems, vol. 52, no. 11, Nov, 2005.

[2] A. C. Metting van Rijn, A. Peper, and C. A. Grimbergen, “High quality recording of bioelectric events. II: A low-noise low-power multichannel amplifier design,” Med. Biol. Eng. Comput., vol. 4, pp. 433–40, Jul. 1991.

[3] G. McGlinchey, S. Pietkiewicz, R. Frank, P. Schmidt-Andersen, and F. Hansen, “A programmable medical data acquisition system chip,” in Proc. IEEE Custom Integrated Circuits Conf., May 1988, pp. 9.4/1–9.4/6.

[4] Gilbert Promitzer, “12 Bit Low Power Fully Differential Switched Capacitor Non-Calibrating Successive Approximation ADC with 1MS/s,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1138-1143, July. 2001.

[5] You-Kuang Chang, Chao-Shiun Wang and Chorng-Kuang Wang, “A 8-bit 500-KS/s Low Power SAR ADC for Biomedical Applications,” IEEE Asian Solid-State Circuits Conference, pp. 228-231, Nov. 2007.

[6] Zhaohui Huang and Peixin Zhong, “An adaptive Analog-to-Digital Converter Based on Low-Power Dynamic Latch Comparator,” IEEE International Conference on Electro Information Technology, 6 pp. - 6, May. 2005.

[7] Shuenn-Yuh Lee, Chih-Jen Cheng, Cheng-Pin Wang, and Shyh-Chyang Lee, “A 1-V 8-bit 0.95mW successive approximation ADC for biosignal acquisition systems,” IEEE International Symposium on Circuits and Systems, pp. 649 – 652, May, 2009.

[8] Harish Balasubramaniam, Wjatscheslaw Galjan, Wolfgang H. Krautschneider and Harald Neubauer, “12-bit Hybrid C2C DAC based SAR ADC with Floating Voltage Shield,” IEEE International Conference on Signals, Circuits and Systems, pp. 1-5, Nov, 2009.

[9] Kumar Parthasarathy, Turker Kuyel, Zhongjun Yu, Degang Chen and Randy Geiger, “A 16-bit Resistor String DAC with Full-Calibration at Final Test,” IEEE International Test Conference, 10 pp. – 75, Nov, 2005.

[10] T.O.Anderson, “Optimum Control Logic for Successive Approximation Analog-to-Digital Converters,” JPL TECHNICAL REPORT 32-1526, VOL. XIII, pp. 168-176, Dec. 1971.

AuthourLi Yu, was born in Nanjing, China, in 1983. He received the MSc degree in IC Design Engineering from The Hong Kong University of Science and Technology, Hong Kong SAR, China, in 2008. He is currently with the Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China, as a research assistant. His current research interests include low-power analog circuits design and layout for biomedical applications.

Fig. 9.Simulation result of dynamic comparator

Fig. 11.Die photograph of AFE