University of Tehran Department of Electrical and Computer Engineering

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University of Tehran Department of Electrical and Computer Engineering ISSCC 2013 / SESSION 18 / ADVANCED EMBEDDED SRAM / 18.1 A 20nm 112Mb SRAM in High-κ Metal-Gate with Assist Circuitry for Low-Leakage and Low-VMIN Applications by: Milad Zamani May 2013

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University of Tehran Department of Electrical and Computer Engineering. ISSCC 2013 / SESSION 18 / ADVANCED EMBEDDED SRAM / 18.1 A 20nm 112Mb SRAM in High-κ Metal-Gate with Assist Circuitry for Low-Leakage and Low-VMIN Applications. by : Milad Zamani May 2013. Contents. Introduction - PowerPoint PPT Presentation

Transcript of University of Tehran Department of Electrical and Computer Engineering

Page 1: University of Tehran Department of Electrical and Computer Engineering

University of TehranDepartment of Electrical and Computer Engineering

ISSCC 2013 / SESSION 18 / ADVANCED EMBEDDED SRAM / 18.1

A 20nm 112Mb SRAM in High-κ Metal-Gate with Assist Circuitry for Low-Leakage and Low-VMIN Applications

 by:Milad Zamani

 

May 2013

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Contents

IntroductionProposed structure Implementation & Layout Conclusions

Introduction

Proposed structure

Implementation & Layout

Conclusions

1/17

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SRAM Structure

Stability

Leakage

Introduction

Introduction

SRAM StructureStability Leakage

2/17

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SRAM Structure

◦ Cell◦ Decoder◦ Sense Amplifier◦ Write Driver◦ Timing

Introduction

3/17

SRAM Structure

Stability

Leakage

Jan M. Rabaey, Anantha P. handrakasan, Borivoje Nikolić, “Digital integrated circuits: a design perspective” , Prentice Hall; 2 edition, January 3, 2003.

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Stability

◦ Static Noise Margin (SNM)

Introduction

4/17

SRAM Structure

Stability

Leakage

Jan M. Rabaey, Anantha P. handrakasan, Borivoje Nikolić, “Digital integrated circuits: a design perspective” , Prentice Hall; 2 edition, January 3, 2003.

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Stability

◦ Dynamic Noise MarginIntroduction

Seng Oon Toh; Zheng Guo; Liu, T.-J.K.; Nikolic, B.; , "Characterization of Dynamic SRAM Stability in 45 nm CMOS," Solid-State Circuits, IEEE Journal of , vol.46, no.11, pp.2702-2712, Nov. 20115/17

SRAM Structure

Stability

Leakage

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Introduction

6/17

SRAM Structure

Stability

Leakage

Subthreshold SRAM

◦ Leakage Current

Verma, N.; Chandrakasan, A.P.; , "A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy," Solid-State Circuits, IEEE Journal of , vol.43, no.1, pp.141-149, Jan. 2008

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Proposed Circuit

PSWL & BT-NBL

Proposed structure

Proposed Circuitpartially suppressed wordline (PSWL) scheme and

bitline-length-tracked negative-bitline-boosting (BT-NBL) scheme

Power management

7/17

Power management

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Proposed structure

8/17

Proposed Circuit

Chang, Jonathan; Chen, Yen-Huei; Cheng, Hank; Chan, Wei-Min; Liao, Hung-Jen; Li, Quincy; Chang, Stanley; Natarajan, Sreedhar; Lee, Robin; Wang, Ping-Wei; Lin, Shyue-Shyh; Wu, Chung-Cheng; Cheng, Kuan-Lun; Cao, Min; Chang, George H., "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 

PSWL & BT-NBL

Power management

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Proposed structure

9/17

Proposed Circuit

Chang, Jonathan; Chen, Yen-Huei; Cheng, Hank; Chan, Wei-Min; Liao, Hung-Jen; Li, Quincy; Chang, Stanley; Natarajan, Sreedhar; Lee, Robin; Wang, Ping-Wei; Lin, Shyue-Shyh; Wu, Chung-Cheng; Cheng, Kuan-Lun; Cao, Min; Chang, George H., "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 

PSWL & BT-NBL

Power management

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Proposed structure

10/17

Proposed Circuit

Chang, Jonathan; Chen, Yen-Huei; Cheng, Hank; Chan, Wei-Min; Liao, Hung-Jen; Li, Quincy; Chang, Stanley; Natarajan, Sreedhar; Lee, Robin; Wang, Ping-Wei; Lin, Shyue-Shyh; Wu, Chung-Cheng; Cheng, Kuan-Lun; Cao, Min; Chang, George H., "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 

PSWL & BT-NBL

Power management

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Implementation & Layout

layout

Structure Structure layout

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BlockRT

BlockLT

BlockRB

BlockLB

Central Unit

256

Row

s

128 ColumnsAddress/Data Reg.

B0 B19

SA0

WD0

SA31

WD31

SA0

WD0

SA31

WD31

Add

ress

/Con

trolWL

WL

WL

SS

Row

Pre

-dec

oder

RT

SS

Row

Pre

-dec

oder

LT

WL

WL

WL

Data Line RData Line L

SS

Row

Pre

-dec

oder

RB

SS

Row

Pre

-dec

oder

LB Dat

a Li

ne

Wor

d 0

Wor

d 1

Wor

d 0

Wor

d 1

Timing Control

Dum

my

Col

umn

Pos

t Dec

oder

Pos

t Dec

oder

Post D

ecoderP

ost Decoder

CLK, CS, WE

A0-A12

DO0-DO31

Implementation & Layout

layout

Structure

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13/17

Implementation & Layout

layout

Structure

Chang, Jonathan; Chen, Yen-Huei; Cheng, Hank; Chan, Wei-Min; Liao, Hung-Jen; Li, Quincy; Chang, Stanley; Natarajan, Sreedhar; Lee, Robin; Wang, Ping-Wei; Lin, Shyue-Shyh; Wu, Chung-Cheng; Cheng, Kuan-Lun; Cao, Min; Chang, George H., "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 

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Implementation & Layout

layout

Structure

The die area of the test-chip is 40.3mm2 with 448 (2048×134) SRAM macros

Chang, Jonathan; Chen, Yen-Huei; Cheng, Hank; Chan, Wei-Min; Liao, Hung-Jen; Li, Quincy; Chang, Stanley; Natarajan, Sreedhar; Lee, Robin; Wang, Ping-Wei; Lin, Shyue-Shyh; Wu, Chung-Cheng; Cheng, Kuan-Lun; Cao, Min; Chang, George H., "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 

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With the SD, PSD and DR power-management modes, the SRAM leakage current is reduced to 16.6% for full macro shut down, 44.7% of peripheral circuits shut down and 34.2% for the peripheral circuits shut down with arrays entering into data-retention mode

Nothing about stability !!!

Conclusion

15/16

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Trends

Trends

16/17

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Trends

Trends

17/17

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Refrence Jan M. Rabaey, Anantha P. handrakasan, Borivoje Nikolić, “Digital integrated circuits: a design perspective” ,

Prentice Hall; 2 edition, January 3, 2003. Seng Oon Toh; Zheng Guo; Liu, T.-J.K.; Nikolic, B.; , "Characterization of Dynamic SRAM Stability in 45 nm

CMOS," Solid-State Circuits, IEEE Journal of , vol.46, no.11, pp.2702-2712, Nov. 2011 Verma, N.; Chandrakasan, A.P.; , "A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier

Redundancy," Solid-State Circuits, IEEE Journal of , vol.43, no.1, pp.141-149, Jan. 2008 Chang, Jonathan; Chen, Yen-Huei; Cheng, Hank; Chan, Wei-Min; Liao, Hung-Jen; Li, Quincy; Chang, Stanley;

Natarajan, Sreedhar; Lee, Robin; Wang, Ping-Wei; Lin, Shyue-Shyh; Wu, Chung-Cheng; Cheng, Kuan-Lun; Cao, Min; Chang, George H., "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 

Trends in ISSCC 2013