Transformer-coupled -network differential CMOS oscillator ...ic2307/papers/3.pdf · function (ISF)....

Transformer-coupled π-network differential CMOS oscillator circuittopology

Ilias Chlis1,2, Domenico Pepe1 and Domenico Zito1,2,*,†

1Marconi Lab, Micro & Nano Systems Centre, Tyndall National Institute, Cork, Ireland2Electrical & Electronic Engineering, School of Engineering, University College Cork, Cork, Ireland

SUMMARY

This paper reports a novel oscillator circuit topology based on a transformer-coupled π-network. As a casestudy, the proposed oscillator topology has been designed and studied for 60GHz applications in the frameof the emerging fifth generation wireless communications. The analytical expression of the oscillation fre-quency is derived and validated through circuit simulations. The root-locus analysis shows that oscillationsoccur only at that resonant frequency of the LC tank. Moreover, a closed-form expression for the qualityfactor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of theLC tank due to the transformer-coupling. Last, a phase noise analysis is reported and the analytical expres-sions of phase noise due to flicker and thermal noise sources are derived and validated by the resultsobtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS processdesign kit commercially available. Copyright © 2016 John Wiley & Sons, Ltd.

Received 11 February 2016; Revised 31 May 2016; Accepted 6 June 2016

KEY WORDS: CMOS; circuit analysis; oscillator topology; phase noise; π-network; transformer; 60GHz

1. INTRODUCTION

Rising data-rate demands have increased exponentially the traffic in current mobile networks. Thisdramatic increase in the demand for high data capacity has pushed towards the development of fifth-generation (5G) cellular systems [1, 2]. More in general, the emerging 5G networks are supposed tooperate at the millimeter-wave (mm-wave) frequencies, allowing wider spectrum allocations andfaster data-rates. For instance, the emerging 60-GHz band is a candidate for high data-rate short-range wireless communication systems, with applications such as uncompressed high-definitionvideo communications [3] or body-centric networks [4]. The major motivation for using the 60-GHzband is that a very large block of unlicensed spectrum is available. In the US, for example, theFederal Communications Commission (FCC) has allocated an unlicensed 7-GHz wide band in theradio-frequency (RF) spectrum from 57 to 64GHz for wireless communications.

Over the past years, oscillators operating at a few gigahertz achieved phase noise lower than �140dBc/Hz at 10MHz frequency offset [5]. However, at mm-wave frequencies, the losses associated withthe reactive elements (inductors and capacitors) lower significantly the quality factor (Q) of the LCtank, thus limiting the performance, especially in terms of phase noise. This mandates in-depthanalysis and adoption of new oscillator design techniques and circuit topologies, so limiting theimpact of losses on phase noise performance.

*Correspondence to: Domenico Zito, Tyndall National Institute, University College Cork, Lee Maltings, Dyke Parade,Cork, Ireland.

†E-mail: [email protected]

Copyright © 2016 John Wiley & Sons, Ltd.

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONSInt. J. Circ. Theor. Appl. (2016)Published online in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.2236

In [6], we proposed the implementation of three techniques for phase noise reduction in Colpittsoscillator topology operating at the mm-waves. In detail, we applied and analyzed theoretically forthe first time the techniques of inductive degeneration, noise filtering, and optimum current density.The results of the analyses show that, under the adopted common design conditions in a 28 nmCMOS technology, the earlier techniques may potentially lead to phase noise reduction up to about20 dB with respect to the traditional oscillator topology. Moreover, in our previous studies [7], wecarried out comparative analyses of phase noise for four oscillator circuit topologies: common-source cross-coupled pair, Colpitts, Hartley and Armstrong, under common conditions. Theinvestigations allowed us to extend the range of design possibilities beyond the common practice ofchoosing the common-source cross-coupled differential pair topology, traditionally selected for itsreliable start-up, but without further topological considerations. The results presented therein [7],suggest the opportunity to invest additional studies and efforts in exploring the circuit designimplementations also of other topologies, whose potential may have been perhaps underestimated upto date and lacking in-depth analyses, especially at very high frequencies.

On the basis of the earlier motivations, in this paper, we present a novel differential oscillator circuittopology using a transformer-coupled feedback π-network, shown in Figure 1. The effective LC tank Qis enhanced by 1+k, where k is the coupling factor for the transformers, thereby with a potential forlow phase noise (i.e. high spectral purity).

The oscillator topology is analyzed and compared under common conditions with the oscillatortopologies examined therein [7]. The analytical expression of the oscillation frequency is derived bymeans of circuit theory and validated by means of the results provided by SpectreRF simulations inCadence. Use of root-locus analysis proves that the oscillator topology oscillates at the targetedfrequency. Moreover, a closed-form expression for the quality factor is derived, so showing theenhancement of the quality factor (Q) of the LC tank due to the transformer-coupling. Then, weaddress a complete analytical study of phase noise in the proposed topology, with the objective ofproviding a closed-form symbolic expression for the phase noise by using the impulse sensitivityfunction (ISF). In detail, we report a theoretical analysis of the phase noise exhibited by thedifferential oscillator circuit topology using a transformer-coupled feedback π-network shown inFigure 1, in both the 1/f3 and 1/f2 regions. The analytical expressions derived by our theoreticalstudy are then validated through the comparison with the results of the circuit simulations carriedout within the Cadence design environment.

In this paper, we take into account the full models of the transistors of a process design kitcommercially available, which adopts the BSIM4v4 model including their parasitic components andsecond order effects. In compliance with the expectations from the theoretical study, in our analyses,we will exclude the effects of the layout interconnections that introduce additional parasiticcomponents, unwanted coupling, and other proximity effects, which can be minimized by careful

Figure 1. Schematic of the differential oscillator circuit topology using a transformer-coupled feedbackπ-network. VB1 is a dc bias voltage source. The π-network which comprises of the L1, L2 and C1 pairs,

provides the 180o phase shift required between the gate and drain of transistor M1.

I. CHLIS, D. PEPE AND D. ZITO

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2016DOI: 10.1002/cta

layout and estimated through electromagnetic and parasitic extraction tools according to latestadvanced design approach for high-frequency integrated circuits on silicon [8, 9]. Moreover, it isworth considering that the additional parasitic components introduced by the layout could lead to anunjustified increase of complexity and cumbersome expressions that could mask the inherenttopological properties that we would like bringing to the light in our study. Capacitors will beconsidered as ideal components, whereas a typical quality factor (Q) of 10 is considered for all thespiral inductors [10]. The assumptions made earlier are reasonable in a first-order approximation andin line with the typical achievable values and the common practice adopted by other theoreticalstudies reported in the literature [11]. From the comparison with the circuit simulation results, wewill see that the results of our study are in good agreement.

The paper is organized as follows. In Section II, the analytical expression of the oscillationfrequency f0 is derived by means of circuit theory and validated by means of the results provided bySpectreRF simulations in Cadence. The root locus analysis of the oscillator topology is reported toprove that oscillation occurs at the resonant frequency f0 of the LC tank. Moreover, a closed-formexpression for the quality factor of the LC tank is derived by means of circuit theory. Section III,reports the analysis of phase noise for the proposed oscillator topology. The theoretical results arevalidated by the results obtained from SpectreRF simulations for the oscillation frequency of60GHz. Finally, conclusions are drawn in Section IV.

2. ANALYSIS OF THE OSCILLATOR CIRCUIT TOPOLOGY

2.1. Oscillation frequency

Figure 1 shows the differential oscillator circuit topology using a transformer-coupled feedback π-network designed in 28 nm fully depleted silicon-on-insulator (FDSOI) CMOS technology with 1Vsupply voltage. C2 is used to tune the oscillation frequency. The π-network which comprises of theL1, L2 and C1 pairs, provides the 180o phase shift required between the gate and drain of transistorM1. The magnetic coupling between L1 and L2 pairs allows the enhancement of the equivalent Q ofthe LC tank as will be shown in Section III. In order to make the results directly comparable withthose of our previous works, the oscillator circuit design has been carried out with the sametransistor size, power and current consumptions, inductance of the tanks, and their quality factors, asin [7]. In particular, the width of transistor pair M1 is 15μm. The dc bias voltage source VB1 inFigure 1, is chosen such that the total power consumption is 6.3mW. In addition, a typical couplingfactor k of 0.85 is considered for the transformers [12, 13].

Figure 2 (a–b) shows the single-ended small-signal equivalent circuit of the oscillator topology. It isobtained by considering the simplified transistor equivalent circuit with the small-signaltransconductance (gm), gate-to-source capacitance (Cgs), gate-to-drain capacitance (Cgd), source-to-bulk capacitance (Csb), and drain-to-bulk capacitance (Cdb). In the interest of a low complexity ofthe derived equations, the small-signal output resistance ro as well as the polysilicon gate resistance

Figure 2. (a) Single-ended small-signal equivalent circuit of the oscillator circuit topology of Figure 1 forderivation of the tank impedance. (b) Equivalent circuit of (a).

TRANSFORMER-COUPLED π-NETWORK DIFFERENTIAL CMOS OSCILLATOR TOPOLOGY


rg of M1, are neglected. Later, we will see that this working hypothesis is acceptable. C1 appears inparallel with Cgd and C2 appears in parallel with Cdb. Their sum can be represented as an equivalentcapacitance C′1 and C′2, respectively. L′1 and L′2 are equal to (1 + k) ×L1 and (1 +k) ×L2, respectively.

In order to calculate the oscillation frequency f0, we derive first an expression for the tankimpedance Zin =Vin/Iin. Considering Z1 and Z2 the impedance of the parallel combination of L′1, C′2and L′2, Cgs, respectively, we can write

Vin ¼ I3 Z2 þ 1

sC′1

� �(1)

I3 ¼ 11þ gmZ2

I2 (2)

I2 ¼ I in � Vin

Z1(3)

Combining (1–3), we obtain

Zin ¼s s2 C′

1 þ Cgs� �þ 1

L′2

h is4 C′

1C′2 þ C′

1Cgs þ C′2Cgs

� �þ C′1gms3 þ s2 C′

1

L′2þ C′

1

L′1þ C′

2

L′2þ Cgs

L′1

� �þ 1

L′1L′2

(4)

We then derive the oscillation frequency f0 by equating the imaginary part of Zin to zero.

f o ¼12π

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiC′

1L′1 þ C′

1L′2 þ C′

2L′1 þ CgsL′2 �

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiC′

1L′1 þ C′

1L′2

� �2 þ 2C′1 L′1 � L′2� �

C′2L

′1 � CgsL′2

� �þ C′2L

′1 � CgsL′2

� �2q2L′1L

′2 C′

1C′2 þ C′

1Cgs þ C′2Cgs

� �vuut

(5)

Figure 3 shows the results obtained by the theoretical expression of the oscillation frequencyprovided by (5), as a function of C2. Note that the oscillation frequency predicted by (5) closelyfollows the simulation results obtained by SpectreRF. In particular, the maximum differenceamounts to about 1.5GHz, observed for C2 = 5 fF. Thereby, the aforementioned simplifications inthe derivation of (5) are justified for an accurate first-order prediction of the oscillation frequency f0.

Figure 3. Oscillation frequency values vs. C2 for the circuit of Figure 1, predicted by (5), and simulated inSpectreRF for an oscillation frequency in the vicinity of 60GHz.



Then, we perform a root-locus analysis in order to prove that the oscillator topology indeedoscillates at f0. First, an expression for the closed-loop voltage gain of the oscillator topology isderived by calculating Vout2(s)/Vin2(s) as shown in Figure 4 (a–b), where Z′1 and Z′2 are theimpedance of the parallel combination of L′1, C′2 and L′2, Cgs, respectively, including the parasiticresistance in series with L1 and L2, r1 and r2, respectively. We can now write that

Vout2 ¼ I6 Z ′2 þ

1

sC′1

� �(6)

I6 ¼�Vout2

Z ′1

� gmVin2 (7)

From (6) and (7) we derive that

Vout2 sð ÞVin2 sð Þ ¼ �gm

Num sð ÞDen sð Þ (8)

where

Num sð Þ ¼ 1

C′2

1

C′1

þ 1Cgs

� �s3 þ C′

1 þ Cgs

C′1C

′2Cgs

r1L′1

þ r2L′2

s2 þ 1

L′2C′1C

′2Cgs

þ r1r2 C′1 þ Cgs

� �L′1L

′2C

′1C

′2Cgs

" #s

þ r1L′1L

′2C

′1C

′2Cgs

(9)

Den sð Þ ¼ 1

C′1

þ 1

C′2

þ 1Cgs

� �s4 þ r1

L′1þ r2L′2

� �1

C′1

þ 1

C′2

þ 1Cgs

� �s3

þ 1

C′2CgsL′2

þ 1

C′2CgsL′1

þ 1

C′1CgsL′2

þ 1

C′1C

′2L

′1

þ"

r1r2L′1L

′2

1

C′1

þ 1

C′2

þ 1Cgs

� �s2

þC′1r1 þ C′

1r2 þ C′2r1 þ Cgsr2

C′1C

′2CgsL′1L

′2

sþ 1

L′1L′2C

′1C

′2Cgs

(10)

Figure 5 shows the root locus plot derived from this theoretical analysis, with the trajectory of polestowards zeros for different values of the closed-loop tank voltage gain. Blue and green lines correspondto the pole pair causing the oscillator to resonate at f0. In practical cases, the oscillator can oscillate onlyat that resonant frequency because the pole pair corresponding to the second resonant frequency only

Figure 4. (a) Single-ended small-signal equivalent circuit of the oscillator circuit topology of Figure 1 forderivation of the closed-loop tank voltage gain. (b) Equivalent circuit of (a).



slightly enters the right half plane. Moreover, the transistor M1 has a lower gain at the second resonantfrequency with respect to f0.

2.2. Quality factor

In order to show that the magnetic coupling between L1 and L2 pairs enhances the Q of the LC tank inthe oscillator topology of Figure 1, we will derive a closed-form expression for Q. In order to do that, webreak the oscillator loop at the gate of M1, so as to find the open-loop transfer function Vout3(s)/Iin2(s)[14], as shown in Figure 6. This yields

I7 þ I in2 þ I8 ¼ 0 (11)

Vout3 ¼ I7 þ I in2ð Þ 1

sC′1

þ I7Z ′1 (12)

Figure 5. Root-locus plot of the oscillator circuit topology of Figure 1 for various values of the tank voltageloop gain.

Figure 6. (a) Single-ended small-signal equivalent circuit of the oscillator circuit topology of Figure 1 forderivation of the oscillator’s open-loop transfer function. (b) Equivalent circuit of (a).



I8 ¼ Vout3

Z ′2

(13)

From (11) to (13) we derive

Vout3 sð ÞI in2 sð Þ ¼ As3 þ Bs2 þ Cs

Ds4 þ Es3 þ Fs2 þ Gsþ 1(14)

where

A ¼�C′1L

′1L

′2 (15)

B ¼�C′1 L′1r2 þ L′2r1� �

(16)

C ¼ �C′1r1r2 (17)

D ¼ L′1L′2 C′

1C′2 þ C′

1Cgs þ C′2Cgs

� �(18)

E ¼ C′1C

′2 þ C′

1Cgs þ C′2Cgs

� �L′1r2 þ L′2r1� �

(19)

F ¼ r1r2 C′1C

′2 þ C′

1Cgs þ C′2Cgs

� �þ L′1 C′1 þ C′

2

� �þ L′2 C′1 þ Cgs

� �(20)

G ¼ C′1 r1 þ r2ð Þ þ C′

2r1 þ Cgsr2 (21)

Q can be calculated from (14) as follows

Q ¼�ω2dϕ ωð Þdω

(22)

where ω is the angular frequency and ϕ is the phase of the open-loop transfer function Vout3/Iin2equal to

ϕ ¼ tan�1ω �Aω2 þ Cð Þ

�Bω2� tan�1

ω �Eω2 þ Gð ÞDω4 � Fω2 þ 1

(23)

Near f0, we yield

dϕ ωð Þdω

≈4Dω2 � 2FG� Eω2

(24)

Q≈Fω� 2Dω3

G� Eω2(25)

By replacing D, E, F, and G, we find that

Q≈ 1þ kð Þ L′1 C′1 þ C′

2

� �þ L′2 C′1 þ Cgs

� �� 2ω2L′1L′2 C′

1C′2 þ C′

1Cgs þ C′2Cgs

� �L′1Q1

C′1 þ C′

2

� �þ L′2Q2

C′1 þ Cgs

� �� ω2L′1L′2 C′

1C′2 þ C′

1Cgs þ C′2Cgs

� �1Q1

þ 1Q2

� � (26)

where Q1, Q2 are the quality factors of L1 and L2, respectively. Assuming Q1=Q2=Q0, thenQ≈ (1 + k) ×Q0. Therefore, the magnetic coupling between L1 and L2 can enhance the equivalent



quality factor of the LC tank up to 1+k times. It is worth mentioning that the higher the Q of theLC tank, the higher is the resulting amplitude of the output oscillation voltage. For Q1=Q2=10, thesingle-ended peak amplitude of the output voltage is about 1.05V.

This is very beneficial at mm-wave frequencies, where the quality factor of the integrated inductorsand capacitors is low due to loss mechanisms [15]. This limits the phase noise performance ofoscillators operating at this frequency range. Also, in ultra-scaled technology nodes, it is even morechallenging to achieve a high quality factor, due to reduced thickness of the metal layers [16, 17].Thereby, the proposed oscillator topology which enhances the effective Q of the LC tank, shows apotential for achieving a high spectral purity at the mm-wave frequency range.

Figure 7 shows a three-dimensional (3-D) plot of the LC tank Q, with respect to L=L1=L2 and theoscillation frequency f0, considering Q1=Q2=Q0=10. As calculated earlier, around f0 = 60GHz, theeffective Q amounts to about (1 +k) ×Q0=18.5.

3. PHASE NOISE ANALYSIS

In this section, we address an analytical study of the novel topology proposed here, with the objectiveof providing a closed-form symbolic expression for the phase noise by using the impulse sensitivityfunction.

In our study, we aim at extending the analysis to the 1/f3 phase noise region because such ananalysis would be essential in order to achieve a good phase noise prediction in oscillator topologiesdesigned in deep submicron (nano-scale) technologies. Indeed, flicker noise in the output spectrumof an integrated CMOS oscillator is particularly important because the 1/f3 phase noise regionusually extends beyond 1MHz offset from the oscillation frequency, as a consequence of nano-scaledevices featuring 1/f corner frequencies of several tens or hundreds of megahertz [7].

Figure 8 shows the single-ended large-signal equivalent circuit of the differential oscillator circuittopology of Figure 1, based on the describing function approach, after changing the groundreference [11,18]. With reference to Figure 1, we define CGS as the large-signal capacitancebetween gate and source of M1. C1EQ represents the parallel combination of C1 with the large signalgate-to-drain capacitance CGD of M1, whereas C2EQ is the parallel combination of C2 with the large-signal drain-to-bulk capacitance CDB of M1. Transistor M1 is replaced by the fundamental currentharmonic I1 that it delivers to the LC tank. We denote the drain and gate resonator impedances asZ3 and Z4, respectively. They are given by (27) and (28), respectively.

Figure 7. Three-dimensional (3-D) plot of the LC tank quality factor (Q) for the oscillator circuit topology ofFigure 1, with respect to L=L1 =L2 and the oscillation frequency f0, with the assumption that

Q1 =Q2=Q0= 10.



Z3 ¼ L′1R1sC2EQL′1R1s2 þ L′1sþ R1

(27)

Z4 ¼ L′2R2sCGSL′2R2s2 þ L′2sþ R2

(28)

where R1, R2 are the parasitic resistances in parallel with L1 and L2, respectively.We define n as the ratio Z4/(Z3+Z4). Z3+Z4 can be interpreted as a parallel RLC resonator made of an

inductance LT=L′1 +L′2, a resistance RT=R1+R2, and a capacitance Cp=C1EQ+C2EQCGS/(C2EQ+CGS)[18]. Assuming that the losses due to the parasitic resistance of the inductors L1 and L2 dominate the lossesin the drain and gate resonators, R1 and R2 are equal to Q1L1ω and Q2L2ω, respectively.

Despite the circuit differences between this oscillator topology and the topology in [18], such as (i)the different feedback mechanism here based on the π-network instead of the magnetic coupling usedin [18], (ii) the absence of current bias source transistor in this case, and (iii) magnetic couplingbetween L1 and L2 pairs allowing an increase of the effective quality factor (Q) of the LC tank, thenew circuit re-arrangement of Figure 8 leads to a phase noise expression formally equivalent tothose obtained in [18], but related to different circuit elements and thereby different qualitative andquantitative evaluations. For instance, comparing the equivalent circuit in Figure 8 with theequivalent circuit of Figure 3 therein [18], one can note that there is no magnetic coupling betweenthe circuit elements of the feedback network in this case.

Thereby the phase noise due to flicker and thermal noise can now be written as [18]

where K is a process-dependent constant approximately equal to 10�23 V2F, μn is the electron mobilityapproximately equal to 0.06m2/(V× s), ω1=f 3 is the frequency, where the sideband power due to

thermal noise is equal to the sideband power due to flicker noise, ω 1/f is the corner frequency of theflicker noise generated by M1, N=2 for the π-network differential oscillator topology, Δω is theangular frequency offset from the oscillation frequency, Gm is the large-signal transconductance ofM1 equal to the ratio of the fundamental component of the drain current over the fundamental

Figure 8. Single-ended large-signal equivalent circuit of the differential oscillator circuit topology ofFigure 1, based on the describing function approach, after changing the ground reference.



component of the gate-to-source voltage, Rp is equal to Q21;2�R2

1;2, Vtank is the peak amplitude of theoutput voltage, L is the channel length of M1, KB is the Boltzmann constant, T is the absolutetemperature, and γ is the excess noise coefficient.

The overall phase noise is given by

For simplicity, we assume that the drain and gate resonators are identical, neglecting the possibleslight difference in parasitic capacitance of the resonators. This means that n is a real number andequal to 0.5. Moreover, in order to compare the phase noise performance of the proposed oscillatortopology with the results reported in our previous studies, under the same common conditions, weconsider a quality factor of 10 at 60GHz, whereas L1 and L2 are chosen such that their seriesparasitic resistance is the same as in [7], so that it generates the same amount of thermal noise. L1

and L2 are both equal to 83 pH.Figure 9 shows the phase noise obtained by direct plots from periodic steady state (PSS) and

periodic noise (Pnoise) circuit simulations in SpectreRF, for an oscillation frequency of 60GHz.Phase noise is reported over a wide frequency offset from the carrier frequency, in order to includethe regions in which the noise at the output spectrum is dominated by either flicker or thermal noise.

Figure 9 reports also the numerical evaluations of the theoretical expressions of phase noise due toflicker and thermal noise from (29) to (30) respectively, as well as the total phase noise from (31). Notethat the theoretical phase noise predicted by (29)–(31) matches well with the results obtained by meansof SpectreRF simulations. Even for the frequency offset of 400kHz, where the worst match is observed,the theoretical phase noise predicted by (31) is within 3dB difference from the simulation results.

At this stage, it is worth also comparing these results obtained from the differential oscillator circuittopology using a transformer-coupled feedback π-network with those obtained for the oscillator circuittopologies reported in [7]. In particular, from Figure 9, we can observe that the phase noise at a 1MHzoffset from the oscillation frequency is �94 dBc/Hz. By comparing this phase noise result with thoseachieved for the common-source cross-coupled, Colpitts, Hartley and Armstrong oscillator topologiesexamined therein [7] under the same common conditions, we conclude that the proposed topologyshows superior phase noise performance at 60GHz.

A summary of the performance achieved by the proposed oscillator circuit topology and a comparisonwith the measured and simulated state-of-the-art solutions for 60GHz CMOS oscillators are reported inTable I. This oscillator topology has the potential to exhibit the lowest power consumption and acompetitive phase noise and Figure of Merit (FOM), with respect to the state of the art.

Figure 9. Phase noise vs. frequency offset obtained from direct plots through PSS and Pnoise SpectreRFsimulations, as well as from the theoretical expressions of (29)–(31) for an oscillation frequency of 60GHz.



4. CONCLUSIONS

In this paper, we reported and analyzed a novel oscillator circuit topology based on a transformer-coupled π-network and designed as a case study to be operating at the mm-wave frequency range.The analytical expression of the oscillation frequency is derived by means of circuit theory andvalidated by means of the results provided by SpectreRF simulations in Cadence. A root-locusanalysis shows that this is the only resonant frequency of the LC tank which guaranteesoscillation.

Moreover, a closed-form expression for the quality factor is derived which demonstrates theenhancement of the quality factor (Q) of the LC tank due to the transformer-coupling. Indeed, atmm-wave frequencies, the quality factor of the integrated inductors and capacitors is low, and thislimits the phase noise performance. Also, in ultra-scaled technology nodes, it is even morechallenging to achieve a high quality factor, due to reduced thickness of the metal layers. Thereby,the proposed oscillator topology improves the effective Q of the LC tank so exhibiting a goodpotential for achieving a high spectral purity at the mm-wave frequency range.

Then, we provided a theoretical analysis of the phase noise in the differential oscillator circuittopology, both in the 1/f3 and 1/f2 regions, in order to allow accurate predictions. The derivedanalytical expressions of the phase noise have been validated through a direct comparison with theresults obtained by SpectreRF simulations for an oscillation frequency of 60GHz. Under theadopted design conditions, the theoretical and simulation results are in a good agreement, with amaximum deviation of about 3 dB.

The results show that, under the adopted design conditions, the proposed oscillator topology showsa potential for superior phase noise performance with respect to traditional oscillator topologiesconsidered in our previous studies. Recent studies refer to the common-source cross-coupleddifferential pair topology as the one with the best phase noise as a consequence of the circuitdesigns carried out at lower frequencies. The results of the analysis of the proposed oscillator circuittopology contribute to extending our consideration also to other topologies, beyond the commonpractice of choosing the common-source cross-coupled differential pair topology, especially at themm-wave frequency range, where the quality factor of passive devices limits significantly theachievable phase noise performance.

ACKNOWLEDGEMENTS

The authors would like to thank Science Foundation Ireland (SFI) for their financial support through theresearch project grants 11/RFP/ECE3325 and 07/SK/I1258. This publication has emanated also fromresearch supported in part by another research grant from SFI and is co-funded under the European RegionalDevelopment Fund under Grant Number 13/RC/2077.

Table I. Summary of performance and comparison with the state of the art.

Ref. TechnologyFreq.[GHz]

PN @ 1MHz freq.offset [dBc/Hz]

Power[mW]

FOM[dB] #

[19]* 0.18μm BiCMOS 60.1 �93.5 19.1 181[20]* 65 nm CMOS 62 �89.8 15.6 176[21]* 90 nm CMOS 60 �90 12 181[22]* 65 nm CMOS 63 �92.2 21.5 182.6[23]* 90 nm CMOS 63.95 �91.53 7.2 178.1[24]** 65 nm CMOS 60 �97.5 12 182.3[25]** 65 nm CMOS 60 �91.6 157 165.2[26]** 130 nm CMOS 60 �87 12 171.8This work** 28 nm CMOS 60 �94 6.3 181.6

*measurements;**simulations#FOM ¼ 10log f 0

Δf

� �21

PN�PmW



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