TLV2772, TLV2772A, TLV2772Y 2.7-V HIGH-SLEW · PDF filetlv2772, tlv2772a, tlv2772y 2.7-v...

TLV2772, TLV2772A, TLV2772Y2.7-V HIGH-SLEW-RATE RAIL-TO-RAIL OUTPUT

DUAL OPERATIONAL AMPLIFIERS

SLOS209 – JANUARY 1998

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

High Slew Rat e . . . 10.5 V/µs Typ

High-Gain Bandwidt h . . . 5.1 MHz Typ

Supply Voltage Range 2.7 V to 5 V

Rail-to-Rail Output

360 µV Input Offset Voltage

Low Distortion Driving 600- Ω 0.005% THD+N

1 mA Supply Current (Per Channel)

17 nV/√Hz Input Noise Voltage

2 pA Input Bias Current

Characterized from T A = –40°C to 125°C Available in MSOP (DGK) Package

description

The TLV2772 dual CMOS operational amplifier combines high slew rate and bandwidth, rail-to-rail output swing,high output drive and excellent dc precision. The device provides 10.5 V/µs of slew rate and 5.1 MHz ofbandwidth while only consuming 1 mA of supply current per channel. This ac performance is much higher thancurrent competitive CMOS amplifiers. The rail-to-rail output swing and high output drive makes this device agood choice for driving the analog input or reference of analog-to-digital converters. The device also has lowdistortion while driving a 600-Ω load for use in telecom systems.

The amplifier has a 360 µV input offset voltage, a 17 nV Hz input noise voltage, and a 2 pA input bias currentfor measurement, medical, and industrial applications. The TLV2772 is also specified across an extendedtemperature range (–40°C to 125°C) making it useful for automotive systems.

The device operates from a 2.2 V to 5.5 V single supply voltage and is characterized at 2.7 V and 5 V. The singlesupply operation and low power consumption make this device a good solution for portable applications. It isavailable in an 8-pin PDIP, SOIC and ultra-low profile MSOP package.

AVAILABLE OPTIONS

PACKAGED DEVICESCHIP FORM‡

TA VIOmax AT 25 °C SMALL OUTLINE †

(D)MSOP(DGK)

PLASTIC DIP(P)

CHIP FORM‡

(Y)

0°C to 70°C 2.5 TLV2772CD TLV2772CDGK TLV2772CP

–40°C to 125°C2.51.6

TLV2772IDTLV2772AID

TLV2772IDGKTLV2772AIDGK

TLV2772IPTLV2772AIP

TLV2772Y

† The D packages are available taped and reeled. Add R suffix to the device type (e.g., TLV2772CDR).‡ Chip forms are tested at TA = 25°C only.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

8

7

6

5

1OUT1IN–1IN+

VDD–/GND

VDD+2OUT2IN–2IN+

D OR P PACKAGE(TOP VIEW)

1

2

3

4

8

7

6

5

1OUT1IN–1IN+

VDD–/GND

VDD+2OUT2IN–2IN+

DGK PACKAGE(TOP VIEW)

This document contains information on products in more than one phaseof development. The status of each device is indicated on the page(s)specifying its electrical characteristics.

Copyright 1998, Texas Instruments Incorporated

TLV2772, TLV2772A, TLV2772Y2.7-V HIGH-SLEW-RATE RAIL-TO-RAIL OUTPUTDUAL OPERATIONAL AMPLIFIERS


2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2772Y chip information

This chip, when properly assembled, displays characteristics similar to the TLV2772. Thermal compression orultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductiveepoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 MILS TYPICAL

BONDING PADS: 4 × 4 MILS MINIMUM

TJmax = 150°C

TOLERANCES ARE ±10%.

ALL DIMENSIONS ARE IN MILS.

+

–1OUT

1IN+

1IN–

VDD+

(8)

(6)

(3)

(2)

(5)

(1)

(7)

(4)VDD–/GND

+

–2OUT

2IN+

2IN–

51

49

(2)

(3) (4)(5)

(6)

(7)

(8)

(1)





absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †

Supply voltage, VDD (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential input voltage, VID (see Note 2) ±VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI (any input, see Note 1) –0.3 V to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input current, II (any input) ±4 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total current into VDD+ ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total current out of VDD– ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Duration of short-circuit current (at or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I suffix –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to VDD –.2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought

below VDD– – 0.3 V.3. The output may be shorted to either supply. Temperature and /or supply voltages must be limited to ensure that the maximum

dissipation rating is not exceeded.

DISSIPATION RATING TABLE

PACKAGETA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C TA = 125°C

PACKAGE APOWER RATING ABOVE TA = 25°C

APOWER RATING

APOWER RATING

APOWER RATING

D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW

DGK n/a n/a n/a n/a n/a

P 1000 mW 8.0 mW/°C 640 mW 520 mW 200 mW

recommended operating conditions

C SUFFIX I SUFFIXUNIT

MIN MAX MIN MAXUNIT

Supply voltage, VDD 2.2 5.5 2.2 5.5 V

Input voltage range, VI VDD– VDD+ –1.3 VDD– VDD+ –1.3 V

Common-mode input voltage, VIC VDD– VDD+ –1.3 VDD– VDD+ –1.3 V

Operating free-air temperature, TA 0 70 –40 125 °C




electrical characteristics at specified free-air temperature, V DD = 2.7 V (unless otherwise noted)

PARAMETER TEST CONDITIONS TA†TLV2772C

UNITPARAMETER TEST CONDITIONS TA†MIN TYP MAX

UNIT

VIO Input offset voltage

V 0 V 0

25°C 0.44 2.5mVVIO Input offset voltage

V 0 V 0

Full range 0.47 2.7mV

αVIOTemperature coefficient of input offset

V 0 V 0

25°Cto 2 µV/°CαVIO voltage

V 0 V 0

to125°C

2 µV/°C

VIC = 0,RS = 50 Ω

VO = 0,25°C 1

IIO Input offset currentRS = 50 Ω

–40°C to85°C 2 100

pA

25°C 2

IIB Input bias current –40°C to85°C 6 100

pA

VICR Common mode input voltage range CMRR > 70 dB RS = 50 Ω

25°C0to

1.4

–0.3to

1.7VVICR Common-mode input voltage range CMRR > 70 dB, RS = 50 Ω

Full range0to

1.4

–0.3to

1.7

V

IOH = 0 675 mA25°C 2.6

VOH High level output voltage

IOH = –0.675 mAFull range 2.5

VVOH High-level output voltage

IOH = 2 2 mA25°C 2.4

V


VIC = 1 35 V IOL = 0 675 mA25°C 0.1

VOL Low level output voltage

VIC = 1.35 V, IOL = 0.675 mAFull range 0.2

VVOL Low-level output voltage

VIC = 1 35 V IOL = 2 2 mA25°C 0.21

V


AVDLarge-signal differential voltage VIC = 1.35 V, RL = 10 kΩ, 25°C 20 380

V/mVAVDg g g

amplificationIC ,

VO = 0.6 V to 2.1 VL ,

Full range 13V/mV

ri(d) Differential input resistance 25°C 1012 Ω

ci(c) Common-mode input capacitance f = 10 kHz 25°C 8 pF

zo Closed-loop output impedance f = 100 kHz, AV = 10 25°C 25 Ω

CMRR Common mode rejection ratioVIC = 0 to 1.5 V, VO = 1.5 V, 25°C 70 84

dBCMRR Common-mode rejection ratio IC ,RS = 50 Ω

O ,Full range 70 82

dB

kSVRSupply voltage rejection ratio VDD = 2.7 V to 5 V, VIC = VDD/2, 25°C 70 89

dBkSVRy g j

(∆VDD /∆VIO)DD ,

No loadIC DD ,

Full range 70 84dB

IDD Supply current (per channel) VO = 1 5 V No load25°C 1 2

mAIDD Supply current (per channel) VO = 1.5 V, No loadFull range 2

mA

† Full range is 0°C to 70°C.





operating characteristics at specified free-air temperature, V DD = 2.7 V (unless otherwise noted)



UNIT

VO(PP) = 0 8 V CL = 100 pF25°C 5 9

SR Slew rate at unity gainVO(PP) = 0.8 V,RL = 10 kΩ

CL = 100 pF,Full

range4.7 6

V/µs

V Equivalent input noise voltagef = 10 Hz 25°C 147

nV/√HzVn Equivalent input noise voltagef = 1 kHz 25°C 21

nV/√Hz

VN(PP)Peak-to-peak equivalent input noise f = 0.1 Hz to 1 Hz

25°C0.33

µVVN(PP)q

voltage f = 0.1 Hz to 10 Hz25°C

0.86µV

In Equivalent input noise current f = 100 Hz 25°C 1.5 pA/√Hz

R 600 ΩAV = 1 0.0085%

THD + N Total harmonic distortion plus noiseRL = 600 Ω,f = 1 kHz

AV = 10 25°C 0.025%f = 1 kHz

AV = 100 0.12%

Gain-bandwidth product f = 10 kHz, CL = 100 pF

RL = 600 Ω, 25°C 4.8 MHz

t Settling time

AV = –1,Step = 0.85 V to 1.85 V,

0.1% 25°C 0.186µsts Settling time ,

RL = 600 Ω,CL = 100 pF 0.01% 25°C 3.92

µs

φm Phase margin at unity gainRL = 600 Ω CL = 100 pF

25°C 46°

Gain marginRL = 600 Ω, CL = 100 pF

25°C 12 dB† Full range is 0°C to 70°C.




electrical characteristics at specified free-air temperature, V DD = 2.7 V (unless otherwise noted)

PARAMETER TEST CONDITIONS TA†TLV2772I TLV2772AI

UNITPARAMETER TEST CONDITIONS TA†MIN TYP MAX MIN TYP MAX

UNIT


V 0 V 0

25°C 0.44 2.5 0.44 1.6mVVIO Input offset voltage

V 0 V 0

Full range 0.47 2.7 0.47 1.9mV

αVIO

Temperature coefficient of input

V 0 V 0

25°Cto 2 2 µV/°CαVIO coefficient of input

offset voltageV 0 V 0

to125°C

2 2 µV/°C

VIC = 0,RS = 50 Ω

VO = 0,25°C 1 1


–40°C to85°C 2 100 2 100

pA

25°C 2 2

IIB Input bias current –40°C to85°C 6 100 6 100

pA

0 –0.3 0 –0.325°C

0to

0.3to

0to

0.3to

VICRCommon-mode

CMRR > 70 dB RS = 50 Ω1.4 1.7 1.4 1.7

VVICR input voltage rangeCMRR > 70 dB, RS = 50 Ω

0 –0.3 0 –0.3V

Full range0to

0.3to

0to

0.3tog

1.4 1.7 1.4 1.7

IOH = 0 675 mA25°C 2.6 2.6

VOHHigh-level output

IOH = –0.675 mAFull range 2.5 2.5

VVOHg

voltageIOH = 2 2 mA

25°C 2.4 2.4V


VIC = 1 35 V IOL = 0 675 mA25°C 0.1 0.1

VOLLow-level output

VIC = 1.35 V, IOL = 0.675 mAFull range 0.2 0.2

VVOL voltageVIC = 1 35 V IOL = 2 2 mA

25°C 0.21 0.21V


AVD

Large-signal differential voltage

VIC = 1.35 V,R 10 kΩ

25°C 20 380 20 380V/mVAVD differential voltage

amplification

IC ,VO = 0.6 V to 2.1 V RL = 10 kΩ

Full range 13 13V/mV

ri(d)Differential inputresistance

25°C 1012 1012 Ω

ci(c)Common-mode input capacitance

f = 10 kHz, 25°C 8 8 pF

zoClosed-loopoutput impedance

f = 100 kHz, AV = 10 25°C 25 25 Ω

CMRRCommon-mode VIC = 0 to 1.5 V, VO = 1.5 V, 25°C 70 84 70 84

dBCMRRrejection ratio

IC ,RS = 50 Ω

O ,Full range 70 82 70 82

dB

kSVR

Supply voltage rejection ratio

VDD = 2.7 V to 5 V, VIC = VDD/2, 25°C 70 89 70 89dBkSVR rejection ratio

(∆VDD /∆VIO)

DD ,No load

IC DD ,

Full range 70 84 70 84dB

IDDSupply current

VO = 1 5 V No load25°C 1 2 1 2

mAIDDy

(per channel) VO = 1.5 V, No loadFull range 2 2

mA

† Full range is – 40°C to 125°C.





operating characteristics at specified free-air temperature, V DD = 2.7 V (unless otherwise noted)



UNIT

VO(PP) = 0 8 V CL = 100 pF25°C 5 9 5 9


CL = 100 pF,Full

range4.7 6 4.7 6

V/µs

VEquivalent input f = 10 Hz 25°C 147 147

nV/√HzVnq

noise voltage f = 1 kHz 25°C 21 21nV/√Hz

VN(PP)

Peak-to-peak equivalent input

f = 0.1 Hz to 1 Hz 25°C 0.33 0.33 µVVN(PP) equivalent input

noise voltage f = 0.1 Hz to 10 Hz 25°C 0.86 0.86 µV

InEquivalent inputnoise current

f = 100 Hz 25°C 1.5 1.5 pA/√Hz

T t l h i R 600 ΩAV = 1 0.0085% 0.0085%

THD + NTotal harmonicdistortion plus noise

RL = 600 Ω,f = 1 kHz

AV = 10 25°C 0.025% 0.025%distortion lus noise f = 1 kHz

AV = 100 0.12% 0.12%

Gain-bandwidth product

f = 10 kHz, CL = 100 pF

RL = 600 Ω, 25°C 4.8 4.8 MHz

t Settling time

AV = –1,Step = 0.85 V to

1 85 V

0.1% 25°C 0.186 0.186

µsts Settling time 1.85 V,RL = 600 Ω,CL = 100 pF

0.01% 25°C 3.92 3.92

µs

φmPhase margin atunity gain RL = 600 Ω, CL = 100 pF

25°C 46° 46°

Gain marginL , L

25°C 12 12 dB† Full range is –40°C to 125°C.




electrical characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted)



UNIT


V 0 V 0

25°C 0.36 2.5mVVIO Input offset voltage

V 0 V 0

Full range 0.4 2.7mV

αVIOTemperature coefficient of input offset

V 0 V 0

25°Cto 2 µV/°CαVIO voltage

V 0 V 0

to125°C

2 µV/°C

VIC = 0,RS = 50 Ω

VO = 0,25°C 1


–40°C to85°C 2 100

pA

25°C 2

IIB Input bias current –40°C to85°C 6 100

pA

VICR Common mode input voltage range CMRR > 60 dB RS = 50 Ω

25°C0to

3.7

–0.3to

3.8VVICR Common-mode input voltage range CMRR > 60 dB, RS = 50 Ω

Full range0to

3.7

–0.3to

3.8

V

IOH = 1 3 mA25°C 4.9

VOH High level output voltage


VVOH High-level output voltage

IOH = 4 2 mA25°C 4.7

V


VIC = 2 5 V IOL = 1 3 mA25°C 0.1

VOL Low level output voltage


VVOL Low-level output voltage

VIC = 2 5 V IOL = 4 2 mA25°C 0.21

V


AVDLarge-signal differential voltage VIC = 2.5 V, RL = 10 kΩ, 25°C 20 450

V/mVAVDg g g

amplificationIC ,

VO = 1 V to 4 VL ,

Full range 13V/mV

ri(d) Differential input resistance 25°C 1012 Ω

ci(c) Common-mode input capacitance f = 10 kHz 25°C 8 pF

zo Closed-loop output impedance f = 100 kHz, AV = 10 25°C 20 Ω

CMRR Common mode rejection ratioVIC = 0 to 3.7 V, VO = 3.7 V, 25°C 60 96

dBCMRR Common-mode rejection ratio IC ,RS = 50 Ω

O ,Full range 60 93

dB

kSVRSupply voltage rejection ratio VDD = 2.7 V to 5 V, VIC = VDD/2, 25°C 70 89

dBkSVRy g j

(∆VDD /∆VIO)DD ,

No loadIC DD ,

Full range 70 84dB

IDD Supply current (per channel) VO = 1 5 V No load25°C 1 2

mAIDD Supply current (per channel) VO = 1.5 V, No loadFull range 2

mA

† Full range is 0°C to 70°C.





operating characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted)



UNIT

VO(PP) = 1 5 V CL = 100 pF25°C 5 10.5


CL = 100 pF,Full

range4.7 6

V/µs

V Equivalent input noise voltagef = 10 Hz 25°C 147

nV/√HzVn Equivalent input noise voltagef = 1 kHz 25°C 17

nV/√Hz

VN(PP)Peak-to-peak equivalent input noise f = 0.1 Hz to 1 Hz

25°C0.33

µVVN(PP)q

voltage f = 0.1 Hz to 10 Hz25°C

0.86µV

In Equivalent input noise current f = 100 Hz 25°C 0.2 pA/√Hz

R 600 ΩAV = 1 0.005%


AV = 10 25°C 0.016%f = 1 kHz

AV = 100 0.095%


RL = 600 Ω, 25°C 5.1 MHz

t Settling time

AV = –1,Step = 1.5 V to 3.5 V,

0.1% 25°C 0.134µsts Settling time ,

RL = 600 Ω,CL = 100 pF 0.01% 25°C 1.97

µs


25°C 46°


25°C 12 dB† Full range is 0°C to 70°C.




electrical characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted)



UNIT


V 0 V 0

25°C 0.36 2.5 0.36 1.6mVVIO Input offset voltage

V 0 V 0

Full range 0.4 2.7 0.4 1.9mV

αVIO

Temperature coefficient of input

V 0 V 0

25°Cto 2 2 µV/°CαVIO coefficient of input

offset voltageV 0 V 0

to125°C

2 2 µV/°C

VIC = 0,RS = 50 Ω

VO = 0,25°C 1 1


–40°C to85°C 2 100 2 100

pA

25°C 2 2

IIB Input bias current –40°C to85°C 6 100 6 100

pA

0 –0.3 0 –0.325°C

0to

0.3to

0to

0.3to

VICRCommon-mode

CMRR > 60 dB RS = 50 Ω3.7 3.8 3.7 3.8

VVICR input voltage rangeCMRR > 60 dB, RS = 50 Ω

0 –0.3 0 –0.3V

Full range0to

0.3to

0to

0.3tog

3.7 3.8 3.7 3.8

IOH = 1 3 mA25°C 4.9 4.9

VOHHigh-level output


VVOHg

voltageIOH = 4 2 mA

25°C 4.7 4.7V


VIC = 2 5 V IOL = 1 3 mA25°C 0.1 0.1

VOLLow-level output


VVOL voltageVIC = 2 5 V IOL = 4 2 mA

25°C 0.21 0.21V


AVD

Large-signal differential voltage

VIC = 2.5 V,R 10 kΩ

25°C 20 450 20 450V/mVAVD differential voltage

amplification

IC ,VO = 1 V to 4 V RL = 10 kΩ

Full range 13 13V/mV

ri(d)Differential inputresistance

25°C 1012 1012 Ω

ci(c)Common-mode input capacitance

f = 10 kHz, 25°C 8 8 pF

zoClosed-loopoutput impedance

f = 100 kHz, AV = 10 25°C 20 20 Ω

CMRRCommon-mode VIC = 0 to 3.7 V, VO = 3.7 V, 25°C 60 96 60 96

dBCMRRrejection ratio

IC ,RS = 50 Ω

O ,Full range 60 93 60 93

dB

kSVR

Supply voltage rejection ratio

VDD = 2.7 V to 5 V, VIC = VDD/2, 25°C 70 89 70 89dBkSVR rejection ratio

(∆VDD /∆VIO)

DD ,No load

IC DD ,

Full range 70 84 70 84dB

IDDSupply current

VO = 1 5 V No load25°C 1 2 1 2

mAIDDy

(per channel) VO = 1.5 V, No loadFull range 2 2

mA

† Full range is – 40°C to 125°C.





operating characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted)



UNIT

VO(PP) = 1 5 V CL = 100 pF25°C 5 10.5 5 10.5


CL = 100 pF,Full

range4.7 6 4.7 6

V/µs

VEquivalent input f = 10 Hz 25°C 147 147

nV/√HzVnq

noise voltage f = 1 kHz 25°C 17 17nV/√Hz

VN(PP)

Peak-to-peak equivalent input

f = 0.1 Hz to 1 Hz 25°C 0.33 0.33 µVVN(PP) equivalent input

noise voltage f = 0.1 Hz to 10 Hz 25°C 0.86 0.86 µV

InEquivalent inputnoise current

f = 100 Hz 25°C 0.2 0.2 pA/√Hz

T t l h i R 600 ΩAV = 1 0.005% 0.005%

THD + NTotal harmonicdistortion plus noise

RL = 600 Ω,f = 1 kHz

AV = 10 25°C 0.016% 0.016%distortion lus noise f = 1 kHz

AV = 100 0.095% 0.095%

Gain-bandwidth product

f = 10 kHz, CL = 100 pF

RL = 600 Ω, 25°C 5.1 5.1 MHz

t Settling time

AV = –1,Step = 1.5 V to

3 5 V

0.1% 25°C 0.134 0.134

µsts Settling time 3.5 V,RL = 600 Ω,CL = 100 pF

0.01% 25°C 1.97 1.97

µs

φmPhase margin atunity gain RL = 600 Ω, CL = 100 pF

25°C 46° 46°

Gain marginL , L

25°C 12 12 dB† Full range is –40°C to 125°C.




electrical characteristics at specified free-air temperature, V DD = 2.7 V, TA = 25°C (unless otherwisenoted)

PARAMETER TEST CONDITIONSTLV2772Y

UNITPARAMETER TEST CONDITIONSMIN TYP MAX

UNIT

VIO Input offset voltageV 0 V 0

0.44 mV

IIO Input offset currentVIC = 0,RS = 50 Ω

VO = 0,1 pA

IIB Input bias currentRS = 50 Ω

2 pA

VICR Common-mode input voltage range CMRR > 70 dB, RS = 50 Ω–0.3

to1.7

V

VOH High level output voltageIOH = –0.675 mA 2.6

VVOH High-level output voltageIOH = –2.2 mA 2.4

V

VOL Low level output voltageVIC = 1.35 V, IOL = 0.675 mA 0.1

VVOL Low-level output voltageVIC = 1.35 V, IOL = 2.2 mA 0.21

V

AVD Large-signal differential voltage amplificationVIC = 1.35 V,VO = 0.6 V to 2.1 V

RL = 10 kΩ, 380 V/mV

ri(d) Differential input resistance 1012 Ω

ci(c) Common-mode input capacitance f = 10 kHz 8 pF

zo Closed-loop output impedance f = 100 kHz, AV = 10 25 Ω

CMRR Common-mode rejection ratioVIC = 0 to 1.5 V,RS = 50 Ω

VO = 1.5 V, 84 dB

kSVR Supply voltage rejection ratio (∆VDD /∆VIO)VDD = 2.7 V to 5 V,No load

VIC = VDD/2,89 dB

IDD Supply current (per channel) VO = 1.5 V, No load 1 mA

operating characteristics at specified free-air temperature, V DD = 2.7 V, TA = 25°C (unless otherwisenoted)



UNIT


CL = 100 pF,9 V/µs

V Equivalent input noise voltagef = 10 Hz 147

nV/√HzVn Equivalent input noise voltagef = 1 kHz 21

nV/√Hz

VN(PP) Peak to peak equivalent input noise voltagef = 0.1 Hz to 1 Hz 0.33

µVVN(PP) Peak-to-peak equivalent input noise voltagef = 0.1 Hz to 10 Hz 0.86

µV

In Equivalent input noise current f = 100 Hz 1.5 pA/√Hz

R 600 ΩAV = 1 0.0085%


AV = 10 0.025%f = 1 kHz

AV = 100 0.12%


RL = 600 Ω, 4.8 MHz

t Settling time

AV = –1,Step = 0.85 V to 1.85 V,

0.1% 0.186µsts Settling time ,

RL = 600 Ω,CL = 100 pF 0.01% 3.92

µs


46°


12 dB





electrical characteristics at specified free-air temperature, V DD = 5 V, TA = 25°C (unless otherwisenoted)



UNIT

VIO Input offset voltageV 0 V 0

0.36 mV

IIO Input offset currentVIC = 0,RS = 50 Ω

VO = 0,1 pA

IIB Input bias currentRS = 50 Ω

2 pA

VICR Common-mode input voltage range CMRR > 60 dB, RS = 50 Ω–0.3

to3.8

V

VOH High level output voltageIOH = –1.3 mA 4.9

VVOH High-level output voltageIOH = –4.2 mA 4.7

V

VOL Low level output voltageVIC = 2.5 V, IOL = 1.3 mA 0.1

VVOL Low-level output voltageVIC = 2.5 V, IOL = 4.2 mA 0.21

V

AVD Large-signal differential voltage amplificationVIC = 2.5 V,VO = 1 V to 4 V

RL = 10 kΩ, 450 V/mV

ri(d) Differential input resistance 1012 Ω

ci(c) Common-mode input capacitance f = 10 kHz 8 pF

zo Closed-loop output impedance f = 100 kHz, AV = 10 20 Ω

CMRR Common-mode rejection ratioVIC = 0 to 3.7 V,RS = 50 Ω

VO = 3.7 V, 96 dB

kSVR Supply voltage rejection ratio (∆VDD /∆VIO)VDD = 2.7 V to 5 V,No load

VIC = VDD/2,89 dB

IDD Supply current (per channel) VO = 1.5 V, No load 1 mA

operating characteristics at specified free-air temperature, V DD = 5 V, TA = 25°C (unless otherwisenoted)



UNIT


CL = 100 pF,10.5 V/µs

V Equivalent input noise voltagef = 10 Hz 147

nV/√HzVn Equivalent input noise voltagef = 1 kHz 17

nV/√Hz

VN(PP) Peak to peak equivalent input noise voltagef = 0.1 Hz to 1 Hz 0.33

µVVN(PP) Peak-to-peak equivalent input noise voltagef = 0.1 Hz to 10 Hz 0.86

µV

In Equivalent input noise current f = 100 Hz 0.2 pA/√Hz

R 600 ΩAV = 1 0.005%


AV = 10 0.016%f = 1 kHz

AV = 100 0.095%


RL = 600 Ω, 5.1 MHz

t Settling time

AV = –1,Step = 1.5 V to 3.5 V,

0.1% 0.134µsts Settling time ,

RL = 600 Ω,CL = 100 pF 0.01% 1.97

µs


46°


12 dB




TYPICAL CHARACTERISTICS

Table of GraphsFIGURE

VIO Input offset voltageDistributionvs Common-mode input voltage

1,23,4

αVIO Temperature coefficient Distribution 5,6

IIB/IIO Input bias and input offset currents vs Free-air temperature 7

VOH High-level output voltage vs High-level output current 8,9

VOL Low-level output voltage vs Low-level output current 10,11

VO(PP) Maximum peak-to-peak output voltage vs Frequency 12,13

IOS Short-circuit output currentvs Supply voltagevs Free-air temperature

1415

VO Output voltage vs Differential input voltage 16

AVD Large-signal differential voltage amplification vs Frequency 17,18

AVD Differential voltage amplificationvs Load resistancevs Free-air temperature

1920,21

zo Output impedance vs Frequency 22,23

CMRR Common-mode rejection ratiovs Frequencyvs Free-air temperature

2425

kSVR Supply-voltage rejection ratio vs Frequency 26,27

IDD Supply current (per channel) vs Supply voltage 28

SR Slew ratevs Load capacitance 29

SR Slew ratevs Free-air temperature 30

VO Voltage-follower small-signal pulse response vs Time 31,32

VO Voltage-follower large-signal pulse response vs Time 33,34

VO Inverting small-signal pulse response vs Time 35,36

VO Inverting large-signal pulse response vs Time 37,38

Vn Equivalent input noise voltage vs Frequency 39,40

Noise voltage (referred to input) Over a 10-second period 41

THD + N Total harmonic distortion plus noise vs Frequency 42,43

Gain-bandwidth product vs Supply voltage 44

B1 Unity-gain bandwidth vs Load capacitance 45

φm Phase margin vs Load capacitance 46

Gain margin vs Load capacitance 47






Figure 1

–2.5

30

20

10

0–2 –1.5 –1 0 0.5

VIO – Input Offset Voltage – mV

–0.5

35

Per

cent

age

of A

mpl

ifier

s –

%

25

15

5

1

40VDD = 2.7 VRL = 10 kΩTA = 25°C

DISTRIBUTION OF TLV2772INPUT OFFSET VOLTAGE

1.5 2.52

Figure 2

–2.5

30

20

10

0–2 –1.5 –1 0 0.5

VIO – Input Offset Voltage – mV

–0.5

35

Per

cent

age

of A

mpl

ifier

s –

%

25

15

5

1

40VDD = 5 VRL = 10 kΩTA = 25°C


1.5 2.52

Figure 3

VDD = 2.7 VTA = 25°C

INPUT OFFSET VOLTAGEvs

COMMON-MODE INPUT VOLTAGE

2

1

0

–1

–2

1.5

0.5

–0.5

–1.5

–1 –0.5 0 0.5 2

VIC – Common-Mode Input Voltage – V

1.51 2.5 3

VIO

– In

put O

ffset

Vol

tage

– m

V

Figure 4

INPUT OFFSET VOLTAGEvs

COMMON-MODE INPUT VOLTAGE

1

0

–1

–2–1 0 0.5

VIC – Common-Mode Input Voltage – V

–0.5

1.5

0.5

–0.5

–1.5

1

2

1.5 2.52 3 3.5 4.54

VDD = 5 VTA = 25°C

VIO

– In

put O

ffset

Vol

tage

– m

V





Figure 5

αVIO – Temperature Coefficient – µV/°C–6

30

20

10

0–3 0 3 9 126

35

Per

cent

age

of A

mpl

ifier

s –

% 25

15

5

VDD = 2.7 VTA = 25°C to 125°C


Figure 6

–6

30

20

10

0–3 0 3 9 12

αVIO – Temperature Coefficient – µV/°C6

35

Per

cent

age

of A

mpl

ifier

s –

% 25

15

5

VDD = 5 VTA = 25°C to 125°C


Figure 7

VDD = 5 VVIC = 0VO = 0RS = 50 Ω

INPUT BIAS AND OFFSET CURRENTvs

FREE-AIR TEMPERATURE

0.20

0.10

0

0.15

0.05

–75 –50 –25 0 75

TA – Free-Air Temperature – °C5025 100 125

I IB

and

IIO

– In

put B

ias

and

Inpu

t Offs

et C

urre

nts

– nA

IIB

IIO

Figure 8

HIGH-LEVEL OUTPUT VOLTAGEvs

HIGH-LEVEL OUTPUT CURRENT

3

2

1

0

2.5

1.5

0.5

0 5 10 15

IOH – High-Level Output Current – mA

2520

VO

H–

Hig

h-Le

vel O

utpu

t Vol

tage

– V

VDD = 2.7 V

TA = 125°C

TA = –40°C

TA = 25°C

TA = 85°C






Figure 9

HIGH-LEVEL OUTPUT VOLTAGEvs

HIGH-LEVEL OUTPUT CURRENT

3

2

1

00 10 15

IOH – High-Level Output Current – mA

5

3.5

2.5

1.5

0.5

20

4

25 3530 40 45 5550

VDD = 5 VTA = 25°C

VO

H–

Hig

h-Le

vel O

utpu

t Vol

tage

– V

4.5

5

TA = –40°C

TA = 85°C

TA = 25°C

TA = 125°C

Figure 10

LOW-LEVEL OUTPUT VOLTAGEvs

LOW-LEVEL OUTPUT CURRENT

3

2

1

0

2.5

1.5

0.5

0 5 10 15

IOL – Low-Level Output Current – mA

3020

VO

L–

Low

-Lev

el O

utpu

t Vol

tage

– V

VDD = 2.7 V

TA = 125°C

25

TA = 85°C

TA = 25°C

TA = –40°C

Figure 11

2

1

00 10

IOL – Low-Level Output Current – mA

2.5

1.5

0.5

20

3

30 40 50

VDD = 5 V

LOW-LEVEL OUTPUT VOLTAGEvs

LOW-LEVEL OUTPUT CURRENT

TA = 125°C

TA = 85°C

TA = –40°C

TA = 25°C

VO

L–

Low

-Lev

el O

utpu

t Vol

tage

– V

Figure 12

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGEvs

FREQUENCY

3

1

01000

f – Frequency – kHz

5

10000100

4

RL = 10 kΩ

VO

(PP

)–

Max

imum

Pea

k-to

-Pea

k O

utpu

t Vol

tage

– V

2

VDD = 5 V1% THD

VDD = 2.7 V2% THD





Figure 13

THD = 5%RL = 600 ΩTA = 25°C

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGEvs

FREQUENCY

3

2

1

0

2.5

1.5

0.5

100

f – Frequency – kHz

1000 10000

VDD = 5 V

VDD = 2.7 V

5

4

4.5

3.5

– M

axim

um P

eak-

to-P

eak

Out

put V

olta

ge –

VV O

(PP

)

Figure 14

SHORT-CIRCUIT OUTPUT CURRENTvs

SUPPLY VOLTAGE

30

0

–30

–602 4 5

VDD – Supply Voltage – V

3

45

15

–15

–45

6

60

7

VO = VDD /2VIC = VDD /2TA = 25°C

I OS

– S

hort

-Circ

uit O

utpu

t Cur

rent

– m

A VID = –100 mV

VID = 100 mV

Figure 15

VDD = 5 VVO = 2.5 V

SHORT-CIRCUIT OUTPUT CURRENTvs


60

20

–20

–60

40

0

–40

–75 –50 –25 0 75

TA – Free-Air Temperature – °C5025 100 125

I OS

– S

hort

-Circ

uit O

utpu

t Cur

rent

– m

A VID = –100 mV

VID = 100 mV

Figure 16

RL = 600 ΩTA = 25°C

OUTPUT VOLTAGEvs

DIFFERENTIAL INPUT VOLTAGE

4

2

0

5

3

1

–1000 –750 –500 –250 500

VID – Differential Input Voltage – µV

2500 750 1000

VO

– O

utpu

t Vol

tage

– V

VDD = 2.7 V

VDD = 5 V






100

60

20

–20

80

40

0

100

f – Frequency – Hz

10k 10M

AVD

Phase

LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATIONAND PHASE MARGIN

vsFREQUENCY

– La

rge-

Sig

nal D

iffer

entia

l Am

plifi

catio

n –

dBA

VD

mφ

– P

hase

Mar

gin

– de

gree

s

300

180

60

–60

240

120

0

1k 100k 1M–40 –90

VDD = 2.7 VRL = 600 ΩCL = 600 pFTA = 25°C

Figure 17

300

180

60

–60

240

120

0

–90

100

60

20

–20

80

40

0

–40100


10k 10M

AVD

Phase

VDD = 5 VRL = 600 ΩCL = 600 pFTA = 25°C

LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATIONAND PHASE MARGIN

vsFREQUENCY

– La

rge-

Sig

nal D

iffer

entia

l Am

plifi

catio

n –

dBA

VD

mφ

– P

hase

Mar

gin

– de

gree

s

1k 100k 1M

Figure 18





Figure 19

DIFFERENTIAL VOLTAGE AMPLIFICATIONvs

LOAD RESISTANCE

200

100

010

RL – Load Resistance – k Ω

250

150

50

1 100 10000.1

TA = 25°C

– D

iffer

entia

l Vol

tage

Am

plifi

catio

n –

V/m

VA

VD

VDD = ±1.35 VVDD = ±2.5 V

Figure 20


FREE-AIR TEMPERATURE1000

10

0.1

100

1

– D

iffer

entia

l Vol

tage

Am

plifi

catio

n –

V/m

VA

VD

TA – Free-Air Temperature – °C

–75 –50 –25 0 755025 100 125

VDD = 2.7 VVIC = 1.35 VVO = 0.6 V to 2.1 V

RL = 1 MΩ

RL = 600 Ω

RL = 10 kΩ

Figure 21

–50



10

0.1

100

1

– D

iffer

entia

l Vol

tage

Am

plifi

catio

n –

V/m

VA

VD


VDD = 5 VVIC = 2.5 VVO = 1 V to 4 V

RL = 1 MΩ

RL = 600 Ω

–75 –25 0 755025 100 125

RL = 10 kΩ

Figure 22

OUTPUT IMPEDANCEvs

FREQUENCY100

1

0.01

10

0.10

100 1k 10k 100k


1M

ZO

– O

utpu

t Im

peda

nce

–

AV = 100

AV = 10

AV = 1

VDD = ±1.35 VTA = 25°C

Ω






Figure 23

OUTPUT IMPEDANCEvs

FREQUENCY100

1

0.01

10

0.1


100 1k 10k 100k 1M

VDD = ±2.5 VTA = 25°C

Av = 100

– O

utpu

t Im

peda

nce

–Z

oΩ

Av = 10

Av = 1

Figure 24

VIC = 1.35 Vand 2.5 VTA = 25°C

COMMON-MODE REJECTION RATIOvs

FREQUENCY

90

80

60

40

70

50

10 100 1k


10k 100k 10M

VDD = 5 V

VDD = 2.7 V

CM

RR

– C

omm

on-M

ode

Rej

ectio

n R

atio

– d

B1M

Figure 25

–20–40 0 20 806040 100 120

COMMON-MODE REJECTION RATIOvs


110

100

90

80

105

95

85


CM

RR

– C

omm

on-M

ode

Rej

ectio

n R

atio

– d

B

120

115

VDD = 5 V

VDD = 2.7 V

140

Figure 26

SUPPLY-VOLTAGE REJECTION RATIOvs

FREQUENCY120

60

010 100 1k 10k


10M

kS

VR

– S

uppl

y-V

olta

ge R

ejec

tion

Rat

io –

dB

kSVR–

VDD = ±1.35 VTA = 25°C

100k 1M

kSVR+100

40

80

20





Figure 27

SUPPLY VOLTAGE REJECTION RATIOvs

FREQUENCY120

80

40

0

100

60

20

10 100 1 k 10 k 10 M


1 M100 k

kS

VR

– S

uppl

y V

olta

ge R

ejec

tion

Rat

io –

dB kSVR+

kSVR–

VDD = ±2.5 VTA = 25°C

Figure 28

SUPPLY CURRENT (PER CHANNEL)vs

SUPPLY VOLTAGE

1.2

0.8

0.4

0

1

0.6

0.2

2.5 3 3.5 4

VDD – Supply Voltage – V

74.5

I DD

– S

uppl

y C

urre

nt (

Per

Cha

nnel

) –

mA

TA = 0°C

1.6

1.4

5 5.5 6 6.5

TA = 125°C

TA = 85°C

TA = 25°C

TA = –40°C

Figure 29

SLEW RATEvs

LOAD CAPACITANCE

1k

CL – Load Capacitance – pF

100 10k 100k10

VDD = 5 VAV = –1TA = 25°C

SR+

12

8

4

0

10

6

2

16

14

SR

– S

lew

Rat

e –

V/

µs

SR–

Figure 30

–50–75 –25 0 755025 100 125

SLEW RATEvs


12

10

8

13

11

9


VDD = 2.7 VRL = 10 kΩCL = 100 pFAV = 1

SR

– S

lew

Rat

e –

µs






Figure 31

t – Time – ns

VOLTAGE-FOLLOWERSMALL-SIGNAL PULSE RESPONSE

VDD = 2.7 VRL = 600 ΩCL = 100 pF

AV = 1TA = 25°C

40

0

20

–20VO

– O

utpu

t Vol

tage

– m

V

80

60

0 1.5k1k500 2k 2.5k 3.5k3k 4k 4.5k 5k

100

–40

–60

Figure 32t – Time – ns

VDD = 5 VRL = 600 ΩCL = 100 pF

AV = 1TA = 25°C

VOLTAGE-FOLLOWERSMALL-SIGNAL PULSE RESPONSE

40

0

20

–20VO

– O

utpu

t Vol

tage

– m

V

80

60

0 1.5k1k500 2k 2.5k 3.5k3k 4k 4.5k 5k

100

–40

–60

Figure 33

t – Time – ns

VOLTAGE-FOLLOWERLARGE-SIGNAL PULSE RESPONSE

VDD = 2.7 VRL = 600 ΩCL = 100 pF

AV = 1TA = 25°C

1.5

0.5

1

0VO

– O

utpu

t Vol

tage

– V

2.5

2

0 1.5k1k500 2k 2.5k 3.5k3k 4k 4.5k 5k

3

–0.5

–1


VDD = 5 VRL = 600 ΩCL = 100 pF

AV = 1TA = 25°C

VOLTAGE-FOLLOWERLARGE-SIGNAL PULSE RESPONSE

3

1

2

0VO

– O

utpu

t Vol

tage

– V

5

4

0 1.5k1k500 2k 2.5k 3.5k3k 4k 4.5k 5k

6

–1

–2





Figure 35

t – Time – ns

VDD = 2.7 VRL = 600 ΩCL = 100 pF

AV = –1TA = 25°C

INVERTING SMALL-SIGNALPULSE RESPONSE

40

0

20

–20VO

– O

utpu

t Vol

tage

– m

V

80

60

0 1.5k1k500 2k 2.5k 3.5k3k 4k 4.5k 5k

100

–40

–60


VDD = 5 VRL = 600 ΩCL = 100 pF

AV = –1TA = 25°C

INVERTING SMALL-SIGNALPULSE RESPONSE

40

0

20

–20VO

– O

utpu

t Vol

tage

– m

V

80

60

0 1.5k1k500 2k 2.5k 3.5k3k 4k 4.5k 5k

100

–40

–60

Figure 37

t – Time – ns

VDD = 2.7 VRL = 600 ΩCL = 100 pF

AV = –1TA = 25°C

INVERTING LARGE-SIGNALPULSE RESPONSE

1.5

0.5

1

0VO

– O

utpu

t Vol

tage

– m

V

2.5

2

0 1.5k1k500 2k 2.5k 3.5k3k 4k 4.5k 5k

3

–0.5

–1


VDD = 5 VRL = 600 ΩCL = 100 pF

AV = –1TA = 25°C

INVERTING LARGE-SIGNALPULSE RESPONSE

2.5

1.5

2

1VO

– O

utpu

t Vol

tage

– m

V

3.5

3

0 1.5k1k500 2k 2.5k 3.5k3k 4k 4.5k 5k

4

0.5

1






Figure 39

EQUIVALENT INPUT NOISE VOLTAGEvs

FREQUENCY

120

80

40

0100 10k


140

100

60

20

1k

160

10

VDD = 2.7 VRS = 20 ΩTA = 25°C

– In

put N

oise

Vol

tage

–V

nnV

/H

z

Figure 40

EQUIVALENT INPUT NOISE VOLTAGEvs

FREQUENCY

100


1k 10k10

VDD = 5 VRS = 20 ΩTA = 25°C120

80

40

0

100

60

20

140

– In

put N

oise

Vol

tage

–nV

Hz

Vn

t – Time – s

VDD = 5 Vf = 0.1 Hz to 10 HzTA = 25°C

NOISE VOLTAGEOVER A 10 SECOND PERIOD

0 1 2 3 4 5 6 7 8 9 10

Noi

se V

olta

ge –

nV

300

100

–100

–300

200

GND

–200

Figure 41





Figure 42

TOTAL HARMONIC DISTORTION PLUS NOISEvs

FREQUENCY10

0.1

0.001

1

0.01


10 100 1k 10k 100k

VDD = 2.7 VRL = 600 ΩTA = 25°C

TH

D+N

– T

otal

Har

mon

ic D

isto

rtio

n P

lus

Noi

se –

%

Av = 100

Av = 10

Av = 1

Figure 43

10

0.1

0.001

1

0.01


10 100 1k 10k 100k

VDD = 5 VRL = 600 ΩTA = 25°C

TH

D+N

– T

otal

Har

mon

ic D

isto

rtio

n P

lus

Noi

se –

%

Av = 100

Av = 10

Av = 1

TOTAL HARMONIC DISTORTION PLUS NOISEvs

FREQUENCY

Figure 44

GAIN-BANDWIDTH PRODUCTvs

SUPPLY VOLTAGE

5.2

4.8

4.4

4

5

4.6

4.2

2 2.5 3 3.5 5

VDD+ – Supply Voltage – V

4.54 5.5 6

Gai

n-B

andw

idth

Pro

duct

– M

Hz

RL = 600 ΩCL = 100 pFFreq = 10 kHzTA = 25°C

Figure 45

UNITY-GAIN BANDWIDTHvs

LOAD CAPACITANCE

4

2

01k


5

3

1

100 10k 100k10

Uni

ty-G

ain

Ban

dwid

th –

MH

z

Rnull = 0

Rnull = 20

Rnull = 50

Rnull = 100

VDD = 5 VRL = 600 ΩTA = 25°C






Figure 46

60

40

20

0

50

30

10

10


1k

VDD = 5 VRL = 600 ΩTA = 25°C

mφ

– P

hase

Mar

gin

– de

gree

s

100 10k 100K

PHASE MARGINvs

LOAD CAPACITANCE90

70

80

Rnull = 0

Rnull = 20 Ω

Rnull = 50 Ω

Rnull = 100 Ω

Figure 47

15

25

35

40

20

30

10


1k

VDD = 5 VRL = 600 ΩTA = 25°C

Gai

n M

argi

n –

dB

100 10k 100K

GAIN MARGINvs

LOAD CAPACITANCE0

10

5

Rnull = 0

Rnull = 20 Ω

Rnull = 50 Ω

Rnull = 100 Ω




APPLICATION INFORMATIONmacromodel information

Macromodel information provided was derived using Microsim Parts Release 8, the model generationsoftware used with Microsim PSpice . The Boyle macromodel (see Note 4) and subcircuit in Figure 48 aregenerated using the TLV2772 typical electrical and operating characteristics at TA = 25°C. Using thisinformation, output simulations of the following key parameters can be generated to a tolerance of 20% (in mostcases):

Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification

Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit

NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”, IEEEJournal of Solid-State Circuits, SC-9, 353 (1974).

+

–

+

–

+

–

+

– +

–

.SUBCKT TLV2772–X 1 2 3 4 5C1 11 12 2.3094E–12C2 6 7 8.0000E–12CSS 10 99 2.1042E–12DC 5 53 DYDE 54 5 DYDLP 90 91 DXDLN 92 90 DXDP 4 3 DXEGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5FB 7 99 POLY (5) VB VC VE VLP+ VLN 0 19.391E6 –1E3 1E3 19E6 –19E6GA 6 0 11 12 150.80E–6GCM 0 6 10 99 7.5576E–9ISS 3 10 DC 116.40E–6HLIM 90 0 VLIM 1KJ1 11 2 10 JX1J2 12 1 10 JX2R2 6 9 100.00E3

RD1 4 11 6.6315E3RD2 4 12 6.6315E3R01 8 5 17.140R02 7 99 17.140RP 3 4 4.5455E3RSS 10 99 1.7182E6VB 9 0 DC 0VC 3 53 DC .1VE 54 4 DC .1VLIM 7 8 DC 0VLP 91 0 DC 47VLN 0 92 DC 47.MODEL DX D (IS=800.0E–18).MODEL DY D (IS=800.0E–18 Rs = 1m Cjo=10p).MODEL JX1 PJF (IS=2.2500E–12 BETA=195.36E–6+ VTO=–1).MODEL JX2 PJF (IS=1.7500E–12 BETA=195.36E–6+ VTO=–1).ENDS

VDD+

RP

IN –2

IN+1

VDD–

RD1

11

J1 J2

10

RSSISS

3

12

RD2DP

VD

DC

4

C1

53

EGNDFB

HLIM

90

DLP

91

DLN

92

VLNVLP

99

CSS

+

–VE

DE

54

OUT

+

–+

–

R2 6

9

VB

C2

GA

VLIM

8

5

RO1

RO2

7

GCM

Figure 48. Boyle Macromodel and Subcircuit

PSpice and Parts are trademarks of MicroSim Corporation.





MECHANICAL INFORMATIOND (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE14 PIN SHOWN

4040047/D 10/96

0.228 (5,80)0.244 (6,20)

0.069 (1,75) MAX0.010 (0,25)0.004 (0,10)

1

14

0.014 (0,35)0.020 (0,51)

A

0.157 (4,00)0.150 (3,81)

7

8

0.044 (1,12)0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189(4,80)

(5,00)0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394(10,00)

0.386

0.004 (0,10)

M0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).D. Falls within JEDEC MS-012




MECHANICAL INFORMATIONDGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE

0,690,41

0,25

0,15 NOM

Gage Plane

4073329/A 02/97

4,98

0,25

5

3,054,782,95

8

4

3,052,95

1

0,38

1,07 MAX 0,05 MIN

Seating Plane

0,65 M0,25

0°–6°

0,10

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion.





MECHANICAL INFORMATIONP (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE

4040082/B 03/95

0.310 (7,87)0.290 (7,37)

0.010 (0,25) NOM

0.400 (10,60)0.355 (9,02)

58

41

0.020 (0,51) MIN

0.070 (1,78) MAX

0.240 (6,10)0.260 (6,60)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.015 (0,38)0.021 (0,53)

Seating Plane

M0.010 (0,25)

0.100 (2,54) 0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. Falls within JEDEC MS-001

IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductorproduct or service without notice, and advises its customers to obtain the latest version of relevant informationto verify, before placing orders, that the information being relied on is current.

TI warrants performance of its semiconductor products and related software to the specifications applicable atthe time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques areutilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of eachdevice is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, orsevere property or environmental damage (“Critical Applications”).

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTEDTO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHERCRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TIproducts in such applications requires the written approval of an appropriate TI officer. Questions concerningpotential risk applications should be directed to TI through a local SC sales office.

In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards should be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance, customer product design, software performance, orinfringement of patents or services described herein. Nor does TI warrant or represent that any license, eitherexpress or implied, is granted under any patent right, copyright, mask work right, or other intellectual propertyright of TI covering or relating to any combination, machine, or process in which such semiconductor productsor services might be or are used.

Copyright 1998, Texas Instruments Incorporated

This datasheet has been downloaded from:

www.DatasheetCatalog.com

Datasheets for electronic components.

http://www.datasheetcatalog.com

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