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  • EE 311 Notes/Prof. Saraswat Handout # 3

    Thin Dielectrics for MOS GateMOS gate oxides thickness in logic, dynamic memory and non-volatile memory has been scaledto enhance the performance

    ID Charge x velocity Cox (VGS - VT) x velocity Cox (VGS - VT) x velocity

    ID

    Cox Koxxo xL

    . (Ref: S. Asai, Microelectronics Engg., Sept. 1996)

    Within the next few years gate dielectric thickness will be scaled to below 20 This is approaching the fundamental limit for proper circuit operation. Supply voltage has not scaled proportionately according to the classical scaling theory.

    Degradation and breakdown is caused due to electrical stress. Therefore lifetime and reliabilityof such ultrathin dielectric films may be a show stopper in the evolution of the currenttechnology.

  • EE 311 Notes/Prof. Saraswat Handout # 3

    2

    Defects andnonuniformity of filmDielectric breakdown

    Reliability due tocharge injection

    Si substrate

    Polysilicon gate electrode

    Dopantpenetration

    gate oxide

    Leakage current

    Leakage- Circuit stability issues- Power dissipation

    0.00001

    0.001

    0.1

    10

    1000

    1801301007050

    Technology Generation (nm)

    Cu

    rren

    t (

    A/

    m)

    Igate

    Ioff

    Ion

    Source G. Bersuker, et al. Sematech

    Source: Sematech

  • EE 311 Notes/Prof. Saraswat Handout # 3

    3

    (Ref: Gupta, et al., IEEE Electron Dev. Lett. Dec. 1997)

    Dopant diffusion from gate poly-Si into the channel can cause VT shift. The problem is more seriousfor p+ poly-Si, i.e., boron diffusion.

    Performance degradation due to tox(electrical) > tox(physical) Carrier quantization in the channel due to quantum confinement.

    Conduction Band

    Depth Under Gate Oxide

    Ele

    ctro

    n e

    ner

    gy

    Carrier Concentration - Classical

    Carrier Concentration - Quantum Mechanical

    Energy Band Split

  • EE 311 Notes/Prof. Saraswat Handout # 3

    4

    0.00E+00

    5.00E+19

    1.00E+20

    1.50E+20

    2.00E+20

    0 1 2 3 4 5

    Depth (nm)

    Ele

    ctro

    n C

    once

    ntra

    tion

    (/c

    m3 )

    Quantum mechanical

    Classical

    2.5 nm gate oxide.

    Classical

    Quantum mechanical

    Electron concentration as a function of the distance from the Si/SiO2 interface as predicted bythe-classical model and by a Q-M model for a MOS structure. (Ref. T.-Y. Oh PhD thsis, Stanford

    Univ. 2004))

    Carrier depletion in poly-Si gate. This occurs because of high E - field due to acombination of higher supply voltage and thinner gate oxide.

    tox(electrical)

    tox(physical)

    Gate depletion

    Oxide

    Substrate

    Combined effect of depletion and quantization is to increase effective tox and thus reduce Cox

  • EE 311 Notes/Prof. Saraswat Handout # 3

    5

    Carrier quantization in the channel Carrier depletion in poly-Si gate

    (Buchanan and Lo, Proc. ECS Vol. PV 96-1, 1996)

    A reduced Cox implies reduction in gm.

    Fig. Threshold voltage shift(=Vth QM -Vth Classical) with different substrate dopingconcentration and oxide thickness. (Ref. T.-Y. Oh PhD thsis, Stanford Univ. 2004)

  • EE 311 Notes/Prof. Saraswat Handout # 3

    6

    Fig. Transconductance calculation result using QM and classical methods with various oxidethicknesses. Substrate doping is p-type 5e17cm3. (Ref. T.-Y. Oh PhD thsis, Stanford Univ. 2004)

    Note that care should be taken in interpreting the C-V measurements of ultrathindielectrics because of increased leakage current through the dielectric which representsa resistive component in the equivalent circuit.

    Techniques to Form MOS Gate Dielectric

    Thermal oxidation in a Furnace

    (or H20)Si + O2 = SiO2

    Si + 2H2O = SiO2 + 2H2 Inexpensive Excellent temperature uniformity good thickness uniformity High thermal mass long process times good for thicker oxides Not good for growing ultrathin gate oxides.

  • EE 311 Notes/Prof. Saraswat Handout # 3

    7

    Lamp Heated Rapid Thermal Oxidation

    Chamber

    WaferQuartz Window

    AcousticThermometer

    ControlSystem

    Gas In

    Gasout

    Shroud

    Low thermal mass short process times. Ideal for growing ultrathin gate oxides. Multiprocessing ideal for nitrided oxides. Rapid thermal CVD of ultrathin Si3N4

    Plasma CVD System

    RF

    Plasma

    ~

    Chuck

    Low temperature (

  • EE 311 Notes/Prof. Saraswat Handout # 3

    8

    Atomic layer CVD (ALCVD)

    In this method the deposition is done layer by layer. ALCVD reaction sequence is shown below.The reaction precursors are adsorbed one monolayer at a time and then energy for reaction issupplied by heat, light or plasma. This sequence is repeated till the desired thickness is achieved.Since the deposition is done one one monolayer at a time, thickness control is very precise.Therefore this technique is ideal for ultrathin film deposition.

    1) ZrCl4(g)

    2) ZrCl4(ad)

    3) ZrCl4(ad) + 2H2O (g) ZrO2 (ad) + 4HCl (g)

    4) ZrO2(ad)

    Being investigated for high-k dielectrics like ZrO2, HfO2

    Schematic of ALCVD equipment

    Wafer

    Heated Pedestal (>400oC)

    Showerhead

    Gas input

  • EE 311 Notes/Prof. Saraswat Handout # 3

    9

    Microstructure of SiO2

    The primary structural unit of all solid forms of SiO2 is the SiO4 tetrahedron. The localtetrahedral atomic order, with bond angle of 109 between O - Si - O, is maintained in all formsof SiO2 whether it be crystalline, vitreous, or amorphous. Amorphous SiO2 (which is of greaterinterest here) still shows the local tetrahedral coordination. The linking of these tetrahedra toform the solid is achieved through the bonding which occurs at the corners of the tetrahedra. Thebonding angle between the Si-O-Si atoms, at the corners of adjacent tetrahedra, is also shown inthe figure below. This ever changing bond angle (generally varies from 120 to 180) produces acontinuous random network model for amorphous SiO2.

    This microstructure gives rise to a band structure with a large band gap of about 9 eV.

    Fig. Ref: J.W.McPherson and H.C. Mogul, IRPS April 1998

    crystalline quartz

    (b) amorphous SiO2

  • EE 311 Notes/Prof. Saraswat Handout # 3

    10

    Conduction in DielectricsAs device technology is improved, device dimensions have been reduced dramatically. A fewyears ago a potential of 5V was applied across 500 oxides in CMOS applications. Today weuse 3.3V drop across 40 oxides. So the oxide electric field has been increasing with time. Witha high field on thin oxides, the thin oxides will no longer be perfect insulators. Quantummechanical tunneling of carriers through gate oxide can occur. There are two types of tunneling,as shown in the figure below.

    n+ polye

    sub

    Voxb

    (a)

    n+ polye

    sub

    Vox

    (b)

    b

    The energy band diagrams for (a) Fowler-Nordheim tunneling (b) direct tunneling.

    1. Fowler-Nordheim Tunneling

    Under the influence of an electric field band bending occurs resulting in apparent thinning of thebarrier. Electrons and even holes can tunnel through the barrier and reach the conduction and thevalance band of the oxide, respectively. This is called Fowler-Nordheim (F-N) tunneling, firstproposed by Fowler and Nordheim, where the electrons are injected by tunneling into theconduction band of the oxide through a triangular energy barrier. The Wentzel-Kramers-Brillouin (WKB) approximation is usually applied for this calculation with the final result shownin the following expression:

    J = AEox2 e

    BEox

    where

    A = q3m

    8hmoxb, B =

    8 2mox b32

    3hq, e is the electron charge, h is the Planck's constant,

    b is the barrier height at the interface of the injecting electrode and the oxide, m is the mass ofelectron in vacuum, mox is the average electron mass in the oxide and has been calculated to bein the range of about 0.5m.

  • EE 311 Notes/Prof. Saraswat Handout # 3

    11

    The above equation is for the ideal case where T= 0K. If the temperature is taken intoaccount, then A will be changed to the following equation:

    A = q3

    8hmox* b

    ckT

    sin(ckT )

    where C =

    2 2mox bhqEox

    .

    2. Direct TunnelingThe second type of tunneling is called direct tunneling with a trapezoidal barrier as shown infigure above. It happens in very thin gate oxides and requires only a low electric field. Usually,direct tunneling current dominates when the oxide thickness is less than 40. As the oxidethickness is reduced the tunneling current increases exponentially. Below 30 the current isexcessive for reliable circuit operation.The relationship describing the tunneling current is

    J = AEox2 exp

    B 1 (1 Voxb)32

    Eox

    3. Trap Assisted Tunneling

    Even at fairly low fields gate leakage is observed in MOS devices. This can be attributed totunneling assisted by the traps in the bulk of the dielectric. Trap assisted tunneling can take placeat very low electric fields. If the density of traps is increased the leakage will also increase.Electrical stress can increase the number of these traps. The associated leakage is known asstress induced leakage current (SILC).

    Traps Traps

  • EE 311 Notes/Prof. Saraswat Handout # 3

    12

    Trap assisted tunneling resulting in leakage

    I-V Characteristics of a thin film of SiO2

    Examples of Problems Caused by Conduction and Trapping in SiO2

    Hot Carrier EffectsFrom our p-n junction discussion we remember that the maximum electric field intensity is nearthe junction itse