The MOS Transistor - ??MOS Transistor –saturated Gate Silicon Substrate Field...

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Transcript of The MOS Transistor - ??MOS Transistor –saturated Gate Silicon Substrate Field...

  • The MOS Transistor

    Prof. MacDonald

    1

  • MOS Capacitor

    Si Wafer P type

    poly silicon or metal gate

    gate oxide

    Vg

    Vb

    2

  • MOS Capacitor Fermi level review

    qEE if

    F

    =

    a

    iFp

    Nn

    qkt ln=

    i

    dFn

    nN

    qkt ln=

    Ec

    Ev

    Ei Efp

    3

  • Energy Band Diagrams Separate

    Metal Oxide Semiconductor

    Eo

    Efm Ec

    Ev

    Ec

    Ev

    Ei Efp

    q = 4.15ev qm = 4.1eV q oxide = 0.95eV

    4

  • Energy Band Diagrams contacted

    Metal Oxide Semiconductor

    Surface potential is smaller than bulk potential. Meaning that near the oxide the silicon is almost intrinsic less carriers. 5

  • Energy Band Diagrams contacted

    Metal Oxide Semiconductor

    A built-in voltage drop exists because of differences in metal/silicon work function. Known as flat band voltage 6

  • MOS Capacitor flat band voltage

    Si Wafer P type

    poly silicon or metal gate

    gate oxide

    Vg = qm q = -0.8V

    Vb = gnd = 0v

    7

  • Energy Band Diagrams Under Bias flat band

    Metal Oxide Semiconductor

    Surface potential is identical to bulk because of negative applied voltage. Same number of carriers across silicon now.

    8

  • MOS Capacitor Accumulation

    Si Wafer P type

    poly silicon or metal gate

    gate oxide

    Vg < qm q = -0.8V

    Vb = gnd = 0v

    Eox ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    9

  • Energy Band Diagrams Under Bias accumulation

    Metal Oxide Semiconductor

    Surface potential even more P type than bulk. More carriers (holes) available at surface near oxide.

    flat band voltage

    applied voltage

    10

  • MOS Capacitor Depletion

    Si Wafer P type

    poly silicon or metal gate

    gate oxide

    Vg > 0 V

    Vb = gnd = 0v

    Eox

    depletion region

    11

  • Energy Band Diagrams depletion

    Metal Oxide Semiconductor

    Surface depleted. Holes are pushed away from surface leaving negatively charged fixed ions. No mobile carriers in depletion region.

    small positive applied voltage

    12

  • MOS Capacitor Inversion

    Si Wafer P type

    poly silicon or metal gate

    gate oxide

    Vg >> 0 V

    Vb = gnd = 0v

    Eox

    depletion region - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    As voltage increases, inversion occurs and electrons gather near the surface. This sheet of electrons shields further depletion, so depletion width (xd) remains constant. Surface becomes N type. 13

  • Energy Band Diagrams inversion

    Metal Oxide Semiconductor

    When surface is as N type as bulk is P type, we have inversion. Ultra thin layer of electrons, free to transport charge.

    small positive applied voltage

    14

  • MOS Capacitor depletion depth

    Si Wafer P type

    poly silicon or metal gate

    gate oxide

    Vg >> 0 V

    Vb = gnd = 0v

    Eox

    depletion region - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    Depletion distance is important when calculating MOS threshold voltages later.

    Xd =

    a

    fssi

    Nq 2

    15

  • MOS Capacitor depletion charge

    Si Wafer P type

    poly silicon or metal gate

    gate oxide

    Vg >> 0 V

    Vb = gnd = 0v

    Eox

    depletion region - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    With depletion depth and dopant concentration we can calculate Q.

    Xd =

    fssiNaqQ = 216

  • MOS Transistor

    Gate

    Silicon Substrate

    Source Field Oxide

    Drain Field Oxide

    gate terminal

    drain terminal source terminal

    substrate terminal typically tied to ground for PWELLs and Vdd for NWELLs 17

  • MOS Transistor

    Gate

    Silicon Substrate

    Source Field Oxide

    Drain Field Oxide

    gate terminal

    drain terminal source terminal

    substrate terminal

    Device is symmetrical for NFET drain is defined as node with highest value. With zero bias on Gate, channel is P type and thus two back-back diodes. No conduction between source and drain.

    N+ N+ P

    18

  • MOS Transistor

    Gate

    Silicon Substrate

    Source Field Oxide

    Drain Field Oxide

    gate terminal

    drain terminal source terminal

    substrate terminal

    If gate voltage is raised to Vth a N type channel is formed below the gate. This effectively shorts out the back-to-back diodes and allows conduction.

    N+ N+

    P Depletion Region Inversion Layer

    19

  • Threshold Voltage

    Metal Oxide Semiconductor

    When surface is as N type as bulk is P type, we have inversion. The applied voltage is called the threshold voltage Vth .

    qVt

    20

  • Threshold Voltage

    l Four components of the Vt work function difference (flat band voltage)

    l -0.8 V for aluminum gate to P type silicon gate voltage component to change surface potential gate voltage component to offset depletion charge gate voltage component to offset fixed charge

    ox

    ox

    ox

    bFgct

    CQ

    CQ

    V =02

    21

  • Threshold Voltage with substrate bias

    l Source to Substrate bias affects Vt l Referred to as the body effect l used in the early eighties to raise Vt in NMOS l now subject of research in variable threshold devices l gamma is the body effect coefficient l affects performance of stacked transistors (more later)

    Vt =Vt0 + 2f +Vsb 2 f( )

    ox

    sia

    CNq

    =2

    22

    Make sure to get the subscript correct for the body to source voltage. The book uses one polarity and IBM used another so I can use either Just saying. Sorry.

    Interview question

  • MOSFET operation - qualitative

    l over-simplified view of MOSFET behavior l Useful for back-of-the-envelope calculations l Three main modes of operation

    Off Linear Saturation

    l Ignores short channel effects of new small geometries

    23

  • MOS Transistor - off

    Gate

    Silicon Substrate

    Source Field Oxide

    Drain Field Oxide

    gate terminal = Vg

    drain terminal Vd source terminal Vs = 0

    substrate terminal Vb = 0

    N+ N+

    P

    if Vgs < Vt, then no inversion layer exists and back-to-back diodes prevent conduction between drain and source regardless of Vds 24

  • MOS Transistor Linear mode

    Gate

    Silicon Substrate

    Source Field Oxide

    Drain Field Oxide

    gate terminal = Vg > Vt

    drain terminal Vd = small source terminal Vs = 0

    substrate terminal Vb = 0

    N+ N+

    P

    if Vgs > Vt and Vds remains small, then inversion layer beneath gate is almost uniform and complete from source to drain. Channel acts as a resistor and Ids increases linearly with Vds. 25

  • MOS Transistor Almost saturated

    Gate

    Silicon Substrate

    Source Field Oxide

    Drain Field Oxide

    gate terminal = Vg > Vt

    drain terminal Vd = Vgs-Vt source terminal Vs = 0

    substrate terminal Vb = 0

    N+ N+

    P

    if Vds = Vgs Vt, the inversion layer begins to disappear at the drain end of the channel. This is the transition point from linear mode to saturation mode. 26

  • MOS Transistor saturated

    Gate

    Silicon Substrate

    Source Field Oxide

    Drain Field Oxide

    gate terminal = Vg > Vt

    drain terminal Vd > Vgs-Vt source terminal Vs = 0

    substrate terminal Vb = 0

    N+ N+

    P

    if Vds > Vgs Vt, the inversion layer disappears near drain. The end of the inversion layer is Vdssat and electrons that reach the end are swept drain. Increases in Vds have little effect on Ids. 27

  • MOSFET operation analytical (kinda)

    l derive closed form current-voltage equations

    l make some major simplifying assumptions

    l ignore deep sub-micron device physics issues

    l reduce analysis to one dimension

    l called gradual channel approximation

    l also called classic square law model

    l useful for first order approximations

    28

  • MOSFET operation GCA

    Derivation assumptions are that the transistor is in linear mode: Vgs > Vt (so we have inversion and a channel) Vds < Vgs Vt (so the channel extends from source to drain) Vbs = 0, so no body effect modifications of the threshold voltage. Surface mobility is constant across the channel Y is axis starting at the source with 0 and reaching the drain with L So charge at any Y = Q(y) = -Cox (Vgs Vc(y) Vto) and the incremental resistance an any point Y in the channel will increase as you approach the drain.

    29

  • MOSFET operation GCA

    )(1

    yQWdydR

    ln =

    )V (y)V (V C- Q(y) tocgsox=

    c

    Vds

    lnLd dVyQWdyI =

    00

    )(

    )(yQWdyIdRIdV

    ln

    dd

    ==

    30

  • MOSFET operation GCA

    [ ]20)(22

    dsdstgsoxn

    d VVVVLWC

    I

    =

    oxn Ck = 'LW

    Ck oxn =

    [ ]20)(2 dsdstgsoxnd VVVVCWLI =

    31

  • MOSFET operation GCA

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