The MOS Transistor - UTEP · MOS Transistor Gate ... 1.200 1.400 1.600 1.800 2.000 ... threshold...

The MOS Transistor

Prof. MacDonald

1

MOS Capacitor

Si Wafer – P type

poly silicon or metal gate

gate oxide

Vg

Vb

2

MOS Capacitor – Fermi level review

qEE if

F−

=φ

a

iFp

Nn

qkt ln•=φ

i

dFn

nN

qkt ln•=φ

Ec

Ev

Ei

Efp

3

Energy Band Diagrams Separate

Metal Oxide Semiconductor

Eo

Efm Ec

Ev

Ec

Ev

Ei

Efp

qχ = 4.15ev qΦm = 4.1eV qχ oxide = 0.95eV

4

Energy Band Diagrams contacted


Surface potential is smaller than bulk potential. Meaning that near the oxide the silicon is almost intrinsic – less carriers. 5

Energy Band Diagrams contacted


A built-in voltage drop exists because of differences in metal/silicon work function. Known as flat band voltage 6

MOS Capacitor – flat band voltage

Si Wafer – P type


gate oxide

Vg = qΦm – qχ = -0.8V

Vb = gnd = 0v

7

Energy Band Diagrams Under Bias – flat band


Surface potential is identical to bulk because of negative applied voltage. Same number of carriers across silicon now.

8

MOS Capacitor – Accumulation

Si Wafer – P type


gate oxide

Vg < qΦm – qχ = -0.8V

Vb = gnd = 0v

Eox ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

9

Energy Band Diagrams Under Bias – accumulation


Surface potential even more P type than bulk. More carriers (holes) available at surface near oxide.

flat band voltage

applied voltage

10

MOS Capacitor – Depletion

Si Wafer – P type


gate oxide

Vg > 0 V

Vb = gnd = 0v

Eox

depletion region

11

Energy Band Diagrams – depletion


Surface depleted. Holes are pushed away from surface leaving negatively charged fixed ions. No mobile carriers in depletion region.

small positive applied voltage

12

MOS Capacitor – Inversion

Si Wafer – P type


gate oxide

Vg >> 0 V

Vb = gnd = 0v

Eox

depletion region - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

As voltage increases, inversion occurs and electrons gather near the surface. This sheet of electrons shields further depletion, so depletion width (xd) remains constant. Surface becomes N type. 13

Energy Band Diagrams inversion


When surface is as N type as bulk is P type, we have inversion. Ultra thin layer of electrons, free to transport charge.

small positive applied voltage

14

MOS Capacitor – depletion depth

Si Wafer – P type


gate oxide

Vg >> 0 V

Vb = gnd = 0v

Eox


Depletion distance is important when calculating MOS threshold voltages later.

Xd =

a

fssi

Nq •Φ−Φ•• ε2

15

MOS Capacitor – depletion charge

Si Wafer – P type


gate oxide

Vg >> 0 V

Vb = gnd = 0v

Eox


With depletion depth and dopant concentration we can calculate Q.

Xd =

fssiNaqQ Φ−Φ••••= ε216

MOS Transistor

Gate

Silicon Substrate

Source Field Oxide

Drain Field Oxide

gate terminal

drain terminal source terminal

substrate terminal typically tied to ground for PWELLs and Vdd for NWELLs 17

MOS Transistor

Gate

Silicon Substrate

Source Field Oxide

Drain Field Oxide

gate terminal


substrate terminal

Device is symmetrical – for NFET drain is defined as node with highest value. With zero bias on Gate, channel is P type and thus two back-back diodes. No conduction between source and drain.

N+ N+ P

18

MOS Transistor

Gate

Silicon Substrate

Source Field Oxide

Drain Field Oxide

gate terminal


substrate terminal

If gate voltage is raised to Vth a N type channel is formed below the gate. This effectively shorts out the back-to-back diodes and allows conduction.

N+ N+

P Depletion Region Inversion Layer

19

Threshold Voltage


When surface is as N type as bulk is P type, we have inversion. The applied voltage is called the threshold voltage – Vth .

qVt

20

Threshold Voltage

l  Four components of the Vt

–  work function difference (flat band voltage) l  -0.8 V for aluminum gate to P type silicon

–  gate voltage component to change surface potential –  gate voltage component to offset depletion charge –  gate voltage component to offset fixed charge

ox

ox

ox

bFgct

CQ

CQ

V −−Φ•−Φ=02

21

Threshold Voltage with substrate bias

l  Source to Substrate bias affects Vt

l  Referred to as the “body effect” l  used in the early eighties to raise Vt in NMOS l  now subject of research in variable threshold devices l  gamma is the body effect coefficient l  affects performance of stacked transistors (more later…)

€

Vt =Vt0 + γ • −2•φf +Vsb − 2•φ f( )

ox

sia

CNq ε

γ•••

=2

22

Make sure to get the subscript correct for the body to source voltage. The book uses one polarity and IBM used another so I can use either… Just saying. Sorry.

Interview question

MOSFET operation - qualitative

l  over-simplified view of MOSFET behavior l  Useful for back-of-the-envelope calculations l  Three main “modes” of operation

–  Off –  Linear –  Saturation

l  Ignores short channel effects of new small geometries

23

MOS Transistor - off

Gate

Silicon Substrate

Source Field Oxide

Drain Field Oxide

gate terminal = Vg

drain terminal Vd source terminal Vs = 0

substrate terminal Vb = 0

N+ N+

P

if Vgs < Vt, then no inversion layer exists and back-to-back diodes prevent conduction between drain and source regardless of Vds 24

MOS Transistor – Linear mode

Gate

Silicon Substrate

Source Field Oxide

Drain Field Oxide

gate terminal = Vg > Vt

drain terminal Vd = small source terminal Vs = 0


N+ N+

P

if Vgs > Vt and Vds remains small, then inversion layer beneath gate is almost uniform and complete from source to drain. Channel acts as a resistor and Ids increases linearly with Vds. 25

MOS Transistor – Almost saturated

Gate

Silicon Substrate

Source Field Oxide

Drain Field Oxide


drain terminal Vd = Vgs-Vt source terminal Vs = 0


N+ N+

P

if Vds = Vgs – Vt, the inversion layer begins to disappear at the drain end of the channel. This is the transition point from linear mode to saturation mode. 26

MOS Transistor –saturated

Gate

Silicon Substrate

Source Field Oxide

Drain Field Oxide


drain terminal Vd > Vgs-Vt source terminal Vs = 0


N+ N+

P

if Vds > Vgs – Vt, the inversion layer disappears near drain. The end of the inversion layer is Vdssat and electrons that reach the end are swept drain. Increases in Vds have little effect on Ids. 27

MOSFET operation – analytical (kinda)

l  derive closed form current-voltage equations

l  make some major simplifying assumptions

l  ignore deep sub-micron device physics issues

l  reduce analysis to one dimension

l  called gradual channel approximation

l  also called classic square law model

l  useful for first order approximations

28

MOSFET operation – GCA

Derivation assumptions are that the transistor is in linear mode: Vgs > Vt (so we have inversion and a channel) Vds < Vgs – Vt (so the channel extends from source to drain) Vbs = 0, so no body effect modifications of the threshold voltage. Surface mobility is constant across the channel Y is axis starting at the source with 0 and reaching the drain with L So charge at any Y = Q(y) = -Cox (Vgs – Vc(y) – Vto) and the incremental resistance an any point Y in the channel will increase as you approach the drain.

29


)(1

yQWdydR

ln ••−=

µ

)V– (y)V– (V C- Q(y) tocgsox=

c

Vds

lnLd dVyQWdyI ∫∫ •••−=•

00

)(µ

)(yQWdyIdRIdV

ln

dd

••

•−=•=

µ

30


[ ]20)(22

dsdstgsoxn

d VVVVLWC

I −•−••••

=µ

oxn Ck •= µ'LW

Ck oxn ••= µ

[ ]20)(2 dsdstgsoxnd VVVVCWLI −•−••••−=• µ

31


0

50

100

150

200

250

300

350

400

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

Vgs = 5

Vgs = 4

Vgs = 3

32


[ ]20)(2

tgsoxn

d VVLWC

I −•••

=µ

l  Assume Vds = (Vgs – Vt) for saturation l  Intuitive given end of inversion layer is Vgs-Vt l  However, for high values of Vds,

–  L decreases as well l  Consequently

–  Ids continues to climb for higher values of Vds

33


0

50

100

150

200

250

300

350

400

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

Vgs = 5

Vgs = 4

Vgs = 3

Vds = Vgs - Vt

34

MOSFET operation – channel length modulation

0

50

100

150

200

250

300

350

400

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

saturation current with channel length modulation

ideal (GCA) saturation current

35

Channel Length Modulation

[ ] ( )dstgsoxn

d VVVLWC

I •+•−•••

= λµ 1)(2

20

l  As Vds increases, channel length decreases l  Decrease in L is proportional to sqrt(Vds – Vdssat) l  Lamda is empirically derived coefficient l  Lamda provides Vds influence on Ids in saturation

36

Well Voltage – well ties and body bias

Gate

Silicon Substrate

Source Field Oxide

Drain Field Oxide N+ N+

P

Field Oxide

P+

37

Substrate Bias Effects l  source to bulk voltage affects Vt value via body effect l  gamma is body effect coefficient l  used in early 80’s to artificially raise Vt l  degrades performance of stacked transistors l  subject of research on dynamic Vt

ox

sia

CNq ε

γ•••

=2

NFET PFET Phi F Negative Positive

Gamma Positive Negative

Vsb Positive Negative €

Vt =Vt0 + γ • −2•φf +Vsb − 2•φ f( )

38

Substrate Bias Effects – Vt vs Vsb

0.000

0.200

0.400

0.600

0.800

1.000

1.200

1.400

1.600

1.800

2.000

-1 0 1 2 3 4

Can only forward bias until the source to body diode turns on and holds body voltage.

Vt0

delta Vt

Some use Vbs instead of Vsb Source of confusion

39

body effect – stacked transistors

I4

I2 out

I1

I3 A

A

B

B

NAND gate – work horse of CMOS technology

Second NFET source is not grounded like the well – thus Vbs < 0 (or Vsb >0).

40

intentional body effect – dynamic Vt

Vgs

Ids(log)

100

10-1

10-2

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10

Vtf Vts

Iofff

Ioffs

Ionf

Ions

more Ion = faster

less Ioff = less static power

41

Silicon-On-Insulator – Floating Body

Gate

Silicon Substrate

Source Field Oxide


P

Field Oxide

P+

Field Oxide

floating body

42

Silicon-On-Insulator

l  SOI advantages –  less junction capacitance - faster / less dynamic power –  radiation hardened (original motivation in the 70’s) –  dynamic Vt (maybe)

l  SOI disadvantages –  dynamic Vt

l  complexity for simulation l  history and Kink effect

l  Intel has disdain l  IBM, AMD, Motorola embrace

43

Silicon-On-Insulator – Radiation Hardened

Gate

Silicon Substrate

Source Field Oxide


P

Field Oxide

P+

Field Oxide

floating body

+ - + -

+ - + -

alpha particles – space and high altitude

44

Silicon-On-Insulator – body contact

active area

T gate poly

N+ N+

P+

source

body contact

drain

Only use body contact for transistors that must have steady threshold voltage – like PLL and analog circuits. Doubles the size of transistor. 45

Strained Silicon

l  Strained silicon is new process to enhance carrier mobilities l  Add dopant that is mechanically close but slightly different from

Silicon to cause strain l  IBM / Intel reported just started production in the 90nm process

from IBM webpage 46

Measurement of Transistor Parameters

l  On wafer – between die – scribe structures –  serpentine metal to check metallization and vias –  transistors to check performance and leakage –  capacitors to check gate oxide integrity

l  For transistors basic checks –  K –  Vt –  Ids –  Leff –  Weff –  tox

47


Vbs

Vgs = Vds

sqrt(I)

Vgs

slope of line= sqrt(K/2) can get Leff, Cox from this

Zero intercept of Vbs = 0 line is Vto

Second zero intercept provides the second Vt and thus body effect coefficient.

20)(

2tgs

oxnd VV

LWC

I −•••

=µ

48


Vds

Ids

Vds

Vgs

[ ] ( )dstgsoxn

d VVVLWC

I •+•−•••

= λµ 1)(2

20

49


Vds

VQ

tA

Cox

oxox =

•=

ε

50

Transistor Performance monitor

Ring Oscillator – captures most aspects of process that affect performance – drive current, metal and via resistance.

time

0 1 0

51

MOSFET Scaling

l  As Moore’s law predicts –  dimensions decrease by factor S –  area decreases by S2

l  Two forms of scaling –  constant voltage - up to the early 90’s – 5V Vdd steady –  constant electric field – after early 90’s – Vdd drops

l  Why scale CMOS –  faster if smaller (drive current = 1/Leff) –  cheaper if transistors take less area –  more functionality if same area is used with more transistors

52

Rough timeline

Node Year Tox Comment 20u 60’s 1u no CMOS – just NMOS (+/- 5V) 2u early 80’s CMOS, but some NMOS 1u late 80’s All CMOS, +5V 0.8u 92 250A 5V – start of my career 0.65u 94 200A 5V 0.5u 96 150A 5V – start of E scaling 0.35u 98 105A 3.5V – 5V tolerant 0.25u 00 50A 2.5V – 3.3V tolerant 0.18u 01 37A 1.8V – 3.3V tolerant 0.12u 02 27A 1.5V 90nm 03 ? 1.2V 65nm 05 ? ? 45nm 08 ? ? 35nm 10 new ? ? ? Quantum Dot Computers? Not! 53

MOSFET Scaling – Constant Voltage

Quantity Before After Effect Channel Length L L' = L/S Channel Width W W' = W/S Gate oxide thickness Tox t'ox= tox/S Junction Depth Xj X'j = Xj/S Vdd Vdd Vdd Threshold voltage Vt Vt Doping Na,Nd NaS, NdS Gate Capicitance (per area) Cox C'ox = CoxS Total Gate Cap Cg C'g = Cg/S faster and less power Drive current Ids Ids*S faster

Power (for same function) P P*S same circuit scaled consumes

less power

Power density P/A (P*S)/(A/S2)=S so more power per function Device Delay D = CV/I D'= D/S2 Much faster than before Wire Delay RC R*S * (C/S) = RC Really gets bigger 54

MOSFET Scaling – Constant Field

Quantity Before After Effect Channel Length L L' = L/S Channel Width W W' = W/S Gate oxide thickness Tox t'ox= tox/S Junction Depth Xj X'j = Xj/S Vdd Vdd Vdd/S for reliability reasons Threshold voltage Vt Vt/S not done in practice - leakage Doping Na,Nd NaS, NdS Gate Capicitance (per area) Cox C'ox = CoxS Total Gate Cap Cg C'g = Cg/S faster and less power Drive current Ids Ids/S

Power (for same function) P P/S2 same circuit scaled consumes

less power

Power density P/A (P/S2)/(A/S2) so same power for more

function

Device Delay D = CV/I D'= D/S Faster but not as fast as CV Wire Delay RC R*S * (C/S) = RC really gets bigger 55

MOSFET Scaling

l  Considerations –  Leff min proportional to (all you need to know about devices)

l  Xj – requires precise implantation and anneal l  N – affects the mobilities of carriers if too high – cap if too low l  Tox - below 20 angstroms – tunneling leakage

–  gate oxide electric field intrinsic breakdown at 10 MV/cm l  this sets the max Vdd for a given technology

–  thresholds need to be scaled l  but every 80mVs reduced, leakage increases X10

56

MOSFET Scaling – current issues

l  Static Power – Major problem –  no static power was original motivation for CMOS –  gate oxides are 17 Angstroms – tunneling 1 Amp / cm

l  need new oxide that acts electrically thin but physically thick l  silicon used because of nice native oxide with good interface

–  sub-threshold leakage increased due to scaled Vts l  using dual threshold processes, but this adds expense

l  Wire Delay –  need low K material for inter-layer dielectric

l  current materials are having mechanical reliability issues l  thermal cycle the chips and get opens/shorts

–  need low resistance conductors l  migrating from aluminum to copper (Intel last to go, IBM first) l  but copper is difficult to etch – dual damascene process 57

MOSFET Scaling – current issues

l  Source / Drain series resistance –  Junction depths need to be ultra thin and this raises R

l  Channel and well doping needs to be increased –  This reduces depletion depth and improves SCE –  but also reduces mobilities of carriers (strained silicon?) –  also increases junction capacitance (SOI to the rescue)

l  more junction cap slows down transistor l  and results in more dynamic power

58

Short Channel Effects

)(2

0tgsoxn

d VVLWC

I −•••

=µ

l  Transistor is a short channel transistor when… –  Leffs = Xj - junction depth or –  Leffs = Xd – depletion depth

l  Vt roll-off –  thresholds affected by leff when too small –  manufacturing with a Gaussian distribution for Leff

l  Drift Velocity –  Ids equations do not correctly reflect empirical data

59

Short Channel Effects – Vt roll off

Leff

targeted Leff

Vt distribution

conflicting need for Leff reduction - lower Leff provides more performance - lower Leff risks leaky, low Vt devices

60

Transistor Reliability Issues – Hot Electrons

Gate

Silicon Substrate

Source Field Oxide


P

In Saturation, depletion “pinch-off” region has very high electric fields. Electrons swept across this region occasionally collide with lattice elements and result in “hot electrons” which have enough energy to jump into the oxide. Consequently, the electrons fix negative charge in the gate dielectric and affect the threshold voltage. This results in long term performance degradation if the transistor is frequently run in the saturated mode with large currents (cold temps). 61

Metallization Reliability – Electromigration

l  “Electron wind” can break metal lines –  momentum transfer between electrons and diffusing metal –  compounded by high temperature and large currents –  grain size of aluminum affects electromigration –  DRC for metal lines with big current densities (e.g. IOs)

62

Reliability - Contamination

l  Most defects are the result of contamination

l  Can be latent in nature – activating in the field

l  Can result in shorts, opens or stuck-at faults

l  Defined by number of particles in cubic foot 63

Gate Oxide Integrity

l  Very thin oxides can have pin holes l  Pin holes can become significant shorts over time l  Most common defect and major reliability issue

64

Oxide Capacitance – Cut off

Gate

Silicon Substrate

Source Field Oxide


P

Oxide capacitance is mainly from gate to substrate when transistor is off.

ox

oxgs

tLW

Cε••

=

65

Oxide Capacitance – Source Drain Overlap

Gate

Silicon Substrate

Source Field Oxide


P

Oxide capacitance is always present between gate and both source and drain although this cap tends to be small.

ox

oxdgs

tLW

Cε••

=66

Oxide Capacitance – Linear Mode

Gate

Silicon Substrate

Source Field Oxide


P

Oxide capacitance is split between Cgs and Cgd in linear mode. Substrate is shielded by inversion layer. Also includes small overlap capacitance.

ovox

oxdsgs C

tLW

CC +••

•= =ε

21

67

Oxide Capacitance – Saturation Mode

Silicon Substrate

Source Field Oxide


P

Oxide capacitance is to incomplete inversion layer which provides a connection to the source only. Gate to drain cap is limited to overlap only.

ovox

oxgs C

tLW

C +••

•=ε

32

68

Oxide Capacitance – Summary

Capacitance Cut- Off Linear SaturationCgb Cox*W*L 0 0

Cgd Cox*W*Ld

1/2Cox*W*L + Cox*W*Ld Cox*W*Ld

Cgs Cox*W*Ld

1/2Cox*W*L+ Cox*W*Ld

2/3*Cox*W*L + Cox*W*Ld

69

Oxide Capacitance – Summary

Vt Vt + Vds

Vgs

oxide cap

70

Oxide Capacitance – Saturation Mode

Silicon Substrate

Source Field Oxide


P

Junction cap is all bad - adding to the load capacitance. The junction cap goes up with the area of the source and drain diffusion, the underlying well doping level and the voltage that is reverse biasing the junction. SOI virtually eliminates this capacitance.

71

Temperature Effects on Transistors

Transistors get leakier when heated. Old (0.8u) rule of thumb is 2X leakage for 11 degree increase (F). Vts drop and subthreshold slope decreases.

Vgs

Ids(log)

100

10-1

10-2

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10

Vtf Vts

Iofff

72

Temperature Effects on Transistors

l  Transistors slow down with temperature –  Vts go down (increasing drive current), but –  mobilities drop more significantly

l  Consequently, chips speeds rated at max temp. –  your 2.4 GHz Pentium, will run close to 3GHz at room temp –  but remember that the chip is hotter than the ambient

l  Very low temperatures can cause problems also –  chips speed up too much and race conditions occur. –  hold time violations –  Space electronics

73

Vdd Effects on Transistors

l  Speed of transistors increases with Vdd2

l  Dynamic power consumption increases with Vdd2

l  Max Vdd is set by gate oxide breakdown –  intrinsic breakdown is 10 MV/cm –  for 20 angstroms, Vddmax = 10 MV/cm * 20e-8cm = 2.0 V –  for 100 angstroms, Vddmax = 10V –  generally never exceed 60% of max

l  Increasing Vdd increases leakages also l  Minimum Vdd = Vtn + Vtp to ensure at least one

transistor in will be conducting.

staticPVFCP +••= 274

Other observations

Vdd Vdd

Vdd-Vt

NFETs can’t drive high voltages well

PFETs can’t drive low voltages well Vt

This will affect many of the circuits that we explore in this class and this is a major source of interview questions (and exam questions). 75

The MOS Transistor - UTEP · MOS Transistor Gate ... 1.200 1.400 1.600 1.800 2.000 ... threshold...

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Transcript of The MOS Transistor - UTEP · MOS Transistor Gate ... 1.200 1.400 1.600 1.800 2.000 ... threshold...