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Transcript of Template MS-Word .Web viewΣχήμα 2. 1:Τρεις βασικές λογικές πύλες:...

Template MS-Word 2013

: VLSI

2: .. MOS

.

1. .. MOS.4

2.DC .5

3. 11

4. 12

5. MOS 14

6. MOS.17

6.1 AND-OR.17

6.2RS Flip-Flops18

6.3Latches18

6.4D Flip Flops (shift registers)19

6.5 (Exclusive OR)20

7. 20

7.1 RAM21

7.2 RAM23

13

.. MOS.

.. , , . .. MOS MOS . . MOS , . 2.1 , .

2. 1: : , NAND & NOR.

. 0 ( ), . 1 ( VDD), . , 1, 0.

, , NAND 0 1. , NOR 0 1. NAND 0 . (enabling), 1. . NOR, 0.

. 2.1 . , 0 1.

, , . , . DC (transient) .

DC .

. 2.2 , . CMOS, . , MOS , .

2. 2: MOS

2. 3: .

.

. 2.3. . 2.4 , , . 0 1, VDS ( VDD) . . 2.5. VT, . 1, 0. , 0 , .

:

(2.1)

0 RL :

(2.2)

2. 4: .

MOS

2. 5: .

MOS , W/L IDS , 10 20 . 2.6, . MOS .

2. 6: MOS .

2. 7: R.

2.7. VDD VT. , VT VT. R=(W/L)/(W/L) (2.3), 0 .

MOS , .

VDD, . 2.8.

2.9 . VDD. , 0 , . , R .

2. 8: .

2. 9: I-V.

MOS .

. 2.10.

VDD , . , .

2. 10: MOS .

0 Volts VT, . . VT , . . . .

2. 11: CMOS.

CMOS

.

2. 12: .

I. ( )

P . ,

II. ( ),

P . ,

III. ( )

P ,

IV. ( )

P , .

V. VDD-VTPVin VDD ( ).

P , .

, . DC , 2.13. . 0 1. , . Vin=Vout. R 0 .

NAND 0 1, . W/L.

2. 13: .

, 0, . , . (transient analysis).

2.15, . , .

2. 14:

2. 15:

2. 16: .

, 1 0, . VDD (risetime). . MOS , VDD-VT, , VDD ( 2.14). , , , . RC. .

, . 0 1, . , . . 1 0. 2.16. 2.14, , W/L 10 .

. . . , . , 50%. 2.17. tpd- tpd+ .

2. 17: .

MOS

MOS . , .

2. 18: MOS .

2.18 NMOS, (W/L=1) -n. , , . Cout , Vout.

. 0, Vin Vout. , Vout . Cout , 0 .

1, Vp, Vin Vout. .

1) Vin=0 Vout=0

VDS=0 Vout 0.

2) Vin=Vp Vout=0

Vin Vout, Vout Cout. (D) (S). VGS Vp - Vout VGS-VT=0. NMOS MOS . , Vout , Vout 3,12 Volts Vp 5 Volts.

3) Vin=Vp Vout=Vp-VT

VGS-VT=0. Vout Vp-VT.

4) Vin=0 Vout=Vp-VT

Vout Vin Vout 0. . VGS , Vout ().

. . , . , NMOS . 18.

, Cout, . , , 0. ( 5 kHz), .

. Vp Vp-VT. CGS, . CGS Cout , 2.17.

2. 19:

Vout . H CGS L=W=6m 0,0025pF Cout

0,1pF Vout . , 5Volts , 0,12Volts Vout 3Volts .

CMOS

2.20 NMOS, VTN PMOS, VTP, . .

2. 20:

1 . :

1) Vin=0V, Vout=0V

VDS=0 Vout 0 Volts.

2) Vin=Vp, Vout=Vp

K VDS=0 .

Vp.

3) Vin=Vp , Vout=0V

Vin NMOS PMOS.

Vin Vout Cout. VGS PMOS

Vp , VGS NMOS Vp

Vout . Vout=Vp-VTN NMOS

Vout Vp PMOS.

4) Vin=0V, Vout=Vp

5) Vin NMOS PMOS. Vout Vin Cout. VGS NMOS Vp , VGS PMOS Vp Vout. Vout=VTP PMOS Vout 0V NMOS.

CMOS (feedthrough) , .

MOS. AND-OR.

2. 21: .

NAND NOR, MOS . . 2.21 : . , . .

RS Flip-Flops

Flip-Flops, .

2. 22:RS flip flop.

2.12 Flip-Flop, RS (Reset-Set) Flip-Flop. MOS NOR . R S 0, Q . R 1 Flip-Flop reset () . Q 0 1. S 1, Flip-Flop set (), . Q 1 0. R S 1 Q 0. Q .Latches

2.23 , Q D CLK 1. 0 Flip-Flop 1. . 2.23 .

2. 23: Latch.

D Flip Flops (shift registers)

2. 24:(a) D flip flop, (b) .

Flip Flop D . 2.24(). 1 1 2 0. , . . 1 0 2 1 , . , L . , 1 2 . 1.

D Flip Flops . . STORE 1 . STORE 0, . .

(Exclusive OR)

2. 25: exclusive OR.

1 1. 2.25. :

2.25. 1 .

. , . . MOS, .. .

RAM (Random Access Memory= ).

RAM, bit ( 1 0) . . . bits. RAMs .

RAM

2. 26: RAM

.

RAM . 2.26 . , (word line) ( ) Q1 Q6, BIT Flip Flop. Flip Flop. BIT (WRITE). 0 Flip Flop .

RAM 16-bits . 2.27.

2. 27: RAM 16-bits.

, . bits (0 1) (WL). bits (2 3) bit. (WRITE), , DI bit BSC Flip Flop . (READ), , BSC . 2.27 , DC DO.

WE (write enable= ), (WRITE) (READ) CE (chip enable), 1 (sense) .

RAM

RAM . , msec.

2. 28: RAM.

2.28 , . (word line), Bit (Bit line), . Bit. (sense). , . , . . .

(. 2.28b). () MOS. (CCD).

, 100fF, . .., .. . - MOS. . - . , . .

1.0

Copyright , , 2014. . . . 2: .. MOS . : 1.0. 2014. : http://opencourses.uoa.gr/courses/DI31/.

Creative Commons , 4.0 [1] , . .. , ..., .

[1] http://creativecommons.org/licenses/by-nc-sa/4.0/

:

,

(.. )

, .

:

( )

.

:

///

2.1 2.17 : Original from: R. Colclaser. Microelectronics Processing and Device Design. New York, NY: John Wiley & Sons, 1980.

2.21 2.28 : Original from: R. Colclaser. Microelectronics Processing and Device Design. New York, NY: John Wiley & Sons, 1980.

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